Re: [Mesa-dev] [PATCH 1/3] vl/dri3: use external texture as back buffers(v4)

On 10/01/17 06:53 PM, Nayan Deshmukh wrote: > On Sat, Jan 7, 2017 at 12:42 PM, Michel Dänzer wrote: >> On 06/01/17 05:50 AM, Andy Furniss wrote: >>> Christian König wrote: Am 04.01.2017 um 18:13 schrieb Nayan Deshmukh: > dri3 allows us to send handle of a texture

Re: [Mesa-dev] [PATCH] glsl: always do sqrt(abs()) and inversesqrt(abs())

W dniu 10.01.2017 o 18:48, Jason Ekstrand pisze: Hi, Can we add workaround to drirc and enable this only when needed? Best Regards Krzysztof Cybulski I'll be honest, I'm not a fan... Given that D3D10 has one defined behavior, D3D9 has another, and GL doesn't specify, I don't really think we

Re: [Mesa-dev] [PATCH 04/22] i965/fs: add lowering step to duplicate sources with stride 0.

Hi Matt, Matt Turner writes: > On Sun, Jan 8, 2017 at 10:53 PM, Matt Turner wrote: >> On 01/05, Samuel Iglesias Gonsálvez wrote: >>> >>> From: "Juan A. Suarez Romero" >>> >>> When dealing with DF uniforms with just 1 component, we

Re: [Mesa-dev] [PATCH 1/3] vl/dri3: use external texture as back buffers(v4)

On 10/01/17 09:07 PM, Andy Furniss wrote: > Andy Furniss wrote: > >> Though recent testing shows this is not true with DAL/DC on 3.7 - >> todo test DC on new drm-next branch. > > todo done, DC for some reason on both amd-staging-4.7 and > amd-staging-drm-next is "slower" = the tear region is 2

Re: [Mesa-dev] [PATCH 04/11] i965/vec4/nir: vec4 also need to remap vs attributes

On 01/09, Juan A. Suarez Romero wrote: From: Alejandro Piñeiro Doubles need extra space, so we would need to do a remapping for vec4 too in order to take that into account. We reuse the already existing remap_vs_attrs, but passing is_scalar, so they could remap

Re: [Mesa-dev] [PATCH 04/22] i965/fs: add lowering step to duplicate sources with stride 0.

On Sun, Jan 8, 2017 at 10:53 PM, Matt Turner wrote: > On 01/05, Samuel Iglesias Gonsálvez wrote: >> >> From: "Juan A. Suarez Romero" >> >> When dealing with DF uniforms with just 1 component, we set stride 0 to >> use the value along the operation.

[Mesa-dev] [Bug 92634] gallium's vl_mpeg12_decoder does not work with st/va

https://bugs.freedesktop.org/show_bug.cgi?id=92634 Reuben changed: What|Removed |Added CC||reube...@yahoo.com -- You

[Mesa-dev] [PATCH] util: fix list_is_singular()

Currently its dependant on the user calling and checking the result of list_empty() before using the result of list_is_singular(). --- src/util/list.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/util/list.h b/src/util/list.h index e8a99ac..07eb9f3 100644 ---

Re: [Mesa-dev] [PATCH 3/3] anv: Support loader interface version 2

On Tue, Jan 10, 2017 at 7:17 PM, Chad Versace wrote: > Loader interface v2 differs from v1 in that the first ICD entrypoint > called by the loader is vk_icdNegotiateLoaderICDInterfaceVersion(), not > vk_icdGetInstanceProcAddr(). The ICD must statically expose this >

Re: [Mesa-dev] Updating vk_icd.h

On Tue 10 Jan 2017, Jason Ekstrand wrote: > I thought for sure we supported at least v2...  In any case, go for it. No. We only supported v1. And I just sent patches to support v2. Dave, I tested that I didn't break the radv build. But you should probably double-check for me.

[Mesa-dev] [PATCH 2/3] vulkan: Update vk_icd.h to interface version 3

Import from commit f2aeefec on branch 'master' of https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers. --- include/vulkan/vk_icd.h | 110 ++-- 1 file changed, 78 insertions(+), 32 deletions(-) diff --git a/include/vulkan/vk_icd.h

[Mesa-dev] [PATCH 3/3] anv: Support loader interface version 2

Loader interface v2 differs from v1 in that the first ICD entrypoint called by the loader is vk_icdNegotiateLoaderICDInterfaceVersion(), not vk_icdGetInstanceProcAddr(). The ICD must statically expose this entrypoint. --- src/intel/vulkan/anv_device.c | 43

[Mesa-dev] [PATCH 0/3] anv: Support loader interface version 2

I tested this by: - Running vkcube on Wayland with an older Vulkan loader 1.0.30, as shipped by Arch Linux. - Running vkcube on Wayland with a Vulkan loader built from today's master at commit 82a2c181e32f4bc. - Running 'dEQP-VK.wsi.xlib.*'. All 33 tests passed. I also checked that

[Mesa-dev] [PATCH 1/3] vulkan: Add new cast macros for VkIcd types

We can't import the latest vk_icd.h because the new header breaks the Mesa build. This patch defines new casting macros, ICD_DEFINE_NONDISP_HANDLE_CASTS() and ICD_FROM_HANDLE(), which can handle both the old and new vk_icd.h, and will prevent the build from breaking when we update the header. In

[Mesa-dev] [PATCH] nouveau: take extra push space into account for pushbuf_space calls

Ever since a long time ago when I messed around with fences, I ensure that after a PUSH_SPACE call there is enough space to write a fence out into the pushbuf. However the PUSH_SPACE macro is not all-knowing, and so sometimes we have to invoke nouveau_pushbuf_space manually with the relocs/pushes

Re: [Mesa-dev] [PATCH 00/11] i965 Haswell ARB_vertex_attrib_64bit / OpenGL 4.2

The docs should be updated in patches 8, 10 and 11. With that, 4-11 Reviewed-by: Jordan Justen On 2017-01-09 09:09:58, Juan A. Suarez Romero wrote: > Hi, > > This series implements the support for Haswell 64bit vertex attributes. With > it, > we can enable OpenGL

[Mesa-dev] [PATCH v2] radv: remove some unused macros and functions

These seem unlikely to be used. Also remove irrelevant comment about SKL. v2: forgot to rebase on master Signed-off-by: Grazvydas Ignotas --- no commit access src/amd/vulkan/radv_private.h | 15 +-- src/amd/vulkan/radv_util.c| 19 --- 2 files

[Mesa-dev] [PATCH v3] gallium/tgsi: fix overflow in parse property

In parse_identifier, it doesn't stop copying '*pcur' untill encounter the NULL. As the 'ret' has a fixed-size buffer, if the '*pcur' has a long string, there will be a buffer overflow. This patch avoid this. Signed-off-by: Li Qiang --- src/gallium/auxiliary/tgsi/tgsi_text.c |

Re: [Mesa-dev] [PATCH 3/3] radv: Call NIR passes using NIR_PASS_V.

Patches 1 & 3 are: Reviewed-by: Timothy Arceri On Wed, 2017-01-11 at 01:29 +0100, Bas Nieuwenhuizen wrote: > Port of faa1edeeb7bbe9321c79587e592dce812e8caa78 > "anv/pipeline: Call NIR passes using NIR_PASS_V" > > Signed-off-by: Bas Nieuwenhuizen

[Mesa-dev] [PATCH] radv: remove some unused macros and functions

These seem unlikely to be used. Also remove irrelevant comment about SKL. Signed-off-by: Grazvydas Ignotas --- no commit access src/amd/vulkan/radv_private.h | 15 +-- src/amd/vulkan/radv_util.c| 19 --- 2 files changed, 1 insertion(+), 33

Re: [Mesa-dev] [PATCH 06/10] amd/common: unify cube map coordinate handling between radeonsi and radv

Unfortunately this one breaks at least (surprise!) texturecubemap SaschaWillemsVulkan demo. I recommend you try it yourself, there are even precompiled binaries available (see README.md): https://github.com/SaschaWillems/Vulkan Gražvydas On Tue, Jan 10, 2017 at 5:12 PM, Nicolai Hähnle

Re: [Mesa-dev] Updating vk_icd.h

I thought for sure we supported at least v2... In any case, go for it. On Tue, Jan 10, 2017 at 2:39 PM, Chad Versace wrote: > I've begun working on updating vk_icd.h to the latest upstream version, > and adding Anvil support for the new interface. Mesa today supports

[Mesa-dev] [PATCH 1/3] radv: Only call remove_dead_variables once.

Port of 43e0b0d4b255d910616c10e3e01bfec5db469e0e "anv/pipeline: Only call remove_dead_variables once" Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_pipeline.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c

[Mesa-dev] [PATCH 2/3] radv: Call nir_lower_constant_initializers.

Port of c5d664f9dc2d281c74844cef36ecb9f5862a8f6a "anv/pipeline: Call nir_lower_constant_initializers" Signed-off-by: Bas Nieuwenhuizen Cc: --- src/amd/vulkan/radv_pipeline.c | 13 + 1 file changed, 13 insertions(+) diff --git

[Mesa-dev] [PATCH 3/3] radv: Call NIR passes using NIR_PASS_V.

Port of faa1edeeb7bbe9321c79587e592dce812e8caa78 "anv/pipeline: Call NIR passes using NIR_PASS_V" Signed-off-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_pipeline.c | 24 +++- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git

Re: [Mesa-dev] Updating vk_icd.h

On 11 Jan. 2017 08:39, "Chad Versace" wrote: I've begun working on updating vk_icd.h to the latest upstream version, and adding Anvil support for the new interface. Mesa today supports loader interface v1; the latest interface is v3. I don't want to duplicate work that

[Mesa-dev] [PATCH 2/3] i965: Fix indentation in brw_miptree_layout_2d()

Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index bf8c338..2f4837e 100644 ---

[Mesa-dev] [PATCH 1/3] i965: Fix comment to include 3d textures

Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 768f8a8..bf8c338 100644 ---

[Mesa-dev] [PATCH 3/3] i965: Remove unnecessary mt->compressed checks

It's harmless to use ALIGN_NPOT() for uncompressed formats because they have block width/height = 1. Signed-off-by: Anuj Phogat --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] anv: implement pipeline statistics queries

ping. On Thu, Dec 22, 2016 at 11:14 AM, Ilia Mirkin wrote: > Ping? Any further comments/feedback/reviews? > > > On Dec 5, 2016 11:22 AM, "Ilia Mirkin" wrote: > > On Mon, Dec 5, 2016 at 11:11 AM, Robert Bragg wrote: >> >> >> On

[Mesa-dev] Updating vk_icd.h

I've begun working on updating vk_icd.h to the latest upstream version, and adding Anvil support for the new interface. Mesa today supports loader interface v1; the latest interface is v3. I don't want to duplicate work that my already been done. So... Has anyone already completed this on a

Re: [Mesa-dev] [PATCH 05/22] i965/fs: consider execsize can be duplicated in lower_simd_with

"Juan A. Suarez Romero" writes: > On Mon, 2017-01-09 at 15:41 -0800, Francisco Jerez wrote: >> Samuel Iglesias Gonsálvez writes: >> >> > From: "Juan A. Suarez Romero" >> > >> > In IVB/VLV, for instructions dealing with DF,

Re: [Mesa-dev] [PATCH v2 03/10] radeonsi: restrict cube map derivative computations to the correct plane

Had some problems to figure out where the factor 2 came from, but in the end, this series is Reviewed-by: Bas Nieuwenhuizen On Tue, Jan 10, 2017 at 5:35 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > As remarked by

[Mesa-dev] [Bug 98002] Mud rendering bug in Portal 2

https://bugs.freedesktop.org/show_bug.cgi?id=98002 Luke changed: What|Removed |Added CC||lukebe...@hotmail.com --

Re: [Mesa-dev] [PATCH 06/22] i965/fs: double-precision execution does not use 2 channels per DF in IVB/VLV

Samuel Iglesias Gonsálvez writes: > On Mon, 2017-01-09 at 16:18 -0800, Francisco Jerez wrote: >> Samuel Iglesias Gonsálvez writes: >> >> > From: Iago Toral Quiroga >> > >> > It seems to use 1 channel por DF, just like later

Re: [Mesa-dev] [PATCH] glsl: always do sqrt(abs()) and inversesqrt(abs())

On 01/09/2017 10:03 PM, Roland Scheidegger wrote: Am 06.01.2017 um 10:42 schrieb Samuel Pitoiset: D3D always computes the absolute value while GLSL says that the That should probably say "d3d9" - it is completely wrong for d3d10 and later (which have it to be defined as a guaranteed NaN).

[Mesa-dev] [PATCH 17/51] i965: Replace opencoded brw_store_register_mem32()

The gen7 transform feedback routines store the SOL_OFFSET between batches into its scratch buffer. Convert these from using opencoded brw_store_register_mem32() Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/gen7_sol_state.c | 10 +++---

[Mesa-dev] [PATCH 44/51] i965: Pass the map-mode along to intel_mipmap_tree_map_raw()

Since we can distinguish when mapping between READ and WRITE, we can pass along the map mode to avoid stalls and flushes where possible. Signed-off-by: Chris Wilson Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c |

[Mesa-dev] [PATCH 25/51] i965: Move HW context into brw_batch

To reduce churn later, move the HW context variable from brw_context to brw_batch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 2 ++ src/mesa/drivers/dri/i965/brw_context.c | 23 --

[Mesa-dev] [PATCH 40/51] i965: Wrap brw_memory_barrier with begin/end

Or rather export a higher level brw_pipe_control_flush() that wraps the brw_emit_pipe_control_flush() into a batch as appropriate for the caller. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_context.h | 1 +

[Mesa-dev] [PATCH 18/51] i965: Refactor setting a register with an immediate constant

We have a few instances where we set a register to an immediate value (MI_LOAD_REGISTER_IMM), so let's replace them with a simple routine. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw.c | 6 +-

[Mesa-dev] [PATCH 26/51] i965: Refactor batch buffer dumping

Move the computation of the state offset into a smaller helper to reduce churn later. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_state_dump.c | 62 -- 1 file changed, 33 insertions(+), 29 deletions(-) diff --git

[Mesa-dev] [PATCH 14/51] i965: Extract brw_batch_busy()

A simple helper to check whether the last batch buffer submitted to the hardware is still busy. Extract it now to reduce churn later. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 5 + src/mesa/drivers/dri/i965/brw_cs.c| 5 ++---

[Mesa-dev] [PATCH 20/51] i965: Add dword aliases to bitfield structs

When processing the packed fields, it is often much easier to pass around the dword value (as would be seen by hardware) than it is manipulating the bitfield. By aliasing the bitfield with a uint32_t member, we can treat the value as either a collection of bits or a single value depending upon the

[Mesa-dev] [PATCH 49/51] i965: Enable brw-batch dirty tracking

Remove the old hashtable approach and switch over to the inline write tracking with brw-batch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.c | 70 ++- src/mesa/drivers/dri/i965/brw_batch.h | 10 +---

[Mesa-dev] [PATCH 10/51] i965: Add a simple utility function to wrap drm_intel_bo_flink()

Just to reduce some later churn, pull out the flink wrapper. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h| 7 +++ src/mesa/drivers/dri/i965/brw_context.c | 11 +-- src/mesa/drivers/dri/i965/intel_screen.c | 2 +- 3 files

[Mesa-dev] [PATCH 48/51] i965: Use fences for tracking QueryCounters

We can use our fence tracking mechanism for fine-grained waiting on results. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_conditional_render.c | 4 +- src/mesa/drivers/dri/i965/brw_context.c| 2 + src/mesa/drivers/dri/i965/brw_context.h

[Mesa-dev] [PATCH 31/51] i965: Refactor the always_flush check

Provide a common routine for doing conditional batch flushes. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 6 ++ src/mesa/drivers/dri/i965/brw_compute.c | 3 +-- src/mesa/drivers/dri/i965/brw_draw.c| 3 +--

[Mesa-dev] [PATCH 50/51] i965: Coalesce relocation read/write domains to a single integer

There are only a handful of distinct cache domains (less than 16), and internally the kernel simply doesn't differentiate between the GPU cache domains - for recent kernels we just pass in whether the object is being written to (for read/write busyness tracking) and whether it requires the global

[Mesa-dev] [PATCH 41/51] i965: Move all the render preamble together

Rather than split the render batch setup between two hooks, coalesce it into a single callback. To simplify this, move some of the state dirtying from the start to the finish hook hook. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_context.c | 15

[Mesa-dev] [PATCH 37/51] i965: Refactor aperture testing and restarting

Refactor the aperture test, roll back and retry logic to a common idiom. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 18 src/mesa/drivers/dri/i965/brw_compute.c | 36 +++-

[Mesa-dev] [PATCH 15/51] i965: Move pipelined register access to its own file

Move the pipelined register access out of intel_batchbuffer into its own utility file in preparation for replacing intel_batchbuffer. This also gives us the opportunity to refactor a few similar routines for writing registers, and so should prove useful in its own right. Similarly there is a

[Mesa-dev] [PATCH 28/51] i965: Pass can-use-active flag to brw_bo_create()

The introduction of brw_bo_create() allows us to pass a new flag down when creating a linear buffer to allow the allocator to return a currently active buffer. (Previously all linear buffers were presumed to be allocated for CPU access and so the allocator only returned an idle buffer.)

[Mesa-dev] [PATCH 47/51] i965: Allow syncobjects to hook into the internal fence tracking

Since we use fences internally for tracking buffer busyness within brw_batch.c, we can expose those directly for GL/DRI2 sync objects. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.c | 87 -- src/mesa/drivers/dri/i965/brw_batch.h

[Mesa-dev] [PATCH 22/51] i965: Refactor batch flush into intel_front_flush()

Since we always flush the intel_batchbuffer before calling intel_front_flush(), simply more that call into intel_front_flush() itself. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_context.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-)

[Mesa-dev] [PATCH 45/51] i965: Remove use of deprecated drm_intel_aub routines

With mesa/drm commit cd2f91e18db087edf93fed828e568ee53b887860 Author: Kristian Høgsberg Kristensen Date: Fri Jul 31 10:47:50 2015 -0700 intel: Drop aub dumping functionality the drm_intel_aub routines are mere stubs and do nothing. Likewise remove our

[Mesa-dev] [PATCH 27/51] i965: Move brw_bo creation to brw_batch.h

Churn now to reduce churn later. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h| 34 + src/mesa/drivers/dri/i965/brw_binding_tables.c | 3 +- src/mesa/drivers/dri/i965/brw_context.c | 3 +-

[Mesa-dev] [PATCH 43/51] i965: Unconditionally reset the HW binding table offsets after a batch

Rather than spend an instruction deciding whether we need to, just zero out the single integer to reset the HW binding tables. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 6 -- src/mesa/drivers/dri/i965/brw_context.c| 3

[Mesa-dev] [PATCH 39/51] i965: Convert brw_emit_mi_flush() to use batch begin/end

We have many flushes outside of the batch buffer critical sections that need wrapping. Introduce a simple function to wrap the brw_emit_mi_flush() with the begin/end. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_clear.c| 4 +--

[Mesa-dev] [PATCH 38/51] i965: Wrap all instances of batch buffer access in begin/end

In order to track aperture usage correctly and flush the batch at safe transition points, we need to wrap all batch buffer access in begin/end introduced in the previous patch. Note, this patch doesn't quite transform everything - we leave the small flushes to a later refactor. Signed-off-by:

[Mesa-dev] [PATCH 42/51] i965: Pack a couple of batch booleans into a flags field

The flags field becomes more useful later as we store more bits in it, but for now we can start it off with the pair of boolean state already stored inside batch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 5 +++--

[Mesa-dev] [PATCH 32/51] i965: Set buffer dirty flags for this batch

Process the postdraw resolves (including setting the buffer dirty flag) before any conditional batch flush as that flush will want to clear the dirty flag. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw.c | 6 ++ 1 file changed, 2 insertions(+),

[Mesa-dev] [PATCH 11/51] i965: Wrap drm_intel_bo_madvise() for brw_bo

To reduce later churn, extract drm_intel_bo_madvise() with a smaller wrapper. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h| 5 + src/mesa/drivers/dri/i965/brw_object_purgeable.c | 4 ++-- 2 files changed, 7 insertions(+), 2

[Mesa-dev] [PATCH 21/51] i965: Refactor adding relocations into the batch buffer

It is essential that the value we write into the batch buffer matches the value we record in the relocation entry (and that value also corresponds with the presumed offset the target buffer). To ensure this is true we combine adding relocation entry to the batch buffer with recording the target

[Mesa-dev] [PATCH 35/51] i965: Convert some intel_batchbuffer prototypes over to brw_batch

Just to ease the next intermediate patch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 1 + src/mesa/drivers/dri/i965/brw_compute.c | 6 +-- src/mesa/drivers/dri/i965/brw_draw.c | 7 ++--

[Mesa-dev] [PATCH 33/51] i965: Move RESERVED_SPACE from intel_batchbuffer.h to brw_batch.h

Simple non-functional change to ease later patches. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 26 ++ src/mesa/drivers/dri/i965/intel_batchbuffer.h | 26 -- 2 files changed, 26

[Mesa-dev] [PATCH 19/51] i965: Simplify parameters to brw_emit_pipe_control_write()

Rather than passing the uint64_t value to write as a pair of high/lo uint32_t values, place the burden on the callee to split the large value into the dwords desired by the hardware. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_context.h | 3 +--

[Mesa-dev] [PATCH 34/51] i965: Move no_batch_wrap from brw_context to brw_batch

To ease intermediate patches. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 2 ++ src/mesa/drivers/dri/i965/brw_compute.c | 4 ++-- src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_draw.c

[Mesa-dev] [PATCH 06/51] i965: Subsitute drm_intel_bo with a local name, brw_bo

In preparation for a local batch manager with a new buffer object, first reduce the churn by renaming the existing buffer objects: s/drm_intel_bo/brw_bo/ We only have to be careful to leave the global screen drm_intel_bo as they are. Signed-off-by: Chris Wilson ---

[Mesa-dev] [PATCH 29/51] i965: Extract batch start/finish hooks

In order to reduce future churn, move the callbacks for starting and finishing the batch from intel_batchbuffer to the brw_context. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_context.c | 83 +++

[Mesa-dev] [PATCH 51/51] i965: Request batch promotion when using mmio commands

We only need the batch promotion if we need to modify privileged registers, so only request it when we do register loads and stores. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.c | 7 ++- src/mesa/drivers/dri/i965/brw_batch.h

[Mesa-dev] [PATCH 07/51] i965: Move struct intel_batchbuffer from brw_context.h to brw_batch.h

To ease future transitions. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 32 src/mesa/drivers/dri/i965/brw_context.h | 32 2 files changed, 32 insertions(+), 32 deletions(-)

[Mesa-dev] [PATCH 30/51] i965: Introduce a perf_debug() hook for flushing the intel_batchbuffer

If we have to flush the batchbuffer early that has performance implications, and if it is a result of user action we should report that through the perf_debug interface. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h| 3 ++

[Mesa-dev] [PATCH 36/51] i965: Move a few intel_batchbuffer functions to brw_batch

In preparation for the next patch, just transplant some functions between header files. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 17 + src/mesa/drivers/dri/i965/intel_batchbuffer.h | 18 -- 2 files

[Mesa-dev] [PATCH 12/51] i965: Move the render_cache dirty set from the context to the batch

To reduce churn later, move the brw->render_cache dirty set into the batch (i.e. brw->batch.render_cache). Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 7 +++ src/mesa/drivers/dri/i965/brw_context.h | 7 ---

[Mesa-dev] [PATCH 02/51] i965: Order write of query availablity with earlier writes

Currently we signal the availabilty of the query result using an unordered pipe-control write. As it is unordered, it may be executed before the write of the query result itself - and so an observer may read the query result too early. Fix this by requesting that the write of the availablity flag

[Mesa-dev] [PATCH 23/51] i965: Move bufmgr from brw_context to brw_batch

Since brw_batch will become the dominate interface for brw_bo, move the pointer now to reduce later churn. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h| 2 ++ src/mesa/drivers/dri/i965/brw_binding_tables.c | 2 +-

[Mesa-dev] [PATCH 24/51] i965: Move batch related parameters from brw_context to intel_batchbuffer

In order to reduce later churn, move a few parameters from the general brw_context into the intel_batchbuffer. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 20 + src/mesa/drivers/dri/i965/brw_compute.c | 2 +-

[Mesa-dev] [PATCH 09/51] i965: Add a couple of utility functions to ref/unref a brw_bo

To further reduce churn when replacing the buffer object implementation, wrap the existing drm_intel_bo_reference/drm_intel_bo_unreference. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h| 12 ++

[Mesa-dev] [PATCH 16/51] i965: Replace opencoded brw_load_register_mem()

gen7_sol_state loads the SOL_OFFSET registers from its scratch buffer by hand, switch it over to the common routine for emitting that command. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/gen7_sol_state.c | 13 ++--- 1 file changed, 6

[Mesa-dev] [PATCH 08/51] i965: Rename intel_batchbuffer to brw_batch

In order to reduce future churn, rename the intel_batchbuffer struct. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 4 ++-- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_state_batch.c | 6

[Mesa-dev] [PATCH 13/51] i965: Rename render_cache dirty tracking to reduce later churn

Simple rename and parameter passing changes now to avoid doing so inside a much larger patch. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_batch.h | 5 + src/mesa/drivers/dri/i965/brw_context.c | 12 ++

[Mesa-dev] [PATCH 05/51] i965: Remove direct includes of intel_batchbuffer.h

Upcoming patches eliminate the intel_batchbuffer interface and one of the minor changes that causes a lot of churn is the removal of the header, along with the occassional need to now call intel_reg.h themselves. This patch moves the individual includes into brw_context.h. Signed-off-by: Chris

[Mesa-dev] [PATCH 04/51] i965: Share the workaround bo between all contexts

Since the workaround bo is used strictly as a write-only buffer, we need only allocate one per screen and use the same one from all contexts. (The caveat here is during extension initialisation, where we write into and read back register values from the buffer, but that is performed only once for

[Mesa-dev] [PATCH 03/51] i965: Only flush the batchbuffer if we need to zero the SO offsets

If we don't have pipelined register access (e.g. Haswell before kernel v4.2), then we can only implement EXT_transform_feedback by reseting the SO offsets *between* batches. However, if we do have pipelined access to the SO registers on gen7, we can simply emit an inline reset of the SO registers

[Mesa-dev] i965: No relocation support for GL

Not much has changed in the couple of years since last posting, just a lot of rebasing. Still the major open question is how much locking do individual contexts require amongst a shared set - can we rely of the upper layer providing sufficient serialisation around access to brw_context? The 40%

[Mesa-dev] [PATCH 01/51] i965: Do not use purged bo after calling glObjectUnpurgeable

If the buffer has been freed by the kernel under memory pressure, it is invalid to try and access the backing storage for that buffer in the future - the backing storage is not recreated automatically. As such we need to mark the GL object as being freed for unretained buffers and so recreate the

[Mesa-dev] [PATCH] egl/dri2: add image_loader_extension back into loader extensions for wayland

before commit f871946594129500a67c05a6d9fe99db54b4bb64 image_loader_extension was always present in dri2_dpy->extensions, after that commit it is only present for render nodes. Its removal broke partial render based on buffer age on (at least) raspberry pi. Signed-off-by: Derek Foreman

Re: [Mesa-dev] [Mesa-dev, 10/32] dri: Add an image creation with modifiers

On 17-01-09 16:42:19, Jason Ekstrand wrote: Somehow I didn't actually get the original e-mail so I'm replying via git-send-email... On 01/02, Ben Widawsky wrote: Modifiers will be obtains or guessed by the client and passed in during image creation/import. This requires bumping the DRIimage

Re: [Mesa-dev] [PATCH v2] Rename the DEBUG macro to MESA_DEBUG

I don't like adding workarounds to our codebase for someone else's problem, generally, but specifically I think this is a bad idea because the name MESA_DEBUG is already used (it's an environment variable), and this is a completely separate meaning. ___

Re: [Mesa-dev] [PATCH v2 03/14] spirv: Handle tessellation execution modes.

On Tuesday, January 10, 2017 9:06:08 AM PST Jason Ekstrand wrote: > On Mon, Jan 9, 2017 at 11:37 PM, Kenneth Graunke > wrote: > > > v2: Use info->tess. > > > > Signed-off-by: Kenneth Graunke > > Reviewed-by: Dave Airlie [v1] > >

Re: [Mesa-dev] [PATCH v2] Rename the DEBUG macro to MESA_DEBUG

On Tue, Jan 10, 2017 at 12:07 PM, Jan Vesely wrote: > On Tue, 2017-01-10 at 16:43 +, Emil Velikov wrote: >> On 10 January 2017 at 15:04, Vedran Miletić wrote: >> > On 09/19/2016 08:39 PM, Vedran Miletić wrote: >> > > On 09/07/2016 06:52 PM, Vedran

Re: [Mesa-dev] [PATCH 1/3] vl/dri3: use external texture as back buffers(v4)

On Tue, Jan 10, 2017 at 12:56 PM, Andy Furniss wrote: > Alex Deucher wrote: >> >> On Tue, Jan 10, 2017 at 4:50 AM, Nayan Deshmukh >> wrote: >>> >>> On Fri, Jan 6, 2017 at 2:20 AM, Andy Furniss wrote: Christian König

Re: [Mesa-dev] [PATCH v4] anv: set input_slots_valid on brw_wm_prog_key

Reviewed-by: Jason Ekstrand On Tue, Jan 10, 2017 at 9:57 AM, Lionel Landwerlin < lionel.g.landwer...@intel.com> wrote: > With shaders using a lot of inputs/outputs, like this (from Gtk+) : > > layout(location = 0) in vec2 inPos; > layout(location = 1) in float

[Mesa-dev] [PATCH v4] anv: set input_slots_valid on brw_wm_prog_key

With shaders using a lot of inputs/outputs, like this (from Gtk+) : layout(location = 0) in vec2 inPos; layout(location = 1) in float inGradientPos; layout(location = 2) in flat int inRepeating; layout(location = 3) in flat int inStopCount; layout(location = 4) in flat vec4 inClipBounds;

Re: [Mesa-dev] [PATCH 1/3] vl/dri3: use external texture as back buffers(v4)

Alex Deucher wrote: On Tue, Jan 10, 2017 at 4:50 AM, Nayan Deshmukh wrote: On Fri, Jan 6, 2017 at 2:20 AM, Andy Furniss wrote: Christian König wrote: Am 04.01.2017 um 18:13 schrieb Nayan Deshmukh: dri3 allows us to send handle of a texture

Re: [Mesa-dev] [PATCH] glsl: always do sqrt(abs()) and inversesqrt(abs())

On Tue, Jan 10, 2017 at 12:51 PM, Jason Ekstrand wrote: > On Tue, Jan 10, 2017 at 9:48 AM, Jason Ekstrand > wrote: >> >> I'll be honest, I'm not a fan... Given that D3D10 has one defined >> behavior, D3D9 has another, and GL doesn't specify, I don't

Re: [Mesa-dev] [PATCH 03/11] i965/vec4: use attribute slots for first non payload GRF

On 2017-01-09 09:10:01, Juan A. Suarez Romero wrote: > From: Alejandro Piñeiro > > --- > src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp >

Re: [Mesa-dev] [PATCH] glsl: always do sqrt(abs()) and inversesqrt(abs())

On Tue, Jan 10, 2017 at 9:48 AM, Jason Ekstrand wrote: > I'll be honest, I'm not a fan... Given that D3D10 has one defined > behavior, D3D9 has another, and GL doesn't specify, I don't really think we > should be making a global change to all drivers to do the D3D9 behavior

Re: [Mesa-dev] [PATCH] glsl: always do sqrt(abs()) and inversesqrt(abs())

I'll be honest, I'm not a fan... Given that D3D10 has one defined behavior, D3D9 has another, and GL doesn't specify, I don't really think we should be making a global change to all drivers to do the D3D9 behavior just to fix one app. Sure, other apps probably have the same bug, but are we going

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