Re: [Mesa-dev] [PATCH] st/clover: Fix build after shrink of pipe_box

[Vinson Lee]

On Tue, Apr 4, 2017 at 6:20 PM, Aaron Watry  wrote:
> Fixes: 3dfe61e ("gallium: decrease the size of pipe_box - 24 -> 16 bytes")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100569
> Signed-off-by: Aaron Watry 
> ---
>  src/gallium/state_trackers/clover/core/resource.cpp | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/state_trackers/clover/core/resource.cpp 
> b/src/gallium/state_trackers/clover/core/resource.cpp
> index 28fba1ac1a..79911771a0 100644
> --- a/src/gallium/state_trackers/clover/core/resource.cpp
> +++ b/src/gallium/state_trackers/clover/core/resource.cpp
> @@ -33,9 +33,9 @@ namespace {
> class box {
> public:
>box(const resource::vector , const resource::vector ) :
> - pipe({ (int)origin[0], (int)origin[1],
> -(int)origin[2], (int)size[0],
> -(int)size[1], (int)size[2] }) {
> +pipe({ (int)origin[0], (int16_t)origin[1],
> +   (int16_t)origin[2], (int)size[0],
> +   (int16_t)size[1], (int16_t)size[2] }) {
>}
>
>operator const pipe_box *() {
> --
> 2.11.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev

This patch fixes the build for me.

Tested-by: Vinson Lee 
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v4 00/28] i965: Ivybridge ARB_gpu_shader_fp64 / OpenGL 4.0

[Samuel Iglesias Gonsálvez]

On Tue, Apr 04, 2017 at 06:04:28PM +0200, Andreas Boll wrote:
> Please update the release notes in the last patch.

OK, thanks!

Sam

> 
> Thanks,
> Andreas
> 
> 2017-03-20 10:16 GMT+01:00 Samuel Iglesias Gonsálvez :
> > Hi,
> >
> > This series implements initial support for Ivybridge FP64 for both
> > align16 and align1 backends, and with that we can enable FP64 and
> > OpenGL 4.0 in Ivybridge.
> >
> > These patches are available in our repository for testing. You can
> > clone it using the following command:
> >
> > $ git clone -b i965-fp64-gen7-ivb-scalar-vec4-rc4 \
> > https://github.com/Igalia/mesa.git
> >
> > This is the fourth version of the patch series. The changes against v3
> > are: generalization of d2x pass to allow conversions to narrower or
> > equal size types and rename it, fix properly the DF CMP with null
> > destination bug, split VEC4_OPCODE_FROM_DOUBLE opcode into two (one
> > for conversion, another for gathering the spread data).
> >
> > The only feature missing in this series would be register spilling of
> > 64-bit data. With this series all existing FP64 tests in Piglit pass on
> > Ivybridge, except for ~36 tests that fail to spill registers (mostly
> > the same varying-packing tests that failed in the scalar backend
> > before Curro fixed the scalar spilling implementation for SIMD32).
> >
> > Best regards,
> >
> > Sam
> >
> >
> > Francisco Jerez (1):
> >   i965/fs: Get 64-bit indirect moves working on IVB.
> >
> > Iago Toral Quiroga (1):
> >   i965/disasm: also print nibctrl in IVB for execsize=8
> >
> > Juan A. Suarez Romero (7):
> >   i965/fs: add helper to retrieve instruction data size
> >   i965/fs: double regioning parameters and execsize for DF in IVB/BYT
> >   i965/fs: fix dst stride in IVB/BYT type conversions
> >   i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT
> >   i965/vec4: keep original type when dealing with null registers
> >   i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT
> >   i965/vec4: consider subregister offset in live variables
> >
> > Matt Turner (5):
> >   i965: Handle IVB DF differences in the validator.
> >   i965: Use <0,2,1> region for scalar DF sources on IVB/BYT.
> >   i965: Use source region <1,2,0> when converting to DF.
> >   i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT.
> >   i965: Use correct VertStride on align16 instructions.
> >
> > Samuel Iglesias Gonsálvez (14):
> >   i965/fs: clamp exec_size when an instruction has a scalar DF source
> >   i965/fs: generalize the legalization d2x pass
> >   i965/fs: rename lower_d2x to lower_narrow_conversions
> >   i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on
> > IVB/BYT
> >   i965/vec4: split DF instructions and later double its execsize in
> > IVB/BYT
> >   i965/vec4: split d2x conversion and data gathering from one opcode to
> > two explicit ones
> >   i965/vec4: fix assert to detect SIMD lowered DF instructions in IVB
> >   i965/vec4: fix SIMD-width lowering for VEC4_OPCODE_FROM_DOUBLE
> >   i965/vec4: use vec4_builder to emit instructions in setup_imm_df()
> >   i965/vec4: don't do horizontal stride on some register file types
> >   i965/vec4/dce: improve track of partial flag register writes
> >   i965: enable ARB_gpu_shader_fp64 for Ivybridge/Baytrail
> >   i965: enable OpenGL 4.0 to Ivybridge/Baytrail
> >   docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by
> > i965/gen7+
> >
> >  docs/features.txt  |   4 +-
> >  src/intel/Makefile.sources |   2 +-
> >  src/intel/compiler/brw_disasm.c|   6 +-
> >  src/intel/compiler/brw_eu_emit.c   |  72 ++--
> >  src/intel/compiler/brw_eu_validate.c   |  24 
> >  src/intel/compiler/brw_fs.cpp  |  54 ++---
> >  src/intel/compiler/brw_fs.h|  16 ++-
> >  src/intel/compiler/brw_fs_generator.cpp| 104 +++--
> >  src/intel/compiler/brw_fs_lower_d2x.cpp|  78 -
> >  .../compiler/brw_fs_lower_narrow_conversions.cpp   | 123 
> > +
> >  src/intel/compiler/brw_ir_vec4.h   |  37 ++-
> >  src/intel/compiler/brw_vec4.cpp|  19 +++-
> >  src/intel/compiler/brw_vec4.h  |   3 +-
> >  .../compiler/brw_vec4_dead_code_eliminate.cpp  |   2 +-
> >  src/intel/compiler/brw_vec4_generator.cpp  |  59 ++
> >  src/intel/compiler/brw_vec4_live_variables.h   |   4 +-
> >  src/intel/compiler/brw_vec4_nir.cpp|  16 +--
> >  src/mesa/drivers/dri/i965/intel_extensions.c   |   4 +-
> >  src/mesa/drivers/dri/i965/intel_screen.c   |   6 +-
> >  19 files changed, 474 insertions(+), 159 deletions(-)
> >  delete mode 100644 src/intel/compiler/brw_fs_lower_d2x.cpp
> >  create mode 100644 src/intel/compiler/brw_fs_lower_narrow_conversions.cpp
> >
> > --
> > 

Re: [Mesa-dev] [PATCH] travis: remove r600 as it requires llvm 3.8

[Rhys Kidd]

On 2 April 2017 at 17:26, Dave Airlie  wrote:

> On 3 April 2017 at 06:44, Rhys Kidd  wrote:
> > On 2 April 2017 at 08:42, Christian Gmeiner  >
> > wrote:
> >>
> >> At the moment travis ci failes with the following error:
> >>
> >> checking for RADEON... yes
> >> checking for RADEON... yes
> >> configure: error: LLVM 3.8.0 or newer is required for r600
> >> make: *** No targets specified and no makefile found.  Stop.
> >>
> >> Signed-off-by: Christian Gmeiner 
> >
> >
> > NACK.
> >
> > I'll send out to the mailing list shortly a patch that enables LLVM 3.8+
> on
> > Travis-CI's Trusty-based environment that we use.
> >
> > Allows r600g to remain and should theoretically allow radeonsi to be
> tested
> > as well. Possibly the vulkan drivers and swr too without a great deal
> > further work.
>
> FYI, radv is llvm 3.9+.
>

Patch for radv continuous integration is on the mailing list (
https://patchwork.freedesktop.org/patch/148457/) now that all the enabling
steps including LLVM 3.9+ are in place.


>
> Dave.
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] travis: Add radv vulkan driver to continuous integration

[Rhys Kidd]

Signed-off-by: Rhys Kidd 
---
 .travis.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.travis.yml b/.travis.yml
index aa212b1..0b03ae7 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -115,6 +115,7 @@ script:
 --with-egl-platforms=x11,drm
 --with-dri-drivers=i915,i965,radeon,r200,swrast,nouveau
 
--with-gallium-drivers=i915,nouveau,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx
+--with-vulkan-drivers=radeon
 --disable-llvm-shared-libs
 ;
   make && make check;
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] V2 More shader cache improvements

[Timothy Arceri]

This is a resend of version 2. The follow is some load/start-up times
gathered by Grazvydas Ignotas. I was seeing similar results as noted
in the commit messages.

   beforeafter
   cold hot  cold hot
DeusExMDbench: 285  34   261  27
Talos: 20   20   18   17
L4D2_lvl:  19   19   19   18
AlienIsl:  27   18   24   17
AlienIsl_lvl:  47   26   43   23
SOMA:  14   14   14   14
SOMA_lvl:  13   13   13   13
TombR_lvl:  75   75

Note: _lvl indicates some saved game level load times from the main
menu.

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 3/3] glsl: don't run the GLSL pre-processor when we are skipping compilation

[Timothy Arceri]

Improves Deus Ex start-up times with a warm cache from ~30 seconds to
~22 seconds.

Also fixes the leaking of state.

V2: fix indentation

Tested-by: Grazvydas Ignotas 
---
 src/compiler/glsl/glsl_parser_extras.cpp | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index ec7860d0..01037d4 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -1997,32 +1997,23 @@ opt_shader_and_create_symbol_table(struct gl_context 
*ctx,
   }
}
 
_mesa_glsl_initialize_derived_variables(ctx, shader);
 }
 
 void
 _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader,
   bool dump_ast, bool dump_hir, bool force_recompile)
 {
-   struct _mesa_glsl_parse_state *state =
-  new(shader) _mesa_glsl_parse_state(ctx, shader->Stage, shader);
const char *source = force_recompile && shader->FallbackSource ?
   shader->FallbackSource : shader->Source;
 
-   if (ctx->Const.GenerateTemporaryNames)
-  (void) p_atomic_cmpxchg(_variable::temporaries_allocate_names,
-  false, true);
-
-   state->error = glcpp_preprocess(state, , >info_log,
- add_builtin_defines, state, ctx);
-
if (!force_recompile) {
   if (ctx->Cache) {
  char buf[41];
  disk_cache_compute_key(ctx->Cache, source, strlen(source),
 shader->sha1);
  if (disk_cache_has_key(ctx->Cache, shader->sha1)) {
 /* We've seen this shader before and know it compiles */
 if (ctx->_Shader->Flags & GLSL_CACHE_INFO) {
_mesa_sha1_format(buf, shader->sha1);
fprintf(stderr, "deferring compile of shader: %s\n", buf);
@@ -2042,20 +2033,30 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, 
struct gl_shader *shader,
   if (shader->CompileStatus == compile_success)
  return;
 
   if (shader->CompileStatus == compiled_no_opts) {
  opt_shader_and_create_symbol_table(ctx, shader);
  shader->CompileStatus = compile_success;
  return;
   }
}
 
+   struct _mesa_glsl_parse_state *state =
+  new(shader) _mesa_glsl_parse_state(ctx, shader->Stage, shader);
+
+   if (ctx->Const.GenerateTemporaryNames)
+  (void) p_atomic_cmpxchg(_variable::temporaries_allocate_names,
+  false, true);
+
+   state->error = glcpp_preprocess(state, , >info_log,
+   add_builtin_defines, state, ctx);
+
if (!state->error) {
  _mesa_glsl_lexer_ctor(state, source);
  _mesa_glsl_parse(state);
  _mesa_glsl_lexer_dtor(state);
  do_late_parsing_checks(state);
}
 
if (dump_ast) {
   foreach_list_typed(ast_node, ast, link, >translation_unit) {
  ast->print();
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] travis: Add radeonsi to continuous integration

[Rhys Kidd]

Signed-off-by: Rhys Kidd 
---
 .travis.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis.yml b/.travis.yml
index aa212b1..c0b2c1f 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -114,7 +114,7 @@ script:
   ./autogen.sh --enable-debug
 --with-egl-platforms=x11,drm
 --with-dri-drivers=i915,i965,radeon,r200,swrast,nouveau
-
--with-gallium-drivers=i915,nouveau,r300,r600,freedreno,svga,swrast,vc4,virgl,etnaviv,imx
+
--with-gallium-drivers=i915,nouveau,r300,r600,radeonsi,freedreno,svga,swrast,vc4,virgl,etnaviv,imx
 --disable-llvm-shared-libs
 ;
   make && make check;
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/3] glsl: disable cache if MESA_EXTENSION_OVERRIDE is set

[Timothy Arceri]

In the following patch we will stop pre-processing shaders before
hashing them, so we just disable the cache if MESA_EXTENSION_OVERRIDE
is set.

Tested-by: Grazvydas Ignotas 
---
 src/util/disk_cache.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c
index d9de8ef..dc883a3 100644
--- a/src/util/disk_cache.c
+++ b/src/util/disk_cache.c
@@ -167,20 +167,29 @@ disk_cache_create(const char *gpu_name, const char 
*timestamp)
 {
void *local;
struct disk_cache *cache = NULL;
char *path, *max_size_str;
uint64_t max_size;
int fd = -1;
struct stat sb;
struct statvfs vfs = { 0 };
size_t size;
 
+   /* We no longer pre-process shaders before hashing them so disable the
+* cache if extensions are overridden.
+*
+* Note: Versions are part of the linked programs hash so we don't need
+* to worry about those here.
+*/
+   if (getenv("MESA_EXTENSION_OVERRIDE"))
+  return NULL;
+
/* If running as a users other than the real user disable cache */
if (geteuid() != getuid())
   return NULL;
 
/* A ralloc context for transient data during this invocation. */
local = ralloc_context(NULL);
if (local == NULL)
   goto fail;
 
/* At user request, disable shader cache entirely. */
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/3] glsl: delay optimisations on individual shaders when cache is available

[Timothy Arceri]

Due to a max limit of 65,536 entries on the index table that we use to
decide if we can skip compiling individual shaders, it is very likely
we will have collisions.

To avoid doing too much work when the linked program may be in the
cache this patch delays calling the optimisations until link time.

Improves cold cache start-up times on Deus Ex by ~20 seconds.

When deleting the cache index to simulate a worst case scenario
of collisions in the index, warm cache start-up time improves by
~45 seconds.

V2: fix indentation, make sure to call optimisations on cache
fallback, make sure optimisations get called for XFB.

Tested-by: Grazvydas Ignotas 
---
 src/compiler/glsl/glsl_parser_extras.cpp | 166 +--
 src/compiler/glsl/linker.cpp |   3 -
 src/compiler/glsl/shader_cache.cpp   |   2 +-
 src/mesa/main/mtypes.h   |   3 +-
 4 files changed, 96 insertions(+), 78 deletions(-)

diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index 8b5df3b..ec7860d0 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -1914,20 +1914,99 @@ static void
 do_late_parsing_checks(struct _mesa_glsl_parse_state *state)
 {
if (state->stage == MESA_SHADER_COMPUTE && !state->has_compute_shader()) {
   YYLTYPE loc;
   memset(, 0, sizeof(loc));
   _mesa_glsl_error(, state, "Compute shaders require "
"GLSL 4.30 or GLSL ES 3.10");
}
 }
 
+static void
+opt_shader_and_create_symbol_table(struct gl_context *ctx,
+   struct gl_shader *shader)
+{
+   assert(shader->CompileStatus != compile_failure &&
+  !shader->ir->is_empty());
+
+   struct gl_shader_compiler_options *options =
+  >Const.ShaderCompilerOptions[shader->Stage];
+
+   /* Do some optimization at compile time to reduce shader IR size
+* and reduce later work if the same shader is linked multiple times
+*/
+   if (ctx->Const.GLSLOptimizeConservatively) {
+  /* Run it just once. */
+  do_common_optimization(shader->ir, false, false, options,
+ ctx->Const.NativeIntegers);
+   } else {
+  /* Repeat it until it stops making changes. */
+  while (do_common_optimization(shader->ir, false, false, options,
+ctx->Const.NativeIntegers))
+ ;
+   }
+
+   validate_ir_tree(shader->ir);
+
+   enum ir_variable_mode other;
+   switch (shader->Stage) {
+   case MESA_SHADER_VERTEX:
+  other = ir_var_shader_in;
+  break;
+   case MESA_SHADER_FRAGMENT:
+  other = ir_var_shader_out;
+  break;
+   default:
+  /* Something invalid to ensure optimize_dead_builtin_uniforms
+   * doesn't remove anything other than uniforms or constants.
+   */
+  other = ir_var_mode_count;
+  break;
+   }
+
+   optimize_dead_builtin_variables(shader->ir, other);
+
+   validate_ir_tree(shader->ir);
+
+   /* Retain any live IR, but trash the rest. */
+   reparent_ir(shader->ir, shader->ir);
+
+   /* Destroy the symbol table.  Create a new symbol table that contains only
+* the variables and functions that still exist in the IR.  The symbol
+* table will be used later during linking.
+*
+* There must NOT be any freed objects still referenced by the symbol
+* table.  That could cause the linker to dereference freed memory.
+*
+* We don't have to worry about types or interface-types here because those
+* are fly-weights that are looked up by glsl_type.
+*/
+   foreach_in_list (ir_instruction, ir, shader->ir) {
+  switch (ir->ir_type) {
+  case ir_type_function:
+ shader->symbols->add_function((ir_function *) ir);
+ break;
+  case ir_type_variable: {
+ ir_variable *const var = (ir_variable *) ir;
+
+ if (var->data.mode != ir_var_temporary)
+shader->symbols->add_variable(var);
+ break;
+  }
+  default:
+ break;
+  }
+   }
+
+   _mesa_glsl_initialize_derived_variables(ctx, shader);
+}
+
 void
 _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader,
   bool dump_ast, bool dump_hir, bool force_recompile)
 {
struct _mesa_glsl_parse_state *state =
   new(shader) _mesa_glsl_parse_state(ctx, shader->Stage, shader);
const char *source = force_recompile && shader->FallbackSource ?
   shader->FallbackSource : shader->Source;
 
if (ctx->Const.GenerateTemporaryNames)
@@ -1955,20 +2034,26 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, 
struct gl_shader *shader,
 return;
  }
   }
} else {
   /* We should only ever end up here if a re-compile has been forced by a
* shader cache miss. In which case we can skip the compile if its
* already be done by a previous fallback or the initial compile call.
*/
   if 

Re: [Mesa-dev] [PATCH 03/53] i965: Make sure we don't use CPU maps for the scanout buffer.

[Jason Ekstrand]

Seems like a good idea.

Reviewed-by: Jason Ekstrand 

On Tue, Apr 4, 2017 at 5:09 PM, Kenneth Graunke 
wrote:

> Using an incoherent CPU map on the active scanout buffer is really
> sketchy - we may need extra flushing via GEM_SW_FINISH, or using
> drmModeDirtyFB() and kernel commit a6a7cc4b7db6d (4.10+).
>
> Chris suggests "never ever do that", which seems like a wise plan!
>
> intel_miptree_map_raw() uses CPU maps on linear buffers.
>
> Having a linear scanout buffer should be really rare, and mapping the
> front buffer should be similarly rare.  Together, it should basically
> never happen.  But, in case it does somehow...make sure that mapping
> the scanout buffer always goes through an uncached GTT map.
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 467ada5079b..272eb49867e 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2460,7 +2460,7 @@ intel_miptree_map_raw(struct brw_context *brw,
> struct intel_mipmap_tree *mt)
> if (drm_intel_bo_references(brw->batch.bo, bo))
>intel_batchbuffer_flush(brw);
>
> -   if (mt->tiling != I915_TILING_NONE)
> +   if (mt->tiling != I915_TILING_NONE || mt->is_scanout)
>brw_bo_map_gtt(brw, bo, "miptree");
> else
>brw_bo_map(brw, bo, true, "miptree");
> --
> 2.12.1
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 01/53] i965: Fix GLX_MESA_query_renderer video memory on 32-bit.

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Tue, Apr 4, 2017 at 5:09 PM, Kenneth Graunke 
wrote:

> On modern systems with 4GB apertures, the size in bytes is 4294967296,
> or (1ull << 32).  The kernel gives us the aperture size as a __u64,
> which works out great.
>
> Unfortunately, libdrm "helpfully" returns the data as a size_t, which
> on 32-bit systems means it truncates the aperture size to 0 bytes.
> We've happily reported this value as 0 MB of video memory via
> GLX_MESA_query_renderer since it was originally exposed.
>
> This patch bypasses libdrm and calls the ioctl ourselves so we can
> use a proper uint64_t, avoiding the 32-bit integer overflow.  We now
> report a proper video memory size on 32-bit systems.
> ---
>  src/mesa/drivers/dri/i965/intel_screen.c | 16 
>  1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
> b/src/mesa/drivers/dri/i965/intel_screen.c
> index 811a9c5a867..f94e8a77c10 100644
> --- a/src/mesa/drivers/dri/i965/intel_screen.c
> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> @@ -950,6 +950,17 @@ static const __DRIimageExtension intelImageExtension
> = {
>  .createImageWithModifiers   = intel_create_image_with_
> modifiers,
>  };
>
> +static uint64_t
> +get_aperture_size(int fd)
> +{
> +   struct drm_i915_gem_get_aperture aperture;
> +
> +   if (drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, ) != 0)
> +  return 0;
> +
> +   return aperture.aper_size;
> +}
> +
>  static int
>  brw_query_renderer_integer(__DRIscreen *dri_screen,
> int param, unsigned int *value)
> @@ -972,10 +983,7 @@ brw_query_renderer_integer(__DRIscreen *dri_screen,
> * assume that there's some fragmentation, and we start doing extra
> * flushing, etc.  That's the big cliff apps will care about.
> */
> -  size_t aper_size;
> -  size_t mappable_size;
> -
> -  drm_intel_get_aperture_sizes(dri_screen->fd, _size,
> _size);
> +  uint64_t aper_size = get_aperture_size(dri_screen->fd);
>
>const unsigned gpu_mappable_megabytes =
>   (aper_size / (1024 * 1024)) * 3 / 4;
> --
> 2.12.1
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] debian wheezy - r300 bug

[Richard Kuenz]

Hello ,

i am affected on Powermac 7,3 by r300 bug as i cannot achieve 3d acceleration 
and video playback is blue with mpv and gnome-mplayer.

is there a way to overcome this whiteout upgrading to newer debian version?


thank you very much
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] anv/query: Busy-wait for available query entries

[Jason Ekstrand]

Before, we were just looking at whether or not the user wanted us to
wait and waiting on the BO.  This instead makes us busy-loop on each
query until it's available.  This reduces some of the pipeline bubbles
we were getting and improves performance of The Talos Principle on
medium settings (where the GPU isn't overloaded) by around 20% on my
SkyLake gt4.
---
 src/intel/vulkan/genX_query.c | 72 +++
 1 file changed, 66 insertions(+), 6 deletions(-)

diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 7ea9404..ebf99d2 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -131,6 +131,64 @@ cpu_write_query_result(void *dst_slot, VkQueryResultFlags 
flags,
}
 }
 
+#define NSEC_PER_SEC 10
+
+static bool
+query_is_available(struct anv_device *device, uint64_t *slot)
+{
+   if (!device->info.has_llc)
+  __builtin_ia32_clflush(slot);
+
+   return slot[0];
+}
+
+static VkResult
+wait_for_available(struct anv_device *device,
+   struct anv_query_pool *pool, uint64_t *slot)
+{
+   while (true) {
+  struct timespec start;
+  clock_gettime(CLOCK_MONOTONIC, );
+
+  while (true) {
+ if (!device->info.has_llc)
+__builtin_ia32_clflush(slot);
+
+ if (query_is_available(device, slot))
+return VK_SUCCESS;
+
+ struct timespec current;
+ clock_gettime(CLOCK_MONOTONIC, );
+
+ if (current.tv_nsec < start.tv_nsec) {
+current.tv_nsec += NSEC_PER_SEC;
+current.tv_sec -= 1;
+ }
+
+ /* If we've been looping for more than 1 ms, break out of the busy
+  * loop and ask the kernel if the buffer is actually busy.
+  */
+ if (current.tv_sec > start.tv_sec ||
+ current.tv_nsec - start.tv_nsec > 100)
+break;
+  }
+
+  VkResult result = anv_device_wait(device, >bo, 0);
+  switch (result) {
+  case VK_SUCCESS:
+ /* The BO is no longer busy.  If we haven't seen availability yet,
+  * then we never will.
+  */
+ return query_is_available(device, slot) ? VK_SUCCESS : VK_NOT_READY;
+  case VK_TIMEOUT:
+ /* The BO is still busy, keep waiting. */
+ continue;
+  default:
+ return result;
+  }
+   }
+}
+
 VkResult genX(GetQueryPoolResults)(
 VkDevice_device,
 VkQueryPool queryPool,
@@ -154,12 +212,6 @@ VkResult genX(GetQueryPoolResults)(
if (pData == NULL)
   return VK_SUCCESS;
 
-   if (flags & VK_QUERY_RESULT_WAIT_BIT) {
-  VkResult result = anv_device_wait(device, >bo, INT64_MAX);
-  if (result != VK_SUCCESS)
- return result;
-   }
-
void *data_end = pData + dataSize;
 
if (!device->info.has_llc) {
@@ -176,6 +228,14 @@ VkResult genX(GetQueryPoolResults)(
   /* Availability is always at the start of the slot */
   bool available = slot[0];
 
+  if (!available && (flags & VK_QUERY_RESULT_WAIT_BIT)) {
+ status = wait_for_available(device, pool, slot);
+ if (status != VK_SUCCESS)
+return status;
+
+ available = true;
+  }
+
   /* From the Vulkan 1.0.42 spec:
*
*"If VK_QUERY_RESULT_WAIT_BIT and VK_QUERY_RESULT_PARTIAL_BIT are
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/3] mesa: rework bind_buffer_object()

[Timothy Arceri]

On 05/04/17 11:41, Timothy Arceri wrote:

This allows internal users to pass buffer objects directly and
alows for KHR_no_error support in the following patch.


Sorry this should read:

This allows internal users to pass buffer objects directly and
allows for KHR_no_error support to be more easily added.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/3] mesa: rework bind_buffer_object()

[Timothy Arceri]

This allows internal users to pass buffer objects directly and
alows for KHR_no_error support in the following patch.
---
 src/mesa/main/bufferobj.c | 34 --
 1 file changed, 16 insertions(+), 18 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index eca86aa..9669f8a 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1006,32 +1006,27 @@ _mesa_handle_bind_buffer_gen(struct gl_context *ctx,
}
 
return true;
 }
 
 /**
  * Bind the specified target to buffer for the specified context.
  * Called by glBindBuffer() and other functions.
  */
 static void
-bind_buffer_object(struct gl_context *ctx, GLenum target, GLuint buffer)
+bind_buffer_object(struct gl_context *ctx,
+   struct gl_buffer_object **bindTarget, GLuint buffer)
 {
struct gl_buffer_object *oldBufObj;
struct gl_buffer_object *newBufObj = NULL;
-   struct gl_buffer_object **bindTarget = NULL;
 
-   bindTarget = get_buffer_target(ctx, target);
-   if (!bindTarget) {
-  _mesa_error(ctx, GL_INVALID_ENUM, "glBindBufferARB(target %s)",
-  _mesa_enum_to_string(target));
-  return;
-   }
+   assert(bindTarget);
 
/* Get pointer to old buffer object (to be unbound) */
oldBufObj = *bindTarget;
if (oldBufObj && oldBufObj->Name == buffer && !oldBufObj->DeletePending)
   return;   /* rebinding the same buffer object- no change */
 
/*
 * Get pointer to new buffer object (newBufObj)
 */
if (buffer == 0) {
@@ -1042,48 +1037,44 @@ bind_buffer_object(struct gl_context *ctx, GLenum 
target, GLuint buffer)
}
else {
   /* non-default buffer object */
   newBufObj = _mesa_lookup_bufferobj(ctx, buffer);
   if (!_mesa_handle_bind_buffer_gen(ctx, buffer,
 , "glBindBuffer"))
  return;
}
 
/* record usage history */
-   switch (target) {
-   case GL_PIXEL_PACK_BUFFER:
+   if (bindTarget == >Pack.BufferObj) {
   newBufObj->UsageHistory |= USAGE_PIXEL_PACK_BUFFER;
-  break;
-   default:
-  break;
}
 
/* bind new buffer */
_mesa_reference_buffer_object(ctx, bindTarget, newBufObj);
 }
 
 
 /**
  * Update the default buffer objects in the given context to reference those
  * specified in the shared state and release those referencing the old
  * shared state.
  */
 void
 _mesa_update_default_objects_buffer_objects(struct gl_context *ctx)
 {
/* Bind the NullBufferObj to remove references to those
 * in the shared context hash table.
 */
-   bind_buffer_object( ctx, GL_ARRAY_BUFFER_ARB, 0);
-   bind_buffer_object( ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, 0);
-   bind_buffer_object( ctx, GL_PIXEL_PACK_BUFFER_ARB, 0);
-   bind_buffer_object( ctx, GL_PIXEL_UNPACK_BUFFER_ARB, 0);
+   bind_buffer_object(ctx, >Array.ArrayBufferObj, 0);
+   bind_buffer_object(ctx, >Array.VAO->IndexBufferObj, 0);
+   bind_buffer_object(ctx, >Pack.BufferObj, 0);
+   bind_buffer_object(ctx, >Unpack.BufferObj, 0);
 }
 
 
 
 /**
  * Return the gl_buffer_object for the given ID.
  * Always return NULL for ID 0.
  */
 struct gl_buffer_object *
 _mesa_lookup_bufferobj(struct gl_context *ctx, GLuint buffer)
@@ -1261,21 +1252,28 @@ _mesa_buffer_unmap_all_mappings(struct gl_context *ctx,
 void GLAPIENTRY
 _mesa_BindBuffer(GLenum target, GLuint buffer)
 {
GET_CURRENT_CONTEXT(ctx);
 
if (MESA_VERBOSE & VERBOSE_API) {
   _mesa_debug(ctx, "glBindBuffer(%s, %u)\n",
   _mesa_enum_to_string(target), buffer);
}
 
-   bind_buffer_object(ctx, target, buffer);
+   struct gl_buffer_object **bindTarget = get_buffer_target(ctx, target);
+   if (!bindTarget) {
+  _mesa_error(ctx, GL_INVALID_ENUM, "glBindBufferARB(target %s)",
+  _mesa_enum_to_string(target));
+  return;
+   }
+
+   bind_buffer_object(ctx, bindTarget, buffer);
 }
 
 
 /**
  * Delete a set of buffer objects.
  *
  * \param n  Number of buffer objects to delete.
  * \param idsArray of \c n buffer object IDs.
  */
 void GLAPIENTRY
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/3] mesa: small texstate tidy up

[Timothy Arceri]

Possibly more efficient, either way it make the code easier to
follow.
---
 src/mesa/main/texstate.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/texstate.c b/src/mesa/main/texstate.c
index ada0dfd..aa99b06 100644
--- a/src/mesa/main/texstate.c
+++ b/src/mesa/main/texstate.c
@@ -697,27 +697,28 @@ _mesa_update_texture_state(struct gl_context *ctx)
 {
struct gl_program *prog[MESA_SHADER_STAGES];
int i;
int old_max_unit = ctx->Texture._MaxEnabledTexImageUnit;
BITSET_DECLARE(enabled_texture_units, MAX_COMBINED_TEXTURE_IMAGE_UNITS);
 
for (i = 0; i < MESA_SHADER_STAGES; i++) {
   if (ctx->_Shader->CurrentProgram[i]) {
  prog[i] = ctx->_Shader->CurrentProgram[i];
   } else {
- if (i == MESA_SHADER_FRAGMENT && ctx->FragmentProgram._Enabled)
-prog[i] = ctx->FragmentProgram.Current;
- else
-prog[i] = NULL;
+ prog[i] = NULL;
   }
}
 
+   if (prog[MESA_SHADER_FRAGMENT] == NULL && ctx->FragmentProgram._Enabled) {
+  prog[MESA_SHADER_FRAGMENT] = ctx->FragmentProgram.Current;
+   }
+
/* TODO: only set this if there are actual changes */
ctx->NewState |= _NEW_TEXTURE_OBJECT | _NEW_TEXTURE_STATE;
 
ctx->Texture._GenFlags = 0x0;
ctx->Texture._TexMatEnabled = 0x0;
ctx->Texture._TexGenEnabled = 0x0;
ctx->Texture._MaxEnabledTexImageUnit = -1;
ctx->Texture._EnabledCoordUnits = 0x0;
 
memset(_texture_units, 0, sizeof(enabled_texture_units));
-- 
2.9.3

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 3/3] mesa: use internal function when deleting buffers

[Timothy Arceri]

This avoids validation and looking up the buffer for a second time.
---
 src/mesa/main/bufferobj.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 9669f8a..d9aee58 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1300,111 +1300,111 @@ _mesa_DeleteBuffers(GLsizei n, const GLuint *ids)
  assert(bufObj->Name == ids[i] || bufObj == );
 
  _mesa_buffer_unmap_all_mappings(ctx, bufObj);
 
  /* unbind any vertex pointers bound to this buffer */
  for (j = 0; j < ARRAY_SIZE(vao->BufferBinding); j++) {
 unbind(ctx, vao, j, bufObj);
  }
 
  if (ctx->Array.ArrayBufferObj == bufObj) {
-_mesa_BindBuffer( GL_ARRAY_BUFFER_ARB, 0 );
+bind_buffer_object(ctx, >Array.ArrayBufferObj, 0);
  }
  if (vao->IndexBufferObj == bufObj) {
-_mesa_BindBuffer( GL_ELEMENT_ARRAY_BUFFER_ARB, 0 );
+bind_buffer_object(ctx, >IndexBufferObj, 0);
  }
 
  /* unbind ARB_draw_indirect binding point */
  if (ctx->DrawIndirectBuffer == bufObj) {
-_mesa_BindBuffer( GL_DRAW_INDIRECT_BUFFER, 0 );
+bind_buffer_object(ctx, >DrawIndirectBuffer, 0);
  }
 
  /* unbind ARB_indirect_parameters binding point */
  if (ctx->ParameterBuffer == bufObj) {
-_mesa_BindBuffer(GL_PARAMETER_BUFFER_ARB, 0);
+bind_buffer_object(ctx, >ParameterBuffer, 0);
  }
 
  /* unbind ARB_compute_shader binding point */
  if (ctx->DispatchIndirectBuffer == bufObj) {
-_mesa_BindBuffer(GL_DISPATCH_INDIRECT_BUFFER, 0);
+bind_buffer_object(ctx, >DispatchIndirectBuffer, 0);
  }
 
  /* unbind ARB_copy_buffer binding points */
  if (ctx->CopyReadBuffer == bufObj) {
-_mesa_BindBuffer( GL_COPY_READ_BUFFER, 0 );
+bind_buffer_object(ctx, >CopyReadBuffer, 0);
  }
  if (ctx->CopyWriteBuffer == bufObj) {
-_mesa_BindBuffer( GL_COPY_WRITE_BUFFER, 0 );
+bind_buffer_object(ctx, >CopyWriteBuffer, 0);
  }
 
  /* unbind transform feedback binding points */
  if (ctx->TransformFeedback.CurrentBuffer == bufObj) {
-_mesa_BindBuffer( GL_TRANSFORM_FEEDBACK_BUFFER, 0 );
+bind_buffer_object(ctx, >TransformFeedback.CurrentBuffer, 0);
  }
  for (j = 0; j < MAX_FEEDBACK_BUFFERS; j++) {
 if (ctx->TransformFeedback.CurrentObject->Buffers[j] == bufObj) {
_mesa_BindBufferBase( GL_TRANSFORM_FEEDBACK_BUFFER, j, 0 );
 }
  }
 
  /* unbind UBO binding points */
  for (j = 0; j < ctx->Const.MaxUniformBufferBindings; j++) {
 if (ctx->UniformBufferBindings[j].BufferObject == bufObj) {
_mesa_BindBufferBase( GL_UNIFORM_BUFFER, j, 0 );
 }
  }
 
  if (ctx->UniformBuffer == bufObj) {
-_mesa_BindBuffer( GL_UNIFORM_BUFFER, 0 );
+bind_buffer_object(ctx, >UniformBuffer, 0);
  }
 
  /* unbind SSBO binding points */
  for (j = 0; j < ctx->Const.MaxShaderStorageBufferBindings; j++) {
 if (ctx->ShaderStorageBufferBindings[j].BufferObject == bufObj) {
_mesa_BindBufferBase(GL_SHADER_STORAGE_BUFFER, j, 0);
 }
  }
 
  if (ctx->ShaderStorageBuffer == bufObj) {
-_mesa_BindBuffer(GL_SHADER_STORAGE_BUFFER, 0);
+bind_buffer_object(ctx, >ShaderStorageBuffer, 0);
  }
 
  /* unbind Atomci Buffer binding points */
  for (j = 0; j < ctx->Const.MaxAtomicBufferBindings; j++) {
 if (ctx->AtomicBufferBindings[j].BufferObject == bufObj) {
_mesa_BindBufferBase( GL_ATOMIC_COUNTER_BUFFER, j, 0 );
 }
  }
 
  if (ctx->AtomicBuffer == bufObj) {
-_mesa_BindBuffer( GL_ATOMIC_COUNTER_BUFFER, 0 );
+bind_buffer_object(ctx, >AtomicBuffer, 0);
  }
 
  /* unbind any pixel pack/unpack pointers bound to this buffer */
  if (ctx->Pack.BufferObj == bufObj) {
-_mesa_BindBuffer( GL_PIXEL_PACK_BUFFER_EXT, 0 );
+bind_buffer_object(ctx, >Pack.BufferObj, 0);
  }
  if (ctx->Unpack.BufferObj == bufObj) {
-_mesa_BindBuffer( GL_PIXEL_UNPACK_BUFFER_EXT, 0 );
+bind_buffer_object(ctx, >Unpack.BufferObj, 0);
  }
 
  if (ctx->Texture.BufferObject == bufObj) {
-_mesa_BindBuffer( GL_TEXTURE_BUFFER, 0 );
+bind_buffer_object(ctx, >Texture.BufferObject, 0);
  }
 
  if (ctx->ExternalVirtualMemoryBuffer == bufObj) {
-_mesa_BindBuffer(GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD, 0);
+bind_buffer_object(ctx, >ExternalVirtualMemoryBuffer, 0);
 

Re: [Mesa-dev] [PATCH] st/clover: Fix build after shrink of pipe_box

[Francisco Jerez]

Aaron Watry  writes:

> Fixes: 3dfe61e ("gallium: decrease the size of pipe_box - 24 -> 16 bytes")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100569
> Signed-off-by: Aaron Watry 

Thanks!

Reviewed-by: Francisco Jerez 

> ---
>  src/gallium/state_trackers/clover/core/resource.cpp | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/state_trackers/clover/core/resource.cpp 
> b/src/gallium/state_trackers/clover/core/resource.cpp
> index 28fba1ac1a..79911771a0 100644
> --- a/src/gallium/state_trackers/clover/core/resource.cpp
> +++ b/src/gallium/state_trackers/clover/core/resource.cpp
> @@ -33,9 +33,9 @@ namespace {
> class box {
> public:
>box(const resource::vector , const resource::vector ) :
> - pipe({ (int)origin[0], (int)origin[1],
> -(int)origin[2], (int)size[0],
> -(int)size[1], (int)size[2] }) {
> +pipe({ (int)origin[0], (int16_t)origin[1],
> +   (int16_t)origin[2], (int)size[0],
> +   (int16_t)size[1], (int16_t)size[2] }) {
>}
>  
>operator const pipe_box *() {
> -- 
> 2.11.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev


signature.asc
Description: PGP signature
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] st/clover: Fix build after shrink of pipe_box

[Aaron Watry]

Fixes: 3dfe61e ("gallium: decrease the size of pipe_box - 24 -> 16 bytes")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100569
Signed-off-by: Aaron Watry 
---
 src/gallium/state_trackers/clover/core/resource.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/clover/core/resource.cpp 
b/src/gallium/state_trackers/clover/core/resource.cpp
index 28fba1ac1a..79911771a0 100644
--- a/src/gallium/state_trackers/clover/core/resource.cpp
+++ b/src/gallium/state_trackers/clover/core/resource.cpp
@@ -33,9 +33,9 @@ namespace {
class box {
public:
   box(const resource::vector , const resource::vector ) :
- pipe({ (int)origin[0], (int)origin[1],
-(int)origin[2], (int)size[0],
-(int)size[1], (int)size[2] }) {
+pipe({ (int)origin[0], (int16_t)origin[1],
+   (int16_t)origin[2], (int)size[0],
+   (int16_t)size[1], (int16_t)size[2] }) {
   }
 
   operator const pipe_box *() {
-- 
2.11.0

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

Matt Turner  changed:

   What|Removed |Added

 Status|RESOLVED|REOPENED
 Resolution|WONTFIX |---

--- Comment #20 from Matt Turner  ---
(In reply to Jonathan Gray from comment #18)
> (In reply to Matt Turner from comment #16)
> > (In reply to Jonathan Gray from comment #15)
> > > Shocking as it may seem Mesa runs on more than just Linux.
> > 
> > Don't act like that. Grazvydas wrote code to fix a bug you reported more
> > than two years ago. You should be thankful, not sarcastic.
> > 
> > Presumably if you don't piss him off he'd be amenable to fixing other things
> > in this area.
> 
> The problem was clearly stated in the original report.  The changes that
> went in have not addressed this.  Only a variant that concerns a subset. 
> Closing the bug because it fixed the case he cared about and not the actual
> reported problem isn't helping anyone.
> 
> I've had to workaround the breakage for years to be able to ship builds of
> Mesa on multiple architectures.

I think you're inappropriately attributing malice to comments 12 and 14.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

Jonathan Gray  changed:

   What|Removed |Added

 Status|REOPENED|RESOLVED
 Resolution|--- |WONTFIX

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

--- Comment #19 from Timothy Arceri  ---
(In reply to Jonathan Gray from comment #18)
> (In reply to Matt Turner from comment #16)
> > (In reply to Jonathan Gray from comment #15)
> > > Shocking as it may seem Mesa runs on more than just Linux.
> > 
> > Don't act like that. Grazvydas wrote code to fix a bug you reported more
> > than two years ago. You should be thankful, not sarcastic.
> > 
> > Presumably if you don't piss him off he'd be amenable to fixing other things
> > in this area.
> 
> The problem was clearly stated in the original report.  The changes that
> went in have not addressed this.  Only a variant that concerns a subset. 
> Closing the bug because it fixed the case he cared about and not the actual
> reported problem isn't helping anyone.

I don't think he cared about it, he was trying to fix the bug for you.

> 
> I've had to workaround the breakage for years to be able to ship builds of
> Mesa on multiple architectures.

Shocking as it may seem Mesa development in mainly done on Linux for Linux on
non-niche modern hardware. Occasionally things are going to break on systems
untested during development, complaining about an inevitability is not very
helpful.

This is a community project with limited resources, we will always need
contributions from people interested in keeping such platforms building/running
optimally.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 100562] u_debug_stack.c:59: undefined reference to `_Ux86_64_getcontext'

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100562

Vinson Lee  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #2 from Vinson Lee  ---
commit c161a104629ad49dc6a4f7d1fe82e87fc08121fe
Author: Vinson Lee 
Date:   Tue Apr 4 14:52:39 2017 -0700

libgl-xlib: Link with libunwind.

Fix linking error.

  CXXLDlibGL.la
../../../../src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In
function `debug_backtrace_capture':
src/gallium/auxiliary/util/u_debug_stack.c:59: undefined reference to
`_Ux86_64_getcontext'
src/gallium/auxiliary/util/u_debug_stack.c:60: undefined reference to
`_ULx86_64_init_local'
src/gallium/auxiliary/util/u_debug_stack.c:62: undefined reference to
`_ULx86_64_step'
src/gallium/auxiliary/util/u_debug_stack.c:71: undefined reference to
`_ULx86_64_get_proc_info'
src/gallium/auxiliary/util/u_debug_stack.c:73: undefined reference to
`_ULx86_64_get_proc_name'
src/gallium/auxiliary/util/u_debug_stack.c:65: undefined reference to
`_ULx86_64_step'

Fixes: 70c272004f72 ("gallium/util: libunwind support")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100562
Signed-off-by: Vinson Lee 
Reviewed-by: Rob Clark 

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 41/53] i965/drm: Merge bo->handle and bo_gem->gem_handle.

[Kenneth Graunke]

These fields are the same value.  In the bad old days, bo->handle could
have been an identifier from the pre-GEM fake bufmgr, but that's long
gone.  Keep the "gem_handle" name for clarity.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h|   6 +-
 src/mesa/drivers/dri/i965/intel_batchbuffer.c |   6 +-
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 101 --
 src/mesa/drivers/dri/i965/intel_screen.c  |   8 +-
 4 files changed, 55 insertions(+), 66 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index d3db6a3967b..509664b6e3d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -77,10 +77,8 @@ struct _drm_bacon_bo {
/** Buffer manager context associated with this buffer object */
drm_bacon_bufmgr *bufmgr;
 
-   /**
-* MM-specific handle for accessing object
-*/
-   int handle;
+   /** The GEM handle for this buffer object. */
+   uint32_t gem_handle;
 
/**
 * Last seen card virtual address (offset from the beginning of the
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 444e33c48ee..00559bb6599 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -516,7 +516,7 @@ add_exec_bo(struct intel_batchbuffer *batch, drm_bacon_bo 
*bo)
 
struct drm_i915_gem_exec_object2 *validation_entry =
   >exec_objects[batch->exec_count];
-   validation_entry->handle = bo->handle;
+   validation_entry->handle = bo->gem_handle;
if (bo == batch->bo) {
   validation_entry->relocation_count = batch->reloc_count;
   validation_entry->relocs_ptr = (uintptr_t) batch->relocs;
@@ -583,7 +583,7 @@ execbuffer(int fd,
   /* Update drm_bacon_bo::offset64 */
   if (batch->exec_objects[i].offset != bo->offset64) {
  DBG("BO %d migrated: 0x%" PRIx64 " -> 0x%llx\n",
- bo->handle, bo->offset64, batch->exec_objects[i].offset);
+ bo->gem_handle, bo->offset64, batch->exec_objects[i].offset);
  bo->offset64 = batch->exec_objects[i].offset;
   }
}
@@ -763,7 +763,7 @@ brw_emit_reloc(struct intel_batchbuffer *batch, uint32_t 
batch_offset,
 
reloc->offset = batch_offset;
reloc->delta = target_offset;
-   reloc->target_handle = target->handle;
+   reloc->target_handle = target->gem_handle;
reloc->read_domains = read_domains;
reloc->write_domain = write_domain;
reloc->presumed_offset = target->offset64;
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 004191ed007..022a186bd6d 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -126,7 +126,6 @@ struct _drm_bacon_bo_gem {
drm_bacon_bo bo;
 
int refcount;
-   uint32_t gem_handle;
const char *name;
 
/**
@@ -260,12 +259,11 @@ int
 drm_bacon_bo_busy(drm_bacon_bo *bo)
 {
drm_bacon_bufmgr *bufmgr = bo->bufmgr;
-   drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
struct drm_i915_gem_busy busy;
int ret;
 
memclear(busy);
-   busy.handle = bo_gem->gem_handle;
+   busy.handle = bo->gem_handle;
 
ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_BUSY, );
if (ret == 0) {
@@ -284,7 +282,7 @@ drm_bacon_gem_bo_madvise_internal(drm_bacon_bufmgr *bufmgr,
struct drm_i915_gem_madvise madv;
 
memclear(madv);
-   madv.handle = bo_gem->gem_handle;
+   madv.handle = bo_gem->bo.gem_handle;
madv.madv = state;
madv.retained = 1;
drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MADVISE, );
@@ -427,11 +425,10 @@ retry:
goto err;
}
 
-   bo_gem->gem_handle = create.handle;
+   bo_gem->bo.gem_handle = create.handle;
_mesa_hash_table_insert(bufmgr->handle_table,
-   _gem->gem_handle, bo_gem);
+   _gem->bo.gem_handle, bo_gem);
 
-   bo_gem->bo.handle = bo_gem->gem_handle;
bo_gem->bo.bufmgr = bufmgr;
bo_gem->bo.align = alignment;
 
@@ -452,7 +449,7 @@ retry:
pthread_mutex_unlock(>lock);
 
DBG("bo_create: buf %d (%s) %ldb\n",
-   bo_gem->gem_handle, bo_gem->name, size);
+   bo_gem->bo.gem_handle, bo_gem->name, size);
 
return _gem->bo;
 
@@ -593,19 +590,18 @@ drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr 
*bufmgr,
bo_gem->bo.offset64 = 0;
bo_gem->bo.virtual = NULL;
bo_gem->bo.bufmgr = bufmgr;
+   bo_gem->bo.gem_handle = open_arg.handle;
bo_gem->name = name;
-   bo_gem->gem_handle = open_arg.handle;
-   bo_gem->bo.handle = open_arg.handle;
bo_gem->global_name = handle;

[Mesa-dev] [PATCH 52/53] i965/drm: Reindent intel_bufmgr_gem.c and brw_bufmgr.h.

[Kenneth Graunke]

indent -i3 -nut -br -brs -npcs -ce --no-tabs -Tuint32_t -Tuint64_t
plus some manual fixes because those aren't quite the right settings.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  196 +--
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 2152 +-
 2 files changed, 1147 insertions(+), 1201 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index c05b67dda7f..974f7d9e20c 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -46,88 +46,88 @@ extern "C" {
 struct gen_device_info;
 
 struct brw_bo {
-   /**
-* Size in bytes of the buffer object.
-*
-* The size may be larger than the size originally requested for the
-* allocation, such as being aligned to page size.
-*/
-   unsigned long size;
-
-   /**
-* Alignment requirement for object
-*
-* Used for GTT mapping & pinning the object.
-*/
-   unsigned long align;
-
-   /**
-* Virtual address for accessing the buffer data.  Only valid while
-* mapped.
-*/
+   /**
+* Size in bytes of the buffer object.
+*
+* The size may be larger than the size originally requested for the
+* allocation, such as being aligned to page size.
+*/
+   unsigned long size;
+
+   /**
+* Alignment requirement for object
+*
+* Used for GTT mapping & pinning the object.
+*/
+   unsigned long align;
+
+   /**
+* Virtual address for accessing the buffer data.  Only valid while
+* mapped.
+*/
 #ifdef __cplusplus
-   void *virt;
+   void *virt;
 #else
-   void *virtual;
+   void *virtual;
 #endif
 
-   /** Buffer manager context associated with this buffer object */
-   struct brw_bufmgr *bufmgr;
-
-   /** The GEM handle for this buffer object. */
-   uint32_t gem_handle;
-
-   /**
-* Last seen card virtual address (offset from the beginning of the
-* aperture) for the object.  This should be used to fill relocation
-* entries when calling brw_bo_emit_reloc()
-*/
-   uint64_t offset64;
-
-   /**
-* Boolean of whether the GPU is definitely not accessing the buffer.
-*
-* This is only valid when reusable, since non-reusable
-* buffers are those that have been shared with other
-* processes, so we don't know their state.
-*/
-   bool idle;
-
-   int refcount;
-   const char *name;
-
-   /**
-* Kenel-assigned global name for this object
- *
- * List contains both flink named and prime fd'd objects
-*/
-   unsigned int global_name;
-
-   /**
-* Current tiling mode
-*/
-   uint32_t tiling_mode;
-   uint32_t swizzle_mode;
-   unsigned long stride;
-
-   time_t free_time;
-
-   /** Mapped address for the buffer, saved across map/unmap cycles */
-   void *mem_virtual;
-   /** GTT virtual address for the buffer, saved across map/unmap cycles */
-   void *gtt_virtual;
-   /** WC CPU address for the buffer, saved across map/unmap cycles */
-   void *wc_virtual;
-   int map_count;
-   struct list_head vma_list;
-
-   /** BO cache list */
-   struct list_head head;
-
-   /**
-* Boolean of whether this buffer can be re-used
-*/
-   bool reusable;
+   /** Buffer manager context associated with this buffer object */
+   struct brw_bufmgr *bufmgr;
+
+   /** The GEM handle for this buffer object. */
+   uint32_t gem_handle;
+
+   /**
+* Last seen card virtual address (offset from the beginning of the
+* aperture) for the object.  This should be used to fill relocation
+* entries when calling brw_bo_emit_reloc()
+*/
+   uint64_t offset64;
+
+   /**
+* Boolean of whether the GPU is definitely not accessing the buffer.
+*
+* This is only valid when reusable, since non-reusable
+* buffers are those that have been shared with other
+* processes, so we don't know their state.
+*/
+   bool idle;
+
+   int refcount;
+   const char *name;
+
+   /**
+* Kenel-assigned global name for this object
+*
+* List contains both flink named and prime fd'd objects
+*/
+   unsigned int global_name;
+
+   /**
+* Current tiling mode
+*/
+   uint32_t tiling_mode;
+   uint32_t swizzle_mode;
+   unsigned long stride;
+
+   time_t free_time;
+
+   /** Mapped address for the buffer, saved across map/unmap cycles */
+   void *mem_virtual;
+   /** GTT virtual address for the buffer, saved across map/unmap cycles */
+   void *gtt_virtual;
+   /** WC CPU address for the buffer, saved across map/unmap cycles */
+   void *wc_virtual;
+   int map_count;
+   struct list_head vma_list;
+
+   /** BO cache list */
+   struct list_head head;
+
+   /**
+* Boolean of whether this buffer can be re-used
+*/
+   bool reusable;
 

[Mesa-dev] [PATCH 53/53] i965/drm: Rename intel_bufmgr_gem.c to brw_bufmgr.c.

[Kenneth Graunke]

Matches the class name and the header file name.
---
 src/mesa/drivers/dri/i965/Makefile.sources | 2 +-
 src/mesa/drivers/dri/i965/{intel_bufmgr_gem.c => brw_bufmgr.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename src/mesa/drivers/dri/i965/{intel_bufmgr_gem.c => brw_bufmgr.c} (100%)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 6cab4eb5f43..02dbb554a0d 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -2,6 +2,7 @@ i965_FILES = \
brw_binding_tables.c \
brw_blorp.c \
brw_blorp.h \
+   brw_bufmgr.c \
brw_bufmgr.h \
brw_cc.c \
brw_clear.c \
@@ -131,7 +132,6 @@ i965_FILES = \
intel_buffer_objects.h \
intel_buffers.c \
intel_buffers.h \
-   intel_bufmgr_gem.c \
intel_copy_image.c \
intel_extensions.c \
intel_fbo.c \
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
similarity index 100%
rename from src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
rename to src/mesa/drivers/dri/i965/brw_bufmgr.c
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 49/53] i965/drm: Rename drm_bacon_reg_read() to brw_reg_read().

[Kenneth Graunke]

Less bacon.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   | 4 +---
 src/mesa/drivers/dri/i965/brw_queryobj.c | 6 +++---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 4 +---
 src/mesa/drivers/dri/i965/intel_screen.c | 6 +++---
 4 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 5205302c001..7609425a35d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -309,9 +309,7 @@ int drm_bacon_bo_gem_export_to_prime(drm_bacon_bo *bo, int 
*prime_fd);
 drm_bacon_bo *drm_bacon_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr,
int prime_fd, int size);
 
-int drm_bacon_reg_read(struct brw_bufmgr *bufmgr,
-  uint32_t offset,
-  uint64_t *result);
+int brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset, uint64_t *result);
 
 /** @{ */
 
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c 
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 8e742af67df..ff6c0c87c9d 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -539,14 +539,14 @@ brw_get_timestamp(struct gl_context *ctx)
 
switch (brw->screen->hw_has_timestamp) {
case 3: /* New kernel, always full 36bit accuracy */
-  drm_bacon_reg_read(brw->bufmgr, TIMESTAMP | 1, );
+  brw_reg_read(brw->bufmgr, TIMESTAMP | 1, );
   break;
case 2: /* 64bit kernel, result is left-shifted by 32bits, losing 4bits */
-  drm_bacon_reg_read(brw->bufmgr, TIMESTAMP, );
+  brw_reg_read(brw->bufmgr, TIMESTAMP, );
   result = result >> 32;
   break;
case 1: /* 32bit kernel, result is 36bit wide but may be inaccurate! */
-  drm_bacon_reg_read(brw->bufmgr, TIMESTAMP, );
+  brw_reg_read(brw->bufmgr, TIMESTAMP, );
   break;
}
 
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index dfce89ba1b4..490898f9d28 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -1444,9 +1444,7 @@ brw_destroy_hw_context(struct brw_bufmgr *bufmgr, 
uint32_t ctx_id)
 }
 
 int
-drm_bacon_reg_read(struct brw_bufmgr *bufmgr,
-  uint32_t offset,
-  uint64_t *result)
+brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset, uint64_t *result)
 {
struct drm_i915_reg_read reg_read;
int ret;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 40860d14346..fc465c3beda 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1323,13 +1323,13 @@ intel_detect_timestamp(struct intel_screen *screen)
 * More recent kernels offer an interface to read the full 36bits
 * everywhere.
 */
-   if (drm_bacon_reg_read(screen->bufmgr, TIMESTAMP | 1, ) == 0)
+   if (brw_reg_read(screen->bufmgr, TIMESTAMP | 1, ) == 0)
   return 3;
 
/* Determine if we have a 32bit or 64bit kernel by inspecting the
 * upper 32bits for a rapidly changing timestamp.
 */
-   if (drm_bacon_reg_read(screen->bufmgr, TIMESTAMP, ))
+   if (brw_reg_read(screen->bufmgr, TIMESTAMP, ))
   return 0;
 
upper = lower = 0;
@@ -1337,7 +1337,7 @@ intel_detect_timestamp(struct intel_screen *screen)
   /* The TIMESTAMP should change every 80ns, so several round trips
* through the kernel should be enough to advance it.
*/
-  if (drm_bacon_reg_read(screen->bufmgr, TIMESTAMP, ))
+  if (brw_reg_read(screen->bufmgr, TIMESTAMP, ))
  return 0;
 
   upper += (dummy >> 32) != (last >> 32);
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 44/53] i965/drm: Drop drm_bacon_* from static functions.

[Kenneth Graunke]

Mesa style is to not use lengthy prefixes for static functions.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 150 ---
 1 file changed, 69 insertions(+), 81 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 0a6d08b..2ec2cd325d4 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -121,11 +121,9 @@ typedef struct _drm_bacon_bufmgr {
 } drm_bacon_bufmgr;
 
 static int
-drm_bacon_gem_bo_set_tiling_internal(drm_bacon_bo *bo,
-uint32_t tiling_mode,
-uint32_t stride);
+bo_set_tiling_internal(drm_bacon_bo *bo, uint32_t tiling_mode, uint32_t 
stride);
 
-static void drm_bacon_gem_bo_free(drm_bacon_bo *bo);
+static void bo_free(drm_bacon_bo *bo);
 
 static uint32_t
 key_hash_uint(const void *key)
@@ -147,8 +145,8 @@ hash_find_bo(struct hash_table *ht, unsigned int key)
 }
 
 static unsigned long
-drm_bacon_gem_bo_tile_size(drm_bacon_bufmgr *bufmgr, unsigned long size,
-  uint32_t *tiling_mode)
+bo_tile_size(drm_bacon_bufmgr *bufmgr, unsigned long size,
+uint32_t *tiling_mode)
 {
if (*tiling_mode == I915_TILING_NONE)
return size;
@@ -163,8 +161,8 @@ drm_bacon_gem_bo_tile_size(drm_bacon_bufmgr *bufmgr, 
unsigned long size,
  * change.
  */
 static unsigned long
-drm_bacon_gem_bo_tile_pitch(drm_bacon_bufmgr *bufmgr,
-   unsigned long pitch, uint32_t *tiling_mode)
+bo_tile_pitch(drm_bacon_bufmgr *bufmgr,
+ unsigned long pitch, uint32_t *tiling_mode)
 {
unsigned long tile_width;
 
@@ -184,8 +182,7 @@ drm_bacon_gem_bo_tile_pitch(drm_bacon_bufmgr *bufmgr,
 }
 
 static struct drm_bacon_gem_bo_bucket *
-drm_bacon_gem_bo_bucket_for_size(drm_bacon_bufmgr *bufmgr,
-unsigned long size)
+bucket_for_size(drm_bacon_bufmgr *bufmgr, unsigned long size)
 {
int i;
 
@@ -253,18 +250,18 @@ drm_bacon_gem_bo_cache_purge_bucket(drm_bacon_bufmgr 
*bufmgr,
break;
 
list_del(>head);
-   drm_bacon_gem_bo_free(bo);
+   bo_free(bo);
}
 }
 
 static drm_bacon_bo *
-drm_bacon_gem_bo_alloc_internal(drm_bacon_bufmgr *bufmgr,
-   const char *name,
-   unsigned long size,
-   unsigned long flags,
-   uint32_t tiling_mode,
-   unsigned long stride,
-   unsigned int alignment)
+bo_alloc_internal(drm_bacon_bufmgr *bufmgr,
+ const char *name,
+ unsigned long size,
+ unsigned long flags,
+ uint32_t tiling_mode,
+ unsigned long stride,
+ unsigned int alignment)
 {
drm_bacon_bo *bo;
unsigned int page_size = getpagesize();
@@ -278,7 +275,7 @@ drm_bacon_gem_bo_alloc_internal(drm_bacon_bufmgr *bufmgr,
for_render = true;
 
/* Round the allocated size up to a power of two number of pages. */
-   bucket = drm_bacon_gem_bo_bucket_for_size(bufmgr, size);
+   bucket = bucket_for_size(bufmgr, size);
 
/* If we don't have caching at this size, don't actually round the
 * allocation up.
@@ -323,16 +320,14 @@ retry:
 
if (alloc_from_cache) {
if (!drm_bacon_bo_madvise(bo, I915_MADV_WILLNEED)) {
-   drm_bacon_gem_bo_free(bo);
+   bo_free(bo);
drm_bacon_gem_bo_cache_purge_bucket(bufmgr,
bucket);
goto retry;
}
 
-   if (drm_bacon_gem_bo_set_tiling_internal(bo,
-tiling_mode,
-stride)) {
-   drm_bacon_gem_bo_free(bo);
+   if (bo_set_tiling_internal(bo, tiling_mode, stride)) {
+   bo_free(bo);
goto retry;
}
}
@@ -345,7 +340,7 @@ retry:
if (!bo)
goto err;
 
-   /* drm_bacon_gem_bo_free calls list_del() for an uninitialized
+   /* bo_free calls list_del() for an uninitialized
   list (vma_list), so better set the list head here */
list_inithead(>vma_list);
 
@@ -373,9 +368,7 @@ retry:
bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
bo->stride = 0;
 
-   if (drm_bacon_gem_bo_set_tiling_internal(bo,
-   

[Mesa-dev] [PATCH 48/53] i965/drm: Rename drm_bacon_bufmgr to struct brw_bufmgr.

[Kenneth Graunke]

Also stop using typedefs, per Mesa coding style.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h| 29 -
 src/mesa/drivers/dri/i965/brw_context.c   |  2 +-
 src/mesa/drivers/dri/i965/brw_context.h   |  2 +-
 src/mesa/drivers/dri/i965/intel_batchbuffer.c |  6 +-
 src/mesa/drivers/dri/i965/intel_batchbuffer.h |  2 +-
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 93 +--
 src/mesa/drivers/dri/i965/intel_screen.c  |  5 +-
 src/mesa/drivers/dri/i965/intel_screen.h  |  2 +-
 8 files changed, 69 insertions(+), 72 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 898989575b0..5205302c001 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -45,7 +45,6 @@ extern "C" {
 
 struct gen_device_info;
 
-typedef struct _drm_bacon_bufmgr drm_bacon_bufmgr;
 typedef struct _drm_bacon_bo drm_bacon_bo;
 
 struct _drm_bacon_bo {
@@ -75,7 +74,7 @@ struct _drm_bacon_bo {
 #endif
 
/** Buffer manager context associated with this buffer object */
-   drm_bacon_bufmgr *bufmgr;
+   struct brw_bufmgr *bufmgr;
 
/** The GEM handle for this buffer object. */
uint32_t gem_handle;
@@ -142,7 +141,7 @@ struct _drm_bacon_bo {
  * address space or graphics device aperture.  They must be mapped
  * using bo_map() or drm_bacon_gem_bo_map_gtt() to be used by the CPU.
  */
-drm_bacon_bo *drm_bacon_bo_alloc(drm_bacon_bufmgr *bufmgr, const char *name,
+drm_bacon_bo *drm_bacon_bo_alloc(struct brw_bufmgr *bufmgr, const char *name,
 unsigned long size, unsigned int alignment);
 /**
  * Allocate a buffer object, hinting that it will be used as a
@@ -150,7 +149,7 @@ drm_bacon_bo *drm_bacon_bo_alloc(drm_bacon_bufmgr *bufmgr, 
const char *name,
  *
  * This is otherwise the same as bo_alloc.
  */
-drm_bacon_bo *drm_bacon_bo_alloc_for_render(drm_bacon_bufmgr *bufmgr,
+drm_bacon_bo *drm_bacon_bo_alloc_for_render(struct brw_bufmgr *bufmgr,
const char *name,
unsigned long size,
unsigned int alignment);
@@ -170,7 +169,7 @@ drm_bacon_bo 
*drm_bacon_bo_alloc_for_render(drm_bacon_bufmgr *bufmgr,
  * 'tiling_mode' field on return, as well as the pitch value, which
  * may have been rounded up to accommodate for tiling restrictions.
  */
-drm_bacon_bo *drm_bacon_bo_alloc_tiled(drm_bacon_bufmgr *bufmgr,
+drm_bacon_bo *drm_bacon_bo_alloc_tiled(struct brw_bufmgr *bufmgr,
   const char *name,
   int x, int y, int cpp,
   uint32_t *tiling_mode,
@@ -219,7 +218,7 @@ void drm_bacon_bo_wait_rendering(drm_bacon_bo *bo);
 /**
  * Tears down the buffer manager instance.
  */
-void drm_bacon_bufmgr_destroy(drm_bacon_bufmgr *bufmgr);
+void brw_bufmgr_destroy(struct brw_bufmgr *bufmgr);
 
 /**
  * Ask that the buffer be placed in tiling mode
@@ -284,13 +283,13 @@ int drm_bacon_bo_disable_reuse(drm_bacon_bo *bo);
 int drm_bacon_bo_is_reusable(drm_bacon_bo *bo);
 
 /* drm_bacon_bufmgr_gem.c */
-drm_bacon_bufmgr *drm_bacon_bufmgr_gem_init(struct gen_device_info *devinfo,
-   int fd, int batch_size);
-drm_bacon_bo *drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr *bufmgr,
+struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo,
+   int fd, int batch_size);
+drm_bacon_bo *drm_bacon_bo_gem_create_from_name(struct brw_bufmgr *bufmgr,
const char *name,
unsigned int handle);
-void drm_bacon_bufmgr_gem_enable_reuse(drm_bacon_bufmgr *bufmgr);
-void drm_bacon_bufmgr_gem_set_vma_cache_size(drm_bacon_bufmgr *bufmgr,
+void brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr);
+void brw_bufmgr_gem_set_vma_cache_size(struct brw_bufmgr *bufmgr,
 int limit);
 int drm_bacon_gem_bo_map_unsynchronized(drm_bacon_bo *bo);
 int drm_bacon_gem_bo_map_gtt(drm_bacon_bo *bo);
@@ -303,14 +302,14 @@ void drm_bacon_gem_bo_start_gtt_access(drm_bacon_bo *bo, 
int write_enable);
 
 int drm_bacon_gem_bo_wait(drm_bacon_bo *bo, int64_t timeout_ns);
 
-uint32_t brw_create_hw_context(drm_bacon_bufmgr *bufmgr);
-void brw_destroy_hw_context(drm_bacon_bufmgr *bufmgr, uint32_t ctx_id);
+uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr);
+void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id);
 
 int drm_bacon_bo_gem_export_to_prime(drm_bacon_bo *bo, int *prime_fd);
-drm_bacon_bo *drm_bacon_bo_gem_create_from_prime(drm_bacon_bufmgr *bufmgr,
+drm_bacon_bo *drm_bacon_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr,
int prime_fd, int size);
 
-int 

[Mesa-dev] [PATCH 34/53] i965/drm: Drop GEM_SW_FINISH stuff.

[Kenneth Graunke]

This is only useful when doing an incoherent CPU mapping of the current
scanout buffer.  That's a terrible plan, so we never do it.  We always
use an uncached GTT map.

So, this is useless.  Drop the code.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 24 
 1 file changed, 24 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 466d9776130..9412a66bc7a 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -235,9 +235,6 @@ struct _drm_bacon_bo_gem {
 * drm_bacon_bufmgr_check_aperture in the common case.
 */
int reloc_tree_size;
-
-   /** Flags that we may need to do the SW_FINISH ioctl on unmap. */
-   bool mapped_cpu_write;
 };
 
 static unsigned int
@@ -1160,9 +1157,6 @@ drm_bacon_bo_map(drm_bacon_bo *bo, int write_enable)
strerror(errno));
}
 
-   if (write_enable)
-   bo_gem->mapped_cpu_write = true;
-
drm_bacon_gem_bo_mark_mmaps_incoherent(bo);
VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size));
pthread_mutex_unlock(>lock);
@@ -1342,24 +1336,6 @@ drm_bacon_bo_unmap(drm_bacon_bo *bo)
return 0;
}
 
-   if (bo_gem->mapped_cpu_write) {
-   struct drm_i915_gem_sw_finish sw_finish;
-
-   /* Cause a flush to happen if the buffer's pinned for
-* scanout, so the results show up in a timely manner.
-* Unlike GTT set domains, this only does work if the
-* buffer should be scanout-related.
-*/
-   memclear(sw_finish);
-   sw_finish.handle = bo_gem->gem_handle;
-   ret = drmIoctl(bufmgr->fd,
-  DRM_IOCTL_I915_GEM_SW_FINISH,
-  _finish);
-   ret = ret == -1 ? -errno : 0;
-
-   bo_gem->mapped_cpu_write = false;
-   }
-
/* We need to unmap after every innovation as we cannot track
 * an open vma for every bo as that will exhaust the system
 * limits and cause later failures.
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 37/53] i965: Make/use a brw_batch_references() wrapper.

[Kenneth Graunke]

We'll want to change the implementation of this shortly.
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 6 +++---
 src/mesa/drivers/dri/i965/brw_queryobj.c  | 4 ++--
 src/mesa/drivers/dri/i965/gen6_queryobj.c | 2 +-
 src/mesa/drivers/dri/i965/gen6_sol.c  | 2 +-
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 5 +
 src/mesa/drivers/dri/i965/intel_batchbuffer.h | 2 ++
 src/mesa/drivers/dri/i965/intel_buffer_objects.c  | 6 +++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
 src/mesa/drivers/dri/i965/intel_pixel_read.c  | 2 +-
 src/mesa/drivers/dri/i965/intel_tex_image.c   | 2 +-
 src/mesa/drivers/dri/i965/intel_tex_subimage.c| 2 +-
 11 files changed, 21 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index dfea2f4bd57..c9ba4fe9256 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1132,7 +1132,7 @@ brw_wait_perf_query(struct gl_context *ctx, struct 
gl_perf_query_object *o)
/* If the current batch references our results bo then we need to
 * flush first...
 */
-   if (drm_bacon_bo_references(brw->batch.bo, bo))
+   if (brw_batch_references(>batch, bo))
   intel_batchbuffer_flush(brw);
 
if (unlikely(brw->perf_debug)) {
@@ -1157,12 +1157,12 @@ brw_is_perf_query_ready(struct gl_context *ctx,
case OA_COUNTERS:
   return (obj->oa.results_accumulated ||
   (obj->oa.bo &&
-   !drm_bacon_bo_references(brw->batch.bo, obj->oa.bo) &&
+   !brw_batch_references(>batch, obj->oa.bo) &&
!drm_bacon_bo_busy(obj->oa.bo)));
 
case PIPELINE_STATS:
   return (obj->pipeline_stats.bo &&
-  !drm_bacon_bo_references(brw->batch.bo, obj->pipeline_stats.bo) 
&&
+  !brw_batch_references(>batch, obj->pipeline_stats.bo) &&
   !drm_bacon_bo_busy(obj->pipeline_stats.bo));
}
 
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c 
b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 04dfc5d5767..8e742af67df 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -137,7 +137,7 @@ brw_queryobj_get_results(struct gl_context *ctx,
 * still contributing to it, flush it now so the results will be present
 * when mapped.
 */
-   if (drm_bacon_bo_references(brw->batch.bo, query->bo))
+   if (brw_batch_references(>batch, query->bo))
   intel_batchbuffer_flush(brw);
 
if (unlikely(brw->perf_debug)) {
@@ -402,7 +402,7 @@ static void brw_check_query(struct gl_context *ctx, struct 
gl_query_object *q)
 *  not ready yet on the first time it is queried.  This ensures that
 *  the async query will return true in finite time.
 */
-   if (query->bo && drm_bacon_bo_references(brw->batch.bo, query->bo))
+   if (query->bo && brw_batch_references(>batch, query->bo))
   intel_batchbuffer_flush(brw);
 
if (query->bo == NULL || !drm_bacon_bo_busy(query->bo)) {
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c 
b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index b439b2d2019..b61967bb57f 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -467,7 +467,7 @@ flush_batch_if_needed(struct brw_context *brw, struct 
brw_query_object *query)
 * (for example, due to being full).  Record that it's been flushed.
 */
query->flushed = query->flushed ||
-  !drm_bacon_bo_references(brw->batch.bo, query->bo);
+!brw_batch_references(>batch, query->bo);
 
if (!query->flushed)
   intel_batchbuffer_flush(brw);
diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c 
b/src/mesa/drivers/dri/i965/gen6_sol.c
index 4c73119c953..f7b53b20501 100644
--- a/src/mesa/drivers/dri/i965/gen6_sol.c
+++ b/src/mesa/drivers/dri/i965/gen6_sol.c
@@ -241,7 +241,7 @@ tally_prims_generated(struct brw_context *brw,
/* If the current batch is still contributing to the number of primitives
 * generated, flush it now so the results will be present when mapped.
 */
-   if (drm_bacon_bo_references(brw->batch.bo, obj->prim_count_bo))
+   if (brw_batch_references(>batch, obj->prim_count_bo))
   intel_batchbuffer_flush(brw);
 
if (unlikely(brw->perf_debug && drm_bacon_bo_busy(obj->prim_count_bo)))
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index cf69927f54c..59ab55d31f7 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -576,6 +576,11 @@ _intel_batchbuffer_flush_fence(struct brw_context *brw,
return ret;
 }
 
+bool
+brw_batch_references(struct intel_batchbuffer *batch, drm_bacon_bo *bo)
+{
+   return drm_bacon_bo_references(batch->bo, bo);
+}
 
 /*  This is the only way buffers get added to the validate list.
  */
diff 

[Mesa-dev] [PATCH 36/53] i965: Use brw_emit_reloc() instead of drm_bacon_bo_emit_reloc().

[Kenneth Graunke]

I'm about to make brw_emit_reloc do actual work, so everybody needs
to start using it and not the raw drm_bacon function.
---
 src/mesa/drivers/dri/i965/brw_cc.c   | 10 +++---
 src/mesa/drivers/dri/i965/brw_clip_state.c   | 11 +++---
 src/mesa/drivers/dri/i965/brw_context.h  | 18 --
 src/mesa/drivers/dri/i965/brw_gs_state.c |  1 +
 src/mesa/drivers/dri/i965/brw_sampler_state.c|  7 ++--
 src/mesa/drivers/dri/i965/brw_sf_state.c | 15 +
 src/mesa/drivers/dri/i965/brw_vs_state.c | 26 +++---
 src/mesa/drivers/dri/i965/brw_wm_state.c | 26 +++---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 43 +---
 src/mesa/drivers/dri/i965/genX_blorp_exec.c  |  5 ++-
 src/mesa/drivers/dri/i965/intel_batchbuffer.h| 15 +
 11 files changed, 82 insertions(+), 95 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_cc.c 
b/src/mesa/drivers/dri/i965/brw_cc.c
index c47e7343d81..21b01f3bb18 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -236,11 +236,11 @@ static void upload_cc_unit(struct brw_context *brw)
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 
/* Emit CC viewport relocation */
-   drm_bacon_bo_emit_reloc(brw->batch.bo,
-  (brw->cc.state_offset +
-   offsetof(struct brw_cc_unit_state, cc4)),
-  brw->batch.bo, brw->cc.vp_offset,
-  I915_GEM_DOMAIN_INSTRUCTION, 0);
+   brw_emit_reloc(>batch,
+  (brw->cc.state_offset +
+   offsetof(struct brw_cc_unit_state, cc4)),
+  brw->batch.bo, brw->cc.vp_offset,
+  I915_GEM_DOMAIN_INSTRUCTION, 0);
 }
 
 const struct brw_tracked_state brw_cc_unit = {
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c 
b/src/mesa/drivers/dri/i965/brw_clip_state.c
index 148b98f14d8..5e084a9961d 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_state.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_state.c
@@ -29,6 +29,7 @@
   *   Keith Whitwell 
   */
 
+#include "intel_batchbuffer.h"
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
@@ -136,11 +137,11 @@ brw_upload_clip_unit(struct brw_context *brw)
  (brw->batch.bo->offset64 + brw->clip.vp_offset) >> 5;
 
   /* emit clip viewport relocation */
-  drm_bacon_bo_emit_reloc(brw->batch.bo,
-  (brw->clip.state_offset +
-   offsetof(struct brw_clip_unit_state, clip6)),
-  brw->batch.bo, brw->clip.vp_offset,
-  I915_GEM_DOMAIN_INSTRUCTION, 0);
+  brw_emit_reloc(>batch,
+ (brw->clip.state_offset +
+  offsetof(struct brw_clip_unit_state, clip6)),
+ brw->batch.bo, brw->clip.vp_offset,
+ I915_GEM_DOMAIN_INSTRUCTION, 0);
}
 
/* _NEW_TRANSFORM */
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 8d94b418777..00e9224d7d7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1609,24 +1609,6 @@ brw_program_const(const struct gl_program *p)
return (const struct brw_program *) p;
 }
 
-static inline uint32_t
-brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
- uint32_t prog_offset)
-{
-   if (brw->gen >= 5) {
-  /* Using state base address. */
-  return prog_offset;
-   }
-
-   drm_bacon_bo_emit_reloc(brw->batch.bo,
-  state_offset,
-  brw->cache.bo,
-  prog_offset,
-  I915_GEM_DOMAIN_INSTRUCTION, 0);
-
-   return brw->cache.bo->offset64 + prog_offset;
-}
-
 static inline bool
 brw_depth_writes_enabled(const struct brw_context *brw)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_gs_state.c 
b/src/mesa/drivers/dri/i965/brw_gs_state.c
index acd0f5f877d..ed9ae44bcdb 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_state.c
@@ -34,6 +34,7 @@
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
+#include "intel_batchbuffer.h"
 
 static void
 brw_upload_gs_unit(struct brw_context *brw)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c 
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index ff338809aa6..5d57a35f20f 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -104,10 +104,9 @@ brw_emit_sampler_state(struct brw_context *brw,
ss[2] = border_color_offset;
if (brw->gen < 6) {
   ss[2] += brw->batch.bo->offset64; /* reloc */
-  drm_bacon_bo_emit_reloc(brw->batch.bo,
-  batch_offset_for_sampler_state + 8,
-  brw->batch.bo, 

[Mesa-dev] [PATCH 40/53] i965/drm: Rewrite relocation handling.

[Kenneth Graunke]

The execbuf2 kernel API requires us to construct two kinds of lists.
First is a "validation list" (struct drm_i915_gem_exec_object2[])
containing each BO referenced by the batch.  (The batch buffer itself
must be the last entry in this list.)  Each validation list entry
contains a pointer to the second kind of list: a relocation list.
The relocation list contains information about pointers to BOs that
the kernel may need to patch up if it relocates objects within the VMA.

This is a very general mechanism, allowing every BO to contain pointers
to other BOs.  libdrm_intel models this by giving each drm_intel_bo a
list of relocations to other BOs.  Together, these form "reloc trees".

Processing relocations involves a depth-first-search of the relocation
trees, starting from the batch buffer.  Care has to be taken not to
double-visit buffers.  Creating the validation list has to be deferred
until the last minute, after all relocations are emitted, so we have the
full tree present.  Calculating the amount of aperture space required to
pin those BOs also involves tree walking, which is expensive, so libdrm
has hacks to try and perform less expensive estimates.

For some reason, it also stored the validation list in the global
(per-screen) bufmgr structure, rather than as an local variable in the
execbuffer function, requiring locking for no good reason.

It also assumed that the batch would probably contain a relocation
every 2 DWords - which is absurdly high - and simply aborted if there
were more relocations than the max.  This meant the first relocation
from a BO would allocate 180kB of data structures!

This is way too complicated for our needs.  i965 only emits relocations
from the batchbuffer - all GPU commands and state such as SURFACE_STATE
live in the batch BO.  No other buffer uses relocations.  This means we
can have a single relocation list for the batchbuffer.  We can add a BO
to the validation list (set) the first time we emit a relocation to it.
We can easily keep a running tally of the aperture space required for
that list by adding the BO size when we add it to the validation list.

This patch overhauls the relocation system to do exactly that.  There
are many nice benefits:

- We have a flat relocation list instead of trees.
- We can produce the validation list up front.
- We can allocate smaller arrays and dynamically grow them.
- Aperture space checks are now (a + b <= c) instead of a tree walk.
- brw_batch_references() is a trivial validation list walk.
  It should be straightforward to make it O(1) in the future.
- We don't need to bloat each drm_bacon_bo with 32B of reloc data.
- We don't need to lock in execbuffer, as the data structures are
  context-local, and not per-screen.
- Significantly less code and a better match for what we're doing.
- The simpler system should make it easier to take advantage of
  I915_EXEC_NO_RELOC in a future patch.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h|  53 +-
 src/mesa/drivers/dri/i965/brw_compute.c   |   2 +-
 src/mesa/drivers/dri/i965/brw_context.h   |  12 +
 src/mesa/drivers/dri/i965/brw_draw.c  |   2 +-
 src/mesa/drivers/dri/i965/genX_blorp_exec.c   |   2 +-
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 215 +++-
 src/mesa/drivers/dri/i965/intel_batchbuffer.h |   3 +
 src/mesa/drivers/dri/i965/intel_blit.c|  30 +-
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 718 +-
 9 files changed, 229 insertions(+), 808 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 237f39bb078..d3db6a3967b 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -88,6 +88,15 @@ struct _drm_bacon_bo {
 * entries when calling drm_bacon_bo_emit_reloc()
 */
uint64_t offset64;
+
+   /**
+* Boolean of whether the GPU is definitely not accessing the buffer.
+*
+* This is only valid when reusable, since non-reusable
+* buffers are those that have been shared with other
+* processes, so we don't know their state.
+*/
+   bool idle;
 };
 
 #define BO_ALLOC_FOR_RENDER (1<<0)
@@ -178,37 +187,6 @@ void drm_bacon_bo_wait_rendering(drm_bacon_bo *bo);
  */
 void drm_bacon_bufmgr_destroy(drm_bacon_bufmgr *bufmgr);
 
-/** Executes the command buffer pointed to by bo. */
-int drm_bacon_bo_exec(drm_bacon_bo *bo, int used);
-
-/** Executes the command buffer pointed to by bo on the selected ring buffer */
-int drm_bacon_bo_mrb_exec(drm_bacon_bo *bo, int used, unsigned int flags);
-int drm_bacon_bufmgr_check_aperture_space(drm_bacon_bo ** bo_array, int count);
-
-/**
- * Add relocation entry in reloc_buf, which will be updated with the
- * target buffer's real offset on on command submission.
- *
- * Relocations remain in place for the lifetime of the buffer object.
- *
- * \param bo Buffer to write the relocation into.
- * \param offset Byte 

[Mesa-dev] [PATCH 47/53] i965: Just use a uint32_t context handle rather than a malloc'd wrapper.

[Kenneth Graunke]

drm_bacon_context is a malloc'd struct containing a uint32_t context ID
and a pointer back to the bufmgr.  The bufmgr pointer is pretty useless,
as everybody already has brw->bufmgr.  At that point...we may as well
just use the ctx_id handle directly.  A number of places already had to
call drm_bacon_gem_context_get_id() to extract the ID anyway.  Now they
just have it.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h|  7 +--
 src/mesa/drivers/dri/i965/brw_context.c   |  4 +-
 src/mesa/drivers/dri/i965/brw_context.h   |  2 +-
 src/mesa/drivers/dri/i965/brw_performance_query.c |  6 +--
 src/mesa/drivers/dri/i965/brw_reset.c | 11 ++---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 10 ++---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 52 ---
 7 files changed, 22 insertions(+), 70 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 026cc00c792..898989575b0 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -46,7 +46,6 @@ extern "C" {
 struct gen_device_info;
 
 typedef struct _drm_bacon_bufmgr drm_bacon_bufmgr;
-typedef struct _drm_bacon_context drm_bacon_context;
 typedef struct _drm_bacon_bo drm_bacon_bo;
 
 struct _drm_bacon_bo {
@@ -304,10 +303,8 @@ void drm_bacon_gem_bo_start_gtt_access(drm_bacon_bo *bo, 
int write_enable);
 
 int drm_bacon_gem_bo_wait(drm_bacon_bo *bo, int64_t timeout_ns);
 
-drm_bacon_context *drm_bacon_gem_context_create(drm_bacon_bufmgr *bufmgr);
-int drm_bacon_gem_context_get_id(drm_bacon_context *ctx,
- uint32_t *ctx_id);
-void drm_bacon_gem_context_destroy(drm_bacon_context *ctx);
+uint32_t brw_create_hw_context(drm_bacon_bufmgr *bufmgr);
+void brw_destroy_hw_context(drm_bacon_bufmgr *bufmgr, uint32_t ctx_id);
 
 int drm_bacon_bo_gem_export_to_prime(drm_bacon_bo *bo, int *prime_fd);
 drm_bacon_bo *drm_bacon_bo_gem_create_from_prime(drm_bacon_bufmgr *bufmgr,
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 077a0cab71b..97fd9bdad33 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1094,7 +1094,7 @@ brwCreateContext(gl_api api,
* This is required for transform feedback buffer offsets, query objects,
* and also allows us to reduce how much state we have to emit.
*/
-  brw->hw_ctx = drm_bacon_gem_context_create(brw->bufmgr);
+  brw->hw_ctx = brw_create_hw_context(brw->bufmgr);
 
   if (!brw->hw_ctx) {
  fprintf(stderr, "Failed to create hardware context.\n");
@@ -1200,7 +1200,7 @@ intelDestroyContext(__DRIcontext * driContextPriv)
if (brw->wm.base.scratch_bo)
   drm_bacon_bo_unreference(brw->wm.base.scratch_bo);
 
-   drm_bacon_gem_context_destroy(brw->hw_ctx);
+   brw_destroy_hw_context(brw->bufmgr, brw->hw_ctx);
 
if (ctx->swrast_context) {
   _swsetup_DestroyContext(>ctx);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 186ce826801..e6a0594edc5 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -670,7 +670,7 @@ struct brw_context
 
drm_bacon_bufmgr *bufmgr;
 
-   drm_bacon_context *hw_ctx;
+   uint32_t hw_ctx;
 
/** BO for post-sync nonzero writes for gen6 workaround. */
drm_bacon_bo *workaround_bo;
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index c9ba4fe9256..a0f4d9b2903 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -948,12 +948,8 @@ brw_begin_perf_query(struct gl_context *ctx,
   /* If the OA counters aren't already on, enable them. */
   if (brw->perfquery.oa_stream_fd == -1) {
  __DRIscreen *screen = brw->screen->driScrnPriv;
- uint32_t ctx_id;
  int period_exponent;
 
- if (drm_bacon_gem_context_get_id(brw->hw_ctx, _id) != 0)
-return false;
-
  /* The timestamp for HSW+ increments every 80ns
   *
   * The period_exponent gives a sampling period as follows:
@@ -973,7 +969,7 @@ brw_begin_perf_query(struct gl_context *ctx,
query->oa_format,
period_exponent,
screen->fd, /* drm fd */
-   ctx_id))
+   brw->hw_ctx))
 return false;
   } else {
  assert(brw->perfquery.current_oa_metrics_set_id ==
diff --git a/src/mesa/drivers/dri/i965/brw_reset.c 
b/src/mesa/drivers/dri/i965/brw_reset.c
index aa68102d2e3..ad8c44f2d1c 100644
--- a/src/mesa/drivers/dri/i965/brw_reset.c
+++ b/src/mesa/drivers/dri/i965/brw_reset.c
@@ -36,16 +36,13 @@ brw_get_graphics_reset_status(struct 

[Mesa-dev] [PATCH 50/53] i965: Drop brw_bo_map[_gtt] wrappers which issue perf warnings.

[Kenneth Graunke]

The stupid reason for eliminating these functions is that I'm about
to rename drm_bacon_bo_map() to brw_bo_map(), which makes the real
function have the short name, rather than the wrapper.

I'm also planning on reworking our mapping code soon, so we use WC
mappings and proper unsynchronized mappings on non-LLC platforms.
It will be easier to do that without thinking about the stall
warnings and wrappers.

My eventual hope is to put the performance warnings in the BO map
function itself, so all callers gain the warning.
---
 src/mesa/drivers/dri/i965/brw_context.h  |  6 ---
 src/mesa/drivers/dri/i965/gen6_queryobj.c|  2 +-
 src/mesa/drivers/dri/i965/intel_buffer_objects.c | 47 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c|  6 +--
 src/mesa/drivers/dri/i965/intel_pixel_read.c |  2 +-
 src/mesa/drivers/dri/i965/intel_tex_image.c  |  2 +-
 src/mesa/drivers/dri/i965/intel_tex_subimage.c   |  2 +-
 7 files changed, 10 insertions(+), 57 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index b40b38d9f61..f5854bf8fb7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1462,12 +1462,6 @@ uint32_t brw_depth_format(struct brw_context *brw, 
mesa_format format);
 /* brw_performance_query.c */
 void brw_init_performance_queries(struct brw_context *brw);
 
-/* intel_buffer_objects.c */
-int brw_bo_map(struct brw_context *brw, drm_bacon_bo *bo, int write_enable,
-   const char *bo_name);
-int brw_bo_map_gtt(struct brw_context *brw, drm_bacon_bo *bo,
-   const char *bo_name);
-
 /* intel_extensions.c */
 extern void intelInitExtensions(struct gl_context *ctx);
 
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c 
b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index b61967bb57f..d8edc079174 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -212,7 +212,7 @@ gen6_queryobj_get_results(struct gl_context *ctx,
if (query->bo == NULL)
   return;
 
-   brw_bo_map(brw, query->bo, false, "query object");
+   drm_bacon_bo_map(query->bo, false);
uint64_t *results = query->bo->virtual;
switch (query->Base.Target) {
case GL_TIME_ELAPSED:
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c 
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index 54a58df11d8..e9bd8a095c9 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -39,46 +39,6 @@
 #include "intel_buffer_objects.h"
 #include "intel_batchbuffer.h"
 
-/**
- * Map a buffer object; issue performance warnings if mapping causes stalls.
- *
- * This matches the drm_bacon_bo_map API, but takes an additional 
human-readable
- * name for the buffer object to use in the performance debug message.
- */
-int
-brw_bo_map(struct brw_context *brw,
-   drm_bacon_bo *bo, int write_enable,
-   const char *bo_name)
-{
-   if (likely(!brw->perf_debug) || !drm_bacon_bo_busy(bo))
-  return drm_bacon_bo_map(bo, write_enable);
-
-   double start_time = get_time();
-
-   int ret = drm_bacon_bo_map(bo, write_enable);
-
-   perf_debug("CPU mapping a busy %s BO stalled and took %.03f ms.\n",
-  bo_name, (get_time() - start_time) * 1000);
-
-   return ret;
-}
-
-int
-brw_bo_map_gtt(struct brw_context *brw, drm_bacon_bo *bo, const char *bo_name)
-{
-   if (likely(!brw->perf_debug) || !drm_bacon_bo_busy(bo))
-  return drm_bacon_gem_bo_map_gtt(bo);
-
-   double start_time = get_time();
-
-   int ret = drm_bacon_gem_bo_map_gtt(bo);
-
-   perf_debug("GTT mapping a busy %s BO stalled and took %.03f ms.\n",
-  bo_name, (get_time() - start_time) * 1000);
-
-   return ret;
-}
-
 static void
 mark_buffer_gpu_usage(struct intel_buffer_object *intel_obj,
uint32_t offset, uint32_t size)
@@ -429,8 +389,8 @@ brw_map_buffer_range(struct gl_context *ctx,
   
intel_obj->map_extra[index],
   alignment);
   if (brw->has_llc) {
- brw_bo_map(brw, intel_obj->range_map_bo[index],
-(access & GL_MAP_WRITE_BIT) != 0, "range-map");
+ drm_bacon_bo_map(intel_obj->range_map_bo[index],
+  (access & GL_MAP_WRITE_BIT) != 0);
   } else {
  drm_bacon_gem_bo_map_gtt(intel_obj->range_map_bo[index]);
   }
@@ -450,8 +410,7 @@ brw_map_buffer_range(struct gl_context *ctx,
   drm_bacon_gem_bo_map_gtt(intel_obj->buffer);
   mark_buffer_inactive(intel_obj);
} else {
-  brw_bo_map(brw, intel_obj->buffer, (access & GL_MAP_WRITE_BIT) != 0,
- "MapBufferRange");
+  drm_bacon_bo_map(intel_obj->buffer, (access & GL_MAP_WRITE_BIT) != 0);
   mark_buffer_inactive(intel_obj);
}
 
diff --git 

[Mesa-dev] [PATCH 39/53] i965/drm: Make register write check handle execbuffer directly.

[Kenneth Graunke]

I'm about to rewrite how relocation handling works, at which point
drm_bacon_bo_emit_reloc() and drm_bacon_bo_mrb_exec() won't exist
anymore.  This code is already largely not using the batchbuffer
infrastructure, so just go all the way and handle relocations, the
validation list, and execbuffer ourselves.  That way, we don't have
to think the weird case where we only have a screen, and no context,
when redesigning the relocation handling.
---
 src/mesa/drivers/dri/i965/intel_screen.c | 38 ++--
 1 file changed, 31 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 4cecd52f36a..42baadf25e1 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1367,6 +1367,9 @@ static bool
 intel_detect_pipelined_register(struct intel_screen *screen,
 int reg, uint32_t expected_value, bool reset)
 {
+   if (screen->no_hw)
+  return false;
+
drm_bacon_bo *results, *bo;
uint32_t *batch;
uint32_t offset = 0;
@@ -1394,11 +1397,14 @@ intel_detect_pipelined_register(struct intel_screen 
*screen,
/* Save the register's value back to the buffer. */
*batch++ = MI_STORE_REGISTER_MEM | (3 - 2);
*batch++ = reg;
-   drm_bacon_bo_emit_reloc(bo, (char *)batch -(char *)bo->virtual,
-   results, offset*sizeof(uint32_t),
-   I915_GEM_DOMAIN_INSTRUCTION,
-   I915_GEM_DOMAIN_INSTRUCTION);
-   *batch++ = ((uint32_t) results->offset64) + offset*sizeof(uint32_t);
+   struct drm_i915_gem_relocation_entry reloc = {
+  .offset = (char *) batch - (char *) bo->virtual,
+  .delta = offset * sizeof(uint32_t),
+  .target_handle = results->handle,
+  .read_domains = I915_GEM_DOMAIN_INSTRUCTION,
+  .write_domain = I915_GEM_DOMAIN_INSTRUCTION,
+   };
+   *batch++ = offset * sizeof(uint32_t);
 
/* And afterwards clear the register */
if (reset) {
@@ -1409,8 +1415,26 @@ intel_detect_pipelined_register(struct intel_screen 
*screen,
 
*batch++ = MI_BATCH_BUFFER_END;
 
-   drm_bacon_bo_mrb_exec(bo, ALIGN((char *)batch - (char *)bo->virtual, 8),
- I915_EXEC_RENDER);
+   struct drm_i915_gem_exec_object2 exec_objects[2] = {
+  {
+ .handle = results->handle,
+  },
+  {
+ .handle = bo->handle,
+ .relocation_count = 1,
+ .relocs_ptr = (uintptr_t) ,
+  }
+   };
+
+   struct drm_i915_gem_execbuffer2 execbuf = {
+  .buffers_ptr = (uintptr_t) exec_objects,
+  .buffer_count = 2,
+  .batch_len = ALIGN((char *) batch - (char *) bo->virtual, 8),
+  .flags = I915_EXEC_RENDER,
+   };
+
+   __DRIscreen *dri_screen = screen->driScrnPriv;
+   drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, );
 
/* Check whether the value got written. */
if (drm_bacon_bo_map(results, false) == 0) {
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 38/53] i965: Make a screen::aperture_threshold field.

[Kenneth Graunke]

This is the threshold after which drm_intel_bufmgr_check_aperture_space
returns -ENOSPC, signalling that it thinks an execbuf is likely to fail
and we need to roll back and flush the batch.

We'll need this when we rewrite aperture space checking, shortly.
In the meantime, we can also use it in GLX_MESA_query_renderer.
---
 src/mesa/drivers/dri/i965/intel_screen.c | 6 +++---
 src/mesa/drivers/dri/i965/intel_screen.h | 3 +++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index e45910ce12b..4cecd52f36a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -983,10 +983,8 @@ brw_query_renderer_integer(__DRIscreen *dri_screen,
* assume that there's some fragmentation, and we start doing extra
* flushing, etc.  That's the big cliff apps will care about.
*/
-  uint64_t aper_size = get_aperture_size(dri_screen->fd);
-
   const unsigned gpu_mappable_megabytes =
- (aper_size / (1024 * 1024)) * 3 / 4;
+ screen->aperture_threshold / (1024 * 1024);
 
   const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
   const long system_page_size = sysconf(_SC_PAGE_SIZE);
@@ -1859,6 +1857,8 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
   screen->max_gtt_map_object_size = gtt_size / 4;
}
 
+   screen->aperture_threshold = get_aperture_size(dri_screen->fd) * 3 / 4;
+
screen->hw_has_swizzling = intel_detect_swizzling(screen);
screen->hw_has_timestamp = intel_detect_timestamp(screen);
 
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h 
b/src/mesa/drivers/dri/i965/intel_screen.h
index 8c9ed1662b1..f6727d95cd7 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -50,6 +50,9 @@ struct intel_screen
 
uint64_t max_gtt_map_object_size;
 
+   /** Bytes of aperture usage beyond which execbuf is likely to fail. */
+   uint64_t aperture_threshold;
+
bool no_hw;
bool hw_has_swizzling;
bool has_exec_fence; /**< I915_PARAM_HAS_EXEC_FENCE */
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 45/53] i965/drm: Rename drm_bacon_gem_bo_bucket to bo_cache_bucket.

[Kenneth Graunke]

No need for a prefix as this struct is local to the .c file.

Less bacon.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 2ec2cd325d4..75b1344286a 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -95,7 +95,7 @@ struct _drm_bacon_context {
struct _drm_bacon_bufmgr *bufmgr;
 };
 
-struct drm_bacon_gem_bo_bucket {
+struct bo_cache_bucket {
struct list_head head;
unsigned long size;
 };
@@ -106,7 +106,7 @@ typedef struct _drm_bacon_bufmgr {
pthread_mutex_t lock;
 
/** Array of lists of cached gem objects of power-of-two sizes */
-   struct drm_bacon_gem_bo_bucket cache_bucket[14 * 4];
+   struct bo_cache_bucket cache_bucket[14 * 4];
int num_buckets;
time_t time;
 
@@ -181,13 +181,13 @@ bo_tile_pitch(drm_bacon_bufmgr *bufmgr,
return ALIGN(pitch, tile_width);
 }
 
-static struct drm_bacon_gem_bo_bucket *
+static struct bo_cache_bucket *
 bucket_for_size(drm_bacon_bufmgr *bufmgr, unsigned long size)
 {
int i;
 
for (i = 0; i < bufmgr->num_buckets; i++) {
-   struct drm_bacon_gem_bo_bucket *bucket =
+   struct bo_cache_bucket *bucket =
>cache_bucket[i];
if (bucket->size >= size) {
return bucket;
@@ -240,7 +240,7 @@ drm_bacon_bo_madvise(drm_bacon_bo *bo, int state)
 /* drop the oldest entries that have been purged by the kernel */
 static void
 drm_bacon_gem_bo_cache_purge_bucket(drm_bacon_bufmgr *bufmgr,
-   struct drm_bacon_gem_bo_bucket *bucket)
+   struct bo_cache_bucket *bucket)
 {
while (!list_empty(>head)) {
drm_bacon_bo *bo;
@@ -266,7 +266,7 @@ bo_alloc_internal(drm_bacon_bufmgr *bufmgr,
drm_bacon_bo *bo;
unsigned int page_size = getpagesize();
int ret;
-   struct drm_bacon_gem_bo_bucket *bucket;
+   struct bo_cache_bucket *bucket;
bool alloc_from_cache;
unsigned long bo_size;
bool for_render = false;
@@ -616,7 +616,7 @@ cleanup_bo_cache(drm_bacon_bufmgr *bufmgr, time_t time)
return;
 
for (i = 0; i < bufmgr->num_buckets; i++) {
-   struct drm_bacon_gem_bo_bucket *bucket =
+   struct bo_cache_bucket *bucket =
>cache_bucket[i];
 
while (!list_empty(>head)) {
@@ -708,7 +708,7 @@ static void
 bo_unreference_final(drm_bacon_bo *bo, time_t time)
 {
drm_bacon_bufmgr *bufmgr = bo->bufmgr;
-   struct drm_bacon_gem_bo_bucket *bucket;
+   struct bo_cache_bucket *bucket;
 
DBG("bo_unreference final: %d (%s)\n",
bo->gem_handle, bo->name);
@@ -1145,7 +1145,7 @@ drm_bacon_bufmgr_destroy(drm_bacon_bufmgr *bufmgr)
 
/* Free any cached buffer objects we were going to reuse */
for (int i = 0; i < bufmgr->num_buckets; i++) {
-   struct drm_bacon_gem_bo_bucket *bucket =
+   struct bo_cache_bucket *bucket =
>cache_bucket[i];
drm_bacon_bo *bo;
 
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 46/53] i965/drm: Fold drm_bacon_gem_reset_stats into the callers.

[Kenneth Graunke]

---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  5 
 src/mesa/drivers/dri/i965/brw_reset.c| 36 +---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 32 -
 3 files changed, 17 insertions(+), 56 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 87e67602bd9..026cc00c792 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -317,11 +317,6 @@ int drm_bacon_reg_read(drm_bacon_bufmgr *bufmgr,
   uint32_t offset,
   uint64_t *result);
 
-int drm_bacon_get_reset_stats(drm_bacon_context *ctx,
- uint32_t *reset_count,
- uint32_t *active,
- uint32_t *pending);
-
 /** @{ */
 
 #if defined(__cplusplus)
diff --git a/src/mesa/drivers/dri/i965/brw_reset.c 
b/src/mesa/drivers/dri/i965/brw_reset.c
index b91ffd723b9..aa68102d2e3 100644
--- a/src/mesa/drivers/dri/i965/brw_reset.c
+++ b/src/mesa/drivers/dri/i965/brw_reset.c
@@ -23,6 +23,7 @@
 
 #include "main/context.h"
 
+#include 
 #include "brw_context.h"
 
 /**
@@ -34,10 +35,8 @@ GLenum
 brw_get_graphics_reset_status(struct gl_context *ctx)
 {
struct brw_context *brw = brw_context(ctx);
-   int err;
-   uint32_t reset_count;
-   uint32_t active;
-   uint32_t pending;
+   __DRIscreen *dri_screen = brw->screen->driScrnPriv;
+   struct drm_i915_reset_stats stats;
 
/* If hardware contexts are not being used (or
 * DRM_IOCTL_I915_GET_RESET_STATS is not supported), this function should
@@ -45,6 +44,9 @@ brw_get_graphics_reset_status(struct gl_context *ctx)
 */
assert(brw->hw_ctx != NULL);
 
+   memset(, 0, sizeof(stats));
+   drm_bacon_gem_context_get_id(brw->hw_ctx, _id);
+
/* A reset status other than NO_ERROR was returned last time. I915 returns
 * nonzero active/pending only if reset has been encountered and completed.
 * Return NO_ERROR from now on.
@@ -52,16 +54,14 @@ brw_get_graphics_reset_status(struct gl_context *ctx)
if (brw->reset_count != 0)
   return GL_NO_ERROR;
 
-   err = drm_bacon_get_reset_stats(brw->hw_ctx, _count, ,
-   );
-   if (err)
+   if (drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, ) != 0)
   return GL_NO_ERROR;
 
/* A reset was observed while a batch from this context was executing.
 * Assume that this context was at fault.
 */
-   if (active != 0) {
-  brw->reset_count = reset_count;
+   if (stats.batch_active != 0) {
+  brw->reset_count = stats.reset_count;
   return GL_GUILTY_CONTEXT_RESET_ARB;
}
 
@@ -69,8 +69,8 @@ brw_get_graphics_reset_status(struct gl_context *ctx)
 * but the batch was not executing.  In this case, assume that the context
 * was not at fault.
 */
-   if (pending != 0) {
-  brw->reset_count = reset_count;
+   if (stats.batch_pending != 0) {
+  brw->reset_count = stats.reset_count;
   return GL_INNOCENT_CONTEXT_RESET_ARB;
}
 
@@ -80,16 +80,14 @@ brw_get_graphics_reset_status(struct gl_context *ctx)
 void
 brw_check_for_reset(struct brw_context *brw)
 {
-   uint32_t reset_count;
-   uint32_t active;
-   uint32_t pending;
-   int err;
+   __DRIscreen *dri_screen = brw->screen->driScrnPriv;
+   struct drm_i915_reset_stats stats;
+   memset(, 0, sizeof(stats));
+   drm_bacon_gem_context_get_id(brw->hw_ctx, _id);
 
-   err = drm_bacon_get_reset_stats(brw->hw_ctx, _count, ,
-   );
-   if (err)
+   if (drmIoctl(dri_screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, ) != 0)
   return;
 
-   if (active > 0 || pending > 0)
+   if (stats.batch_active > 0 || stats.batch_pending > 0)
   _mesa_set_context_lost_dispatch(>ctx);
 }
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 75b1344286a..317265b65cf 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -1478,38 +1478,6 @@ drm_bacon_gem_context_destroy(drm_bacon_context *ctx)
 }
 
 int
-drm_bacon_get_reset_stats(drm_bacon_context *ctx,
- uint32_t *reset_count,
- uint32_t *active,
- uint32_t *pending)
-{
-   struct drm_i915_reset_stats stats;
-   int ret;
-
-   if (ctx == NULL)
-   return -EINVAL;
-
-   memclear(stats);
-
-   stats.ctx_id = ctx->ctx_id;
-   ret = drmIoctl(ctx->bufmgr->fd,
-  DRM_IOCTL_I915_GET_RESET_STATS,
-  );
-   if (ret == 0) {
-   if (reset_count != NULL)
-   *reset_count = stats.reset_count;
-
-   if (active != NULL)
-   *active = stats.batch_active;
-
-   if (pending != NULL)
-   *pending = stats.batch_pending;
-   }
-
-   return ret;

[Mesa-dev] [PATCH 32/53] i965/drm: Unwrap the unnecessary drm_bacon_reloc_target_info struct.

[Kenneth Graunke]

This used to have another field, but now it's just a BO pointer.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 45 
 1 file changed, 19 insertions(+), 26 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 98f2e131377..eb6a5e742b1 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -151,10 +151,6 @@ typedef struct _drm_bacon_bufmgr {
unsigned int no_exec : 1;
 } drm_bacon_bufmgr;
 
-typedef struct _drm_bacon_reloc_target_info {
-   drm_bacon_bo *bo;
-} drm_bacon_reloc_target;
-
 struct _drm_bacon_bo_gem {
drm_bacon_bo bo;
 
@@ -189,7 +185,7 @@ struct _drm_bacon_bo_gem {
/**
 * Array of info structs corresponding to relocs[i].target_handle etc
 */
-   drm_bacon_reloc_target *reloc_target_info;
+   drm_bacon_bo **reloc_bos;
/** Number of entries in relocs */
int reloc_count;
/** Mapped address for the buffer, saved across map/unmap cycles */
@@ -358,7 +354,7 @@ drm_bacon_gem_dump_validation_list(drm_bacon_bufmgr *bufmgr)
}
 
for (j = 0; j < bo_gem->reloc_count; j++) {
-   drm_bacon_bo *target_bo = 
bo_gem->reloc_target_info[j].bo;
+   drm_bacon_bo *target_bo = bo_gem->reloc_bos[j];
drm_bacon_bo_gem *target_gem =
(drm_bacon_bo_gem *) target_bo;
 
@@ -459,16 +455,15 @@ drm_bacon_setup_reloc_list(drm_bacon_bo *bo)
 
bo_gem->relocs = malloc(max_relocs *
sizeof(struct drm_i915_gem_relocation_entry));
-   bo_gem->reloc_target_info = malloc(max_relocs *
-  sizeof(drm_bacon_reloc_target));
-   if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) {
+   bo_gem->reloc_bos = malloc(max_relocs * sizeof(drm_bacon_bo *));
+   if (bo_gem->relocs == NULL || bo_gem->reloc_bos == NULL) {
bo_gem->has_error = true;
 
free (bo_gem->relocs);
bo_gem->relocs = NULL;
 
-   free (bo_gem->reloc_target_info);
-   bo_gem->reloc_target_info = NULL;
+   free (bo_gem->reloc_bos);
+   bo_gem->reloc_bos = NULL;
 
return 1;
}
@@ -1028,9 +1023,9 @@ drm_bacon_gem_bo_unreference_final(drm_bacon_bo *bo, 
time_t time)
 
/* Unreference all the target buffers */
for (i = 0; i < bo_gem->reloc_count; i++) {
-   if (bo_gem->reloc_target_info[i].bo != bo) {
+   if (bo_gem->reloc_bos[i] != bo) {
drm_bacon_gem_bo_unreference_locked_timed(bo_gem->
- 
reloc_target_info[i].bo,
+ reloc_bos[i],
  time);
}
}
@@ -1041,9 +1036,9 @@ drm_bacon_gem_bo_unreference_final(drm_bacon_bo *bo, 
time_t time)
bo_gem->gem_handle, bo_gem->name);
 
/* release memory associated with this object */
-   if (bo_gem->reloc_target_info) {
-   free(bo_gem->reloc_target_info);
-   bo_gem->reloc_target_info = NULL;
+   if (bo_gem->reloc_bos) {
+   free(bo_gem->reloc_bos);
+   bo_gem->reloc_bos = NULL;
}
if (bo_gem->relocs) {
free(bo_gem->relocs);
@@ -1594,7 +1589,7 @@ drm_bacon_bo_emit_reloc(drm_bacon_bo *bo, uint32_t offset,
bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
}
 
-   bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo;
+   bo_gem->reloc_bos[bo_gem->reloc_count] = target_bo;
if (target_bo != bo)
drm_bacon_bo_reference(target_bo);
 
@@ -1647,7 +1642,7 @@ drm_bacon_gem_bo_clear_relocs(drm_bacon_bo *bo, int start)
pthread_mutex_lock(>lock);
 
for (i = start; i < bo_gem->reloc_count; i++) {
-   drm_bacon_bo_gem *target_bo_gem = (drm_bacon_bo_gem *) 
bo_gem->reloc_target_info[i].bo;
+   drm_bacon_bo_gem *target_bo_gem = (drm_bacon_bo_gem *) 
bo_gem->reloc_bos[i];
if (_bo_gem->bo != bo) {

drm_bacon_gem_bo_unreference_locked_timed(_bo_gem->bo,
  time.tv_sec);
@@ -1669,7 +1664,7 @@ drm_bacon_gem_bo_process_reloc2(drm_bacon_bo *bo)
return;
 
for (i = 0; i < bo_gem->reloc_count; i++) {
-   drm_bacon_bo *target_bo = bo_gem->reloc_target_info[i].bo;
+   drm_bacon_bo *target_bo = bo_gem->reloc_bos[i];
 
if (target_bo == bo)
continue;
@@ -2051,8 +2046,7 @@ drm_bacon_gem_bo_get_aperture_space(drm_bacon_bo *bo)
 

[Mesa-dev] [PATCH 43/53] i965/drm: Drop drm_bacon_gem_bo_madvise_internal().

[Kenneth Graunke]

The only difference is that it takes an explicit bufmgr rather than
using bo->bufmgr, but there is only one bufmgr per screen so they
should be identical anyway.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 22 ++
 1 file changed, 6 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index a1cb8079822..0a6d08b 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -226,9 +226,8 @@ drm_bacon_bo_busy(drm_bacon_bo *bo)
return (ret == 0 && busy.busy);
 }
 
-static int
-drm_bacon_gem_bo_madvise_internal(drm_bacon_bufmgr *bufmgr,
- drm_bacon_bo *bo, int state)
+int
+drm_bacon_bo_madvise(drm_bacon_bo *bo, int state)
 {
struct drm_i915_gem_madvise madv;
 
@@ -236,17 +235,11 @@ drm_bacon_gem_bo_madvise_internal(drm_bacon_bufmgr 
*bufmgr,
madv.handle = bo->gem_handle;
madv.madv = state;
madv.retained = 1;
-   drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MADVISE, );
+   drmIoctl(bo->bufmgr->fd, DRM_IOCTL_I915_GEM_MADVISE, );
 
return madv.retained;
 }
 
-int
-drm_bacon_bo_madvise(drm_bacon_bo *bo, int madv)
-{
-   return drm_bacon_gem_bo_madvise_internal(bo->bufmgr, bo, madv);
-}
-
 /* drop the oldest entries that have been purged by the kernel */
 static void
 drm_bacon_gem_bo_cache_purge_bucket(drm_bacon_bufmgr *bufmgr,
@@ -256,8 +249,7 @@ drm_bacon_gem_bo_cache_purge_bucket(drm_bacon_bufmgr 
*bufmgr,
drm_bacon_bo *bo;
 
bo = LIST_ENTRY(drm_bacon_bo, bucket->head.next, head);
-   if (drm_bacon_gem_bo_madvise_internal
-   (bufmgr, bo, I915_MADV_DONTNEED))
+   if (drm_bacon_bo_madvise(bo, I915_MADV_DONTNEED))
break;
 
list_del(>head);
@@ -330,8 +322,7 @@ retry:
}
 
if (alloc_from_cache) {
-   if (!drm_bacon_gem_bo_madvise_internal
-   (bufmgr, bo, I915_MADV_WILLNEED)) {
+   if (!drm_bacon_bo_madvise(bo, I915_MADV_WILLNEED)) {
drm_bacon_gem_bo_free(bo);
drm_bacon_gem_bo_cache_purge_bucket(bufmgr,
bucket);
@@ -743,8 +734,7 @@ drm_bacon_gem_bo_unreference_final(drm_bacon_bo *bo, time_t 
time)
bucket = drm_bacon_gem_bo_bucket_for_size(bufmgr, bo->size);
/* Put the buffer into our internal cache for reuse if we can. */
if (bufmgr->bo_reuse && bo->reusable && bucket != NULL &&
-   drm_bacon_gem_bo_madvise_internal(bufmgr, bo,
- I915_MADV_DONTNEED)) {
+   drm_bacon_bo_madvise(bo, I915_MADV_DONTNEED)) {
bo->free_time = time;
 
bo->name = NULL;
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 42/53] i965/drm: Merge drm_bacon_bo_gem into drm_bacon_bo.

[Kenneth Graunke]

The separate class gives us a bit of extra encapsulation, but I don't
know that it's really worth the boilerplate.  I think we can reasonably
expect the rest of the driver to be responsible.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  37 ++
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 554 ---
 2 files changed, 272 insertions(+), 319 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 509664b6e3d..87e67602bd9 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -37,6 +37,7 @@
 #include 
 #include 
 #include 
+#include "util/list.h"
 
 #if defined(__cplusplus)
 extern "C" {
@@ -95,6 +96,42 @@ struct _drm_bacon_bo {
 * processes, so we don't know their state.
 */
bool idle;
+
+   int refcount;
+   const char *name;
+
+   /**
+* Kenel-assigned global name for this object
+ *
+ * List contains both flink named and prime fd'd objects
+*/
+   unsigned int global_name;
+
+   /**
+* Current tiling mode
+*/
+   uint32_t tiling_mode;
+   uint32_t swizzle_mode;
+   unsigned long stride;
+
+   time_t free_time;
+
+   /** Mapped address for the buffer, saved across map/unmap cycles */
+   void *mem_virtual;
+   /** GTT virtual address for the buffer, saved across map/unmap cycles */
+   void *gtt_virtual;
+   /** WC CPU address for the buffer, saved across map/unmap cycles */
+   void *wc_virtual;
+   int map_count;
+   struct list_head vma_list;
+
+   /** BO cache list */
+   struct list_head head;
+
+   /**
+* Boolean of whether this buffer can be re-used
+*/
+   bool reusable;
 };
 
 #define BO_ALLOC_FOR_RENDER (1<<0)
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 022a186bd6d..a1cb8079822 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -95,8 +95,6 @@ struct _drm_bacon_context {
struct _drm_bacon_bufmgr *bufmgr;
 };
 
-typedef struct _drm_bacon_bo_gem drm_bacon_bo_gem;
-
 struct drm_bacon_gem_bo_bucket {
struct list_head head;
unsigned long size;
@@ -122,46 +120,6 @@ typedef struct _drm_bacon_bufmgr {
unsigned int bo_reuse : 1;
 } drm_bacon_bufmgr;
 
-struct _drm_bacon_bo_gem {
-   drm_bacon_bo bo;
-
-   int refcount;
-   const char *name;
-
-   /**
-* Kenel-assigned global name for this object
- *
- * List contains both flink named and prime fd'd objects
-*/
-   unsigned int global_name;
-
-   /**
-* Current tiling mode
-*/
-   uint32_t tiling_mode;
-   uint32_t swizzle_mode;
-   unsigned long stride;
-
-   time_t free_time;
-
-   /** Mapped address for the buffer, saved across map/unmap cycles */
-   void *mem_virtual;
-   /** GTT virtual address for the buffer, saved across map/unmap cycles */
-   void *gtt_virtual;
-   /** WC CPU address for the buffer, saved across map/unmap cycles */
-   void *wc_virtual;
-   int map_count;
-   struct list_head vma_list;
-
-   /** BO cache list */
-   struct list_head head;
-
-   /**
-* Boolean of whether this buffer can be re-used
-*/
-   bool reusable;
-};
-
 static int
 drm_bacon_gem_bo_set_tiling_internal(drm_bacon_bo *bo,
 uint32_t tiling_mode,
@@ -169,11 +127,6 @@ drm_bacon_gem_bo_set_tiling_internal(drm_bacon_bo *bo,
 
 static void drm_bacon_gem_bo_free(drm_bacon_bo *bo);
 
-static inline drm_bacon_bo_gem *to_bo_gem(drm_bacon_bo *bo)
-{
-return (drm_bacon_bo_gem *)bo;
-}
-
 static uint32_t
 key_hash_uint(const void *key)
 {
@@ -186,11 +139,11 @@ key_uint_equal(const void *a, const void *b)
return *((unsigned *) a) == *((unsigned *) b);
 }
 
-static drm_bacon_bo_gem *
+static drm_bacon_bo *
 hash_find_bo(struct hash_table *ht, unsigned int key)
 {
struct hash_entry *entry = _mesa_hash_table_search(ht, );
-   return entry ? (drm_bacon_bo_gem *) entry->data : NULL;
+   return entry ? (drm_bacon_bo *) entry->data : NULL;
 }
 
 static unsigned long
@@ -250,9 +203,7 @@ drm_bacon_gem_bo_bucket_for_size(drm_bacon_bufmgr *bufmgr,
 inline void
 drm_bacon_bo_reference(drm_bacon_bo *bo)
 {
-   drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
-
-   p_atomic_inc(_gem->refcount);
+   p_atomic_inc(>refcount);
 }
 
 int
@@ -277,12 +228,12 @@ drm_bacon_bo_busy(drm_bacon_bo *bo)
 
 static int
 drm_bacon_gem_bo_madvise_internal(drm_bacon_bufmgr *bufmgr,
- drm_bacon_bo_gem *bo_gem, int state)
+ drm_bacon_bo *bo, int state)
 {
struct drm_i915_gem_madvise madv;
 
memclear(madv);
-   madv.handle = 

[Mesa-dev] [PATCH 28/53] i965/drm: Drop softpin support for now.

[Kenneth Graunke]

We may want this eventually, but simplify for now.  We can add it back
later when we actually intend to use it.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |   7 --
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 144 ++-
 2 files changed, 8 insertions(+), 143 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 487abe162b3..96e8571859c 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -256,13 +256,6 @@ int drm_bacon_bo_busy(drm_bacon_bo *bo);
 int drm_bacon_bo_madvise(drm_bacon_bo *bo, int madv);
 
 /**
- * Set the offset at which this buffer will be softpinned
- * \param bo Buffer to set the softpin offset for
- * \param offset Softpin offset
- */
-int drm_bacon_bo_set_softpin_offset(drm_bacon_bo *bo, uint64_t offset);
-
-/**
  * Disable buffer reuse for buffers which will be shared in some way,
  * as with scanout buffers. When the buffer reference count goes to
  * zero, it will be freed and not placed in the reuse list.
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index e5de94b36f0..aa718d714c5 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -198,13 +198,6 @@ struct _drm_bacon_bo_gem {
drm_bacon_reloc_target *reloc_target_info;
/** Number of entries in relocs */
int reloc_count;
-   /** Array of BOs that are referenced by this buffer and will be 
softpinned */
-   drm_bacon_bo **softpin_target;
-   /** Number softpinned BOs that are referenced by this buffer */
-   int softpin_target_count;
-   /** Maximum amount of softpinned BOs that are referenced by this buffer 
*/
-   int softpin_target_size;
-
/** Mapped address for the buffer, saved across map/unmap cycles */
void *mem_virtual;
/** GTT virtual address for the buffer, saved across map/unmap cycles */
@@ -345,9 +338,8 @@ drm_bacon_gem_dump_validation_list(drm_bacon_bufmgr *bufmgr)
drm_bacon_bo *bo = bufmgr->exec_bos[i];
drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
 
-   if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL) {
-   DBG("%2d: %d %s(%s)\n", i, bo_gem->gem_handle,
-   bo_gem->kflags & EXEC_OBJECT_PINNED ? "*" : "",
+   if (bo_gem->relocs == NULL) {
+   DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle,
bo_gem->name);
continue;
}
@@ -357,11 +349,10 @@ drm_bacon_gem_dump_validation_list(drm_bacon_bufmgr 
*bufmgr)
drm_bacon_bo_gem *target_gem =
(drm_bacon_bo_gem *) target_bo;
 
-   DBG("%2d: %d %s(%s)@0x%08x %08x -> "
+   DBG("%2d: %d (%s)@0x%08x %08x -> "
"%d (%s)@0x%08x %08x + 0x%08x\n",
i,
bo_gem->gem_handle,
-   bo_gem->kflags & EXEC_OBJECT_PINNED ? "*" : "",
bo_gem->name,
upper_32_bits(bo_gem->relocs[j].offset),
lower_32_bits(bo_gem->relocs[j].offset),
@@ -371,22 +362,6 @@ drm_bacon_gem_dump_validation_list(drm_bacon_bufmgr 
*bufmgr)
lower_32_bits(target_bo->offset64),
bo_gem->relocs[j].delta);
}
-
-   for (j = 0; j < bo_gem->softpin_target_count; j++) {
-   drm_bacon_bo *target_bo = bo_gem->softpin_target[j];
-   drm_bacon_bo_gem *target_gem =
-   (drm_bacon_bo_gem *) target_bo;
-   DBG("%2d: %d %s(%s) -> "
-   "%d *(%s)@0x%08x %08x\n",
-   i,
-   bo_gem->gem_handle,
-   bo_gem->kflags & EXEC_OBJECT_PINNED ? "*" : "",
-   bo_gem->name,
-   target_gem->gem_handle,
-   target_gem->name,
-   upper_32_bits(target_bo->offset64),
-   lower_32_bits(target_bo->offset64));
-   }
}
 }
 
@@ -1043,13 +1018,9 @@ drm_bacon_gem_bo_unreference_final(drm_bacon_bo *bo, 
time_t time)
  time);
}
}
-   for (i = 0; i < bo_gem->softpin_target_count; i++)
-   
drm_bacon_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i],
- time);
bo_gem->kflags = 0;
bo_gem->reloc_count = 0;
bo_gem->used_as_reloc_target = false;
-   bo_gem->softpin_target_count = 0;
 

[Mesa-dev] [PATCH 35/53] i965: Change intel_batchbuffer_reloc() into brw_emit_reloc().

[Kenneth Graunke]

This renames intel_batchbuffer_reloc to brw_emit_reloc and changes the
parameter naming and ordering to match drm_intel_bo_emit_reloc().

For now, it's a trivial wrapper that accesses batch->bo.  When we
rework relocations, it will start doing actual work.
---
 src/mesa/drivers/dri/i965/genX_blorp_exec.c   |  8 
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 +++
 src/mesa/drivers/dri/i965/intel_batchbuffer.h | 17 +++--
 3 files changed, 18 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c 
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index 7a2c8aaa596..78854e6fada 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -55,10 +55,10 @@ blorp_emit_reloc(struct blorp_batch *batch,
struct brw_context *brw = batch->driver_batch;
 
uint32_t offset = (char *)location - (char *)brw->batch.map;
-   return intel_batchbuffer_reloc(>batch, address.buffer, offset,
-  address.read_domains,
-  address.write_domain,
-  address.offset + delta);
+   return brw_emit_reloc(>batch, offset,
+ address.buffer, address.offset + delta,
+ address.read_domains,
+ address.write_domain);
 }
 
 static void
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index c35d9ca5bda..cf69927f54c 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -580,16 +580,15 @@ _intel_batchbuffer_flush_fence(struct brw_context *brw,
 /*  This is the only way buffers get added to the validate list.
  */
 uint64_t
-intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
-drm_bacon_bo *buffer, uint32_t offset,
-uint32_t read_domains, uint32_t write_domain,
-uint32_t delta)
+brw_emit_reloc(struct intel_batchbuffer *batch, uint32_t batch_offset,
+   drm_bacon_bo *target, uint32_t target_offset,
+   uint32_t read_domains, uint32_t write_domain)
 {
int ret;
 
-   ret = drm_bacon_bo_emit_reloc(batch->bo, offset,
-buffer, delta,
-read_domains, write_domain);
+   ret = drm_bacon_bo_emit_reloc(batch->bo, batch_offset,
+ target, target_offset,
+ read_domains, write_domain);
assert(ret == 0);
(void)ret;
 
@@ -597,7 +596,7 @@ intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
 * case the buffer doesn't move and we can short-circuit the relocation
 * processing in the kernel
 */
-   return buffer->offset64 + delta;
+   return target->offset64 + target_offset;
 }
 
 void
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
index 61b4fef3e3c..d5f0fc025b7 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h
@@ -65,12 +65,9 @@ void intel_batchbuffer_data(struct brw_context *brw,
 const void *data, GLuint bytes,
 enum brw_gpu_ring ring);
 
-uint64_t intel_batchbuffer_reloc(struct intel_batchbuffer *batch,
- drm_bacon_bo *buffer,
- uint32_t offset,
- uint32_t read_domains,
- uint32_t write_domain,
- uint32_t delta);
+uint64_t brw_emit_reloc(struct intel_batchbuffer *batch, uint32_t batch_offset,
+drm_bacon_bo *target, uint32_t target_offset,
+uint32_t read_domains, uint32_t write_domain);
 
 #define USED_BATCH(batch) ((uintptr_t)((batch).map_next - (batch).map))
 
@@ -159,8 +156,8 @@ intel_batchbuffer_advance(struct brw_context *brw)
 #define OUT_RELOC(buf, read_domains, write_domain, delta) do {  \
uint32_t __offset = (__map - brw->batch.map) * 4;\
uint32_t reloc = \
-  intel_batchbuffer_reloc(>batch, (buf), __offset, \
-  (read_domains), (write_domain), (delta)); \
+  brw_emit_reloc(>batch, __offset, (buf), (delta), \
+ (read_domains), (write_domain));   \
OUT_BATCH(reloc);\
 } while (0)
 
@@ -168,8 +165,8 @@ intel_batchbuffer_advance(struct brw_context *brw)
 #define OUT_RELOC64(buf, read_domains, write_domain, delta) do {\
uint32_t __offset = (__map - brw->batch.map) * 4;\
uint64_t reloc64 =   \
-  

[Mesa-dev] [PATCH 22/53] i965/drm: Assume aperture size query will work.

[Kenneth Graunke]

This query has been available since 2.6.28.  We require 3.6.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 17 ++---
 1 file changed, 2 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 440ec16de38..339e2034b06 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -3024,21 +3024,8 @@ drm_bacon_bufmgr_gem_init(int fd, int batch_size)
}
 
memclear(aperture);
-   ret = drmIoctl(bufmgr->fd,
-  DRM_IOCTL_I915_GEM_GET_APERTURE,
-  );
-
-   if (ret == 0)
-   bufmgr->gtt_size = aperture.aper_available_size;
-   else {
-   fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
-   strerror(errno));
-   bufmgr->gtt_size = 128 * 1024 * 1024;
-   fprintf(stderr, "Assuming %dkB available aperture size.\n"
-   "May lead to reduced performance or incorrect "
-   "rendering.\n",
-   (int)bufmgr->gtt_size / 1024);
-   }
+   drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, );
+   bufmgr->gtt_size = aperture.aper_available_size;
 
bufmgr->pci_device = get_pci_device_id(bufmgr);
 
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 30/53] i965/drm: Drop bo_gem::kflags.

[Kenneth Graunke]

It's always zero now.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index fb02b1258eb..499cd19808f 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -185,8 +185,6 @@ struct _drm_bacon_bo_gem {
uint32_t swizzle_mode;
unsigned long stride;
 
-   unsigned long kflags;
-
time_t free_time;
 
/** Array passed to the DRM containing relocation information. */
@@ -406,7 +404,7 @@ drm_bacon_add_validate_buffer2(drm_bacon_bo *bo)
bufmgr->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
bufmgr->exec2_objects[index].alignment = bo->align;
bufmgr->exec2_objects[index].offset = bo->offset64;
-   bufmgr->exec2_objects[index].flags = bo_gem->kflags;
+   bufmgr->exec2_objects[index].flags = 0;
bufmgr->exec2_objects[index].rsvd1 = 0;
bufmgr->exec2_objects[index].rsvd2 = 0;
bufmgr->exec_bos[index] = bo;
@@ -1017,7 +1015,6 @@ drm_bacon_gem_bo_unreference_final(drm_bacon_bo *bo, 
time_t time)
  time);
}
}
-   bo_gem->kflags = 0;
bo_gem->reloc_count = 0;
bo_gem->used_as_reloc_target = false;
 
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 21/53] i965/drm: Combine drm_bacon_bufmgr_gem and drm_bacon_bufmgr classes.

[Kenneth Graunke]

---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 -
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 687 --
 src/mesa/drivers/dri/i965/intel_bufmgr_priv.h |  45 --
 3 files changed, 328 insertions(+), 405 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/intel_bufmgr_priv.h

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 3e73d0f9e2a..9068bcdde7a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -132,7 +132,6 @@ i965_FILES = \
intel_buffers.c \
intel_buffers.h \
intel_bufmgr_gem.c \
-   intel_bufmgr_priv.h \
intel_chipset.h \
intel_copy_image.c \
intel_extensions.c \
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index d0395e78307..440ec16de38 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -62,7 +62,6 @@
 #include "util/macros.h"
 #include "util/list.h"
 #include "brw_bufmgr.h"
-#include "intel_bufmgr_priv.h"
 #include "intel_chipset.h"
 #include "string.h"
 
@@ -119,9 +118,7 @@ struct drm_bacon_gem_bo_bucket {
unsigned long size;
 };
 
-typedef struct _drm_bacon_bufmgr_gem {
-   drm_bacon_bufmgr bufmgr;
-
+typedef struct _drm_bacon_bufmgr {
int refcount;
 
int fd;
@@ -165,7 +162,7 @@ typedef struct _drm_bacon_bufmgr_gem {
uint32_t handle;
} userptr_active;
 
-} drm_bacon_bufmgr_gem;
+} drm_bacon_bufmgr;
 
 typedef struct _drm_bacon_reloc_target_info {
drm_bacon_bo *bo;
@@ -308,7 +305,7 @@ static inline drm_bacon_bo_gem *to_bo_gem(drm_bacon_bo *bo)
 }
 
 static unsigned long
-drm_bacon_gem_bo_tile_size(drm_bacon_bufmgr_gem *bufmgr_gem, unsigned long 
size,
+drm_bacon_gem_bo_tile_size(drm_bacon_bufmgr *bufmgr, unsigned long size,
   uint32_t *tiling_mode)
 {
if (*tiling_mode == I915_TILING_NONE)
@@ -324,7 +321,7 @@ drm_bacon_gem_bo_tile_size(drm_bacon_bufmgr_gem 
*bufmgr_gem, unsigned long size,
  * change.
  */
 static unsigned long
-drm_bacon_gem_bo_tile_pitch(drm_bacon_bufmgr_gem *bufmgr_gem,
+drm_bacon_gem_bo_tile_pitch(drm_bacon_bufmgr *bufmgr,
unsigned long pitch, uint32_t *tiling_mode)
 {
unsigned long tile_width;
@@ -345,14 +342,14 @@ drm_bacon_gem_bo_tile_pitch(drm_bacon_bufmgr_gem 
*bufmgr_gem,
 }
 
 static struct drm_bacon_gem_bo_bucket *
-drm_bacon_gem_bo_bucket_for_size(drm_bacon_bufmgr_gem *bufmgr_gem,
+drm_bacon_gem_bo_bucket_for_size(drm_bacon_bufmgr *bufmgr,
 unsigned long size)
 {
int i;
 
-   for (i = 0; i < bufmgr_gem->num_buckets; i++) {
+   for (i = 0; i < bufmgr->num_buckets; i++) {
struct drm_bacon_gem_bo_bucket *bucket =
-   _gem->cache_bucket[i];
+   >cache_bucket[i];
if (bucket->size >= size) {
return bucket;
}
@@ -362,12 +359,12 @@ drm_bacon_gem_bo_bucket_for_size(drm_bacon_bufmgr_gem 
*bufmgr_gem,
 }
 
 static void
-drm_bacon_gem_dump_validation_list(drm_bacon_bufmgr_gem *bufmgr_gem)
+drm_bacon_gem_dump_validation_list(drm_bacon_bufmgr *bufmgr)
 {
int i, j;
 
-   for (i = 0; i < bufmgr_gem->exec_count; i++) {
-   drm_bacon_bo *bo = bufmgr_gem->exec_bos[i];
+   for (i = 0; i < bufmgr->exec_count; i++) {
+   drm_bacon_bo *bo = bufmgr->exec_bos[i];
drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
 
if (bo_gem->relocs == NULL && bo_gem->softpin_target == NULL) {
@@ -426,7 +423,7 @@ drm_bacon_bo_reference(drm_bacon_bo *bo)
 static void
 drm_bacon_add_validate_buffer2(drm_bacon_bo *bo)
 {
-   drm_bacon_bufmgr_gem *bufmgr_gem = (drm_bacon_bufmgr_gem *)bo->bufmgr;
+   drm_bacon_bufmgr *bufmgr = bo->bufmgr;
drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *)bo;
int index;
 
@@ -434,38 +431,38 @@ drm_bacon_add_validate_buffer2(drm_bacon_bo *bo)
return;
 
/* Extend the array of validation entries as necessary. */
-   if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
-   int new_size = bufmgr_gem->exec_size * 2;
+   if (bufmgr->exec_count == bufmgr->exec_size) {
+   int new_size = bufmgr->exec_size * 2;
 
if (new_size == 0)
new_size = 5;
 
-   bufmgr_gem->exec2_objects =
-   realloc(bufmgr_gem->exec2_objects,
-   sizeof(*bufmgr_gem->exec2_objects) * new_size);
-   bufmgr_gem->exec_bos =
-   realloc(bufmgr_gem->exec_bos,
-   sizeof(*bufmgr_gem->exec_bos) * new_size);
-   bufmgr_gem->exec_size = new_size;
+   bufmgr->exec2_objects =
+   

[Mesa-dev] [PATCH 31/53] i965/drm: Switch from uthash to Mesa's hash table.

[Kenneth Graunke]

No performance data has been gathered about this choice.  I just don't
want that many hash tables.
---
 src/mesa/drivers/dri/i965/Makefile.sources   |3 +-
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c |   79 +-
 src/mesa/drivers/dri/i965/uthash.h   | 1074 --
 3 files changed, 53 insertions(+), 1103 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/uthash.h

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 9b550dc17cc..6cab4eb5f43 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -160,8 +160,7 @@ i965_FILES = \
intel_tiled_memcpy.c \
intel_tiled_memcpy.h \
intel_upload.c \
-   libdrm_macros.h \
-   uthash.h
+   libdrm_macros.h
 
 i965_gen6_FILES = \
genX_blorp_exec.c
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 499cd19808f..98f2e131377 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -61,12 +61,12 @@
 #include "libdrm_macros.h"
 #include "main/macros.h"
 #include "util/macros.h"
+#include "util/hash_table.h"
 #include "util/list.h"
 #include "brw_bufmgr.h"
 #include "string.h"
 
 #include "i915_drm.h"
-#include "uthash.h"
 
 #ifdef HAVE_VALGRIND
 #include 
@@ -139,8 +139,8 @@ typedef struct _drm_bacon_bufmgr {
 
struct list_head managers;
 
-   drm_bacon_bo_gem *name_table;
-   drm_bacon_bo_gem *handle_table;
+   struct hash_table *name_table;
+   struct hash_table *handle_table;
 
struct list_head vma_cache;
int vma_count, vma_open, vma_max;
@@ -169,9 +169,6 @@ struct _drm_bacon_bo_gem {
 */
unsigned int global_name;
 
-   UT_hash_handle handle_hh;
-   UT_hash_handle name_hh;
-
/**
 * Index of the buffer within the validation list while preparing a
 * batchbuffer execution.
@@ -272,6 +269,25 @@ static inline drm_bacon_bo_gem *to_bo_gem(drm_bacon_bo *bo)
 return (drm_bacon_bo_gem *)bo;
 }
 
+static uint32_t
+key_hash_uint(const void *key)
+{
+   return _mesa_hash_data(key, 4);
+}
+
+static bool
+key_uint_equal(const void *a, const void *b)
+{
+   return *((unsigned *) a) == *((unsigned *) b);
+}
+
+static drm_bacon_bo_gem *
+hash_find_bo(struct hash_table *ht, unsigned int key)
+{
+   struct hash_entry *entry = _mesa_hash_table_search(ht, );
+   return entry ? (drm_bacon_bo_gem *) entry->data : NULL;
+}
+
 static unsigned long
 drm_bacon_gem_bo_tile_size(drm_bacon_bufmgr *bufmgr, unsigned long size,
   uint32_t *tiling_mode)
@@ -635,9 +651,8 @@ retry:
}
 
bo_gem->gem_handle = create.handle;
-   HASH_ADD(handle_hh, bufmgr->handle_table,
-gem_handle, sizeof(bo_gem->gem_handle),
-bo_gem);
+   _mesa_hash_table_insert(bufmgr->handle_table,
+   _gem->gem_handle, bo_gem);
 
bo_gem->bo.handle = bo_gem->gem_handle;
bo_gem->bo.bufmgr = bufmgr;
@@ -767,8 +782,7 @@ drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr *bufmgr,
 * provides a sufficiently fast match.
 */
pthread_mutex_lock(>lock);
-   HASH_FIND(name_hh, bufmgr->name_table,
- , sizeof(handle), bo_gem);
+   bo_gem = hash_find_bo(bufmgr->name_table, handle);
if (bo_gem) {
drm_bacon_bo_reference(_gem->bo);
goto out;
@@ -789,8 +803,7 @@ drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr *bufmgr,
  * object from the kernel before by looking through the list
  * again for a matching gem_handle
  */
-   HASH_FIND(handle_hh, bufmgr->handle_table,
- _arg.handle, sizeof(open_arg.handle), bo_gem);
+   bo_gem = hash_find_bo(bufmgr->handle_table, open_arg.handle);
if (bo_gem) {
drm_bacon_bo_reference(_gem->bo);
goto out;
@@ -814,10 +827,10 @@ drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr 
*bufmgr,
bo_gem->global_name = handle;
bo_gem->reusable = false;
 
-   HASH_ADD(handle_hh, bufmgr->handle_table,
-gem_handle, sizeof(bo_gem->gem_handle), bo_gem);
-   HASH_ADD(name_hh, bufmgr->name_table,
-global_name, sizeof(bo_gem->global_name), bo_gem);
+   _mesa_hash_table_insert(bufmgr->handle_table,
+   _gem->gem_handle, bo_gem);
+   _mesa_hash_table_insert(bufmgr->name_table,
+   _gem->global_name, bo_gem);
 
memclear(get_tiling);
get_tiling.handle = bo_gem->gem_handle;
@@ -849,6 +862,7 @@ drm_bacon_gem_bo_free(drm_bacon_bo *bo)
drm_bacon_bufmgr *bufmgr = bo->bufmgr;
drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
   

[Mesa-dev] [PATCH 33/53] i965/drm: Drop code to search for an existing bufmgr.

[Kenneth Graunke]

This functionality was added by libdrm commit
743af59669386cb6e063fa4bd85f0a0b2da86295 (intel: make bufmgr_gem
shareable from different API) in an attempt to solve libva/mesa buffer
sharing problems.  Specifically, this was working around an issue hit
by Chromium, which used the same drm_fd for multiple APIs, and shared
buffers between them.

This code attempted to work around that issue by using the same bufmgr
for both libva and Mesa.  It worked because libdrm_intel was loaded by
both libraries.  However, now that Mesa has forked, we don't have a
common library, and this code cannot work.

The correct solution is to have each API open its own file descriptor
(and get a corresponding buffer manager), and then use PRIME export
and import to share BOs across those APIs.  Then the kernel can manage
those shared resources.  According to Chris, the kernel will pass back
the same handle for a prime FD if the lookup is from the same device FD.

We believe Chromium has since moved to this model.

In Mesa, there is already only one screen per FD, and so there will
only be one bufmgr per FD.  We don't need any of this code.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 57 ++--
 1 file changed, 4 insertions(+), 53 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index eb6a5e742b1..466d9776130 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -119,8 +119,6 @@ struct drm_bacon_gem_bo_bucket {
 };
 
 typedef struct _drm_bacon_bufmgr {
-   int refcount;
-
int fd;
 
int max_relocs;
@@ -137,8 +135,6 @@ typedef struct _drm_bacon_bufmgr {
int num_buckets;
time_t time;
 
-   struct list_head managers;
-
struct hash_table *name_table;
struct hash_table *handle_table;
 
@@ -1514,8 +1510,8 @@ drm_bacon_gem_bo_start_gtt_access(drm_bacon_bo *bo, int 
write_enable)
}
 }
 
-static void
-drm_bacon_bufmgr_gem_destroy(drm_bacon_bufmgr *bufmgr)
+void
+drm_bacon_bufmgr_destroy(drm_bacon_bufmgr *bufmgr)
 {
free(bufmgr->exec2_objects);
free(bufmgr->exec_bos);
@@ -2369,38 +2365,6 @@ drm_bacon_reg_read(drm_bacon_bufmgr *bufmgr,
return ret;
 }
 
-static pthread_mutex_t bufmgr_list_mutex = PTHREAD_MUTEX_INITIALIZER;
-static struct list_head bufmgr_list = { _list, _list };
-
-static drm_bacon_bufmgr *
-drm_bacon_bufmgr_gem_find(int fd)
-{
-   list_for_each_entry(drm_bacon_bufmgr,
-bufmgr, _list, managers) {
-   if (bufmgr->fd == fd) {
-   p_atomic_inc(>refcount);
-   return bufmgr;
-   }
-   }
-
-   return NULL;
-}
-
-void
-drm_bacon_bufmgr_destroy(drm_bacon_bufmgr *bufmgr)
-{
-   if (atomic_add_unless(>refcount, -1, 1)) {
-   pthread_mutex_lock(_list_mutex);
-
-   if (p_atomic_dec_zero(>refcount)) {
-   list_del(>managers);
-   drm_bacon_bufmgr_gem_destroy(bufmgr);
-   }
-
-   pthread_mutex_unlock(_list_mutex);
-   }
-}
-
 void *drm_bacon_gem_bo_map__gtt(drm_bacon_bo *bo)
 {
drm_bacon_bufmgr *bufmgr = bo->bufmgr;
@@ -2538,23 +2502,15 @@ drm_bacon_bufmgr_gem_init(struct gen_device_info 
*devinfo,
drm_bacon_bufmgr *bufmgr;
struct drm_i915_gem_get_aperture aperture;
 
-   pthread_mutex_lock(_list_mutex);
-
-   bufmgr = drm_bacon_bufmgr_gem_find(fd);
-   if (bufmgr)
-   goto exit;
-
bufmgr = calloc(1, sizeof(*bufmgr));
if (bufmgr == NULL)
-   goto exit;
+   return NULL;
 
bufmgr->fd = fd;
-   p_atomic_set(>refcount, 1);
 
if (pthread_mutex_init(>lock, NULL) != 0) {
free(bufmgr);
-   bufmgr = NULL;
-   goto exit;
+   return NULL;
}
 
memclear(aperture);
@@ -2576,15 +2532,10 @@ drm_bacon_bufmgr_gem_init(struct gen_device_info 
*devinfo,
list_inithead(>vma_cache);
bufmgr->vma_max = -1; /* unlimited by default */
 
-   list_add(>managers, _list);
-
bufmgr->name_table =
_mesa_hash_table_create(NULL, key_hash_uint, key_uint_equal);
bufmgr->handle_table =
_mesa_hash_table_create(NULL, key_hash_uint, key_uint_equal);
 
-exit:
-   pthread_mutex_unlock(_list_mutex);
-
return bufmgr;
 }
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 23/53] i965/drm: Drop has_wait_timeout.

[Kenneth Graunke]

We require Kernel 3.6 and fail screen creation if this doesn't exist.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 16 
 1 file changed, 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 339e2034b06..8f9fbdf74be 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -151,7 +151,6 @@ typedef struct _drm_bacon_bufmgr {
unsigned int has_bsd : 1;
unsigned int has_blt : 1;
unsigned int has_llc : 1;
-   unsigned int has_wait_timeout : 1;
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
unsigned int has_vebox : 1;
@@ -1663,17 +1662,6 @@ drm_bacon_gem_bo_wait(drm_bacon_bo *bo, int64_t 
timeout_ns)
struct drm_i915_gem_wait wait;
int ret;
 
-   if (!bufmgr->has_wait_timeout) {
-   DBG("%s:%d: Timed wait is not supported. Falling back to "
-   "infinite wait\n", __FILE__, __LINE__);
-   if (timeout_ns) {
-   drm_bacon_bo_wait_rendering(bo);
-   return 0;
-   } else {
-   return drm_bacon_bo_busy(bo) ? -ETIME : 0;
-   }
-   }
-
memclear(wait);
wait.bo_handle = bo_gem->gem_handle;
wait.timeout_ns = timeout_ns;
@@ -3062,10 +3050,6 @@ drm_bacon_bufmgr_gem_init(int fd, int batch_size)
ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, );
bufmgr->has_exec_async = ret == 0;
 
-   gp.param = I915_PARAM_HAS_WAIT_TIMEOUT;
-   ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, );
-   bufmgr->has_wait_timeout = ret == 0;
-
gp.param = I915_PARAM_HAS_LLC;
ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, );
if (ret != 0) {
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 26/53] i965/drm: Delete engine checks.

[Kenneth Graunke]

This is basically handholding to prevent a bogus caller from trying to
execbuffer on a bogus engine.  i965 already does this correctly.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 35 
 1 file changed, 35 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 7c8598c1fde..4362b51b04e 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -146,12 +146,9 @@ typedef struct _drm_bacon_bufmgr {
int vma_count, vma_open, vma_max;
 
uint64_t gtt_size;
-   unsigned int has_bsd : 1;
-   unsigned int has_blt : 1;
unsigned int has_llc : 1;
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
-   unsigned int has_vebox : 1;
unsigned int has_exec_async : 1;
 
struct {
@@ -1987,26 +1984,6 @@ do_exec2(drm_bacon_bo *bo, int used, drm_bacon_context 
*ctx,
if (to_bo_gem(bo)->has_error)
return -ENOMEM;
 
-   switch (flags & 0x7) {
-   default:
-   return -EINVAL;
-   case I915_EXEC_BLT:
-   if (!bufmgr->has_blt)
-   return -EINVAL;
-   break;
-   case I915_EXEC_BSD:
-   if (!bufmgr->has_bsd)
-   return -EINVAL;
-   break;
-   case I915_EXEC_VEBOX:
-   if (!bufmgr->has_vebox)
-   return -EINVAL;
-   break;
-   case I915_EXEC_RENDER:
-   case I915_EXEC_DEFAULT:
-   break;
-   }
-
pthread_mutex_lock(>lock);
/* Update indices and set up the validate list. */
drm_bacon_gem_bo_process_reloc2(bo);
@@ -2949,24 +2926,12 @@ drm_bacon_bufmgr_gem_init(struct gen_device_info 
*devinfo,
memclear(gp);
gp.value = 
 
-   gp.param = I915_PARAM_HAS_BSD;
-   ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, );
-   bufmgr->has_bsd = ret == 0;
-
-   gp.param = I915_PARAM_HAS_BLT;
-   ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, );
-   bufmgr->has_blt = ret == 0;
-
gp.param = I915_PARAM_HAS_EXEC_ASYNC;
ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, );
bufmgr->has_exec_async = ret == 0;
 
bufmgr->has_llc = devinfo->has_llc;
 
-   gp.param = I915_PARAM_HAS_VEBOX;
-   ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, );
-   bufmgr->has_vebox = (ret == 0) & (*gp.value > 0);
-
/* Let's go with one relocation per every 2 dwords (but round down a bit
 * since a power of two will mean an extra page allocation for the reloc
 * buffer).
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 29/53] i965/drm: Drop has_exec_async related API.

[Kenneth Graunke]

Mesa doesn't use this yet.  We'll almost certainly want to, but we can
add the functionality back after we clean up the messy drm code.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  5 ---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 61 
 2 files changed, 66 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 96e8571859c..237f39bb078 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -286,11 +286,6 @@ void 
drm_bacon_bufmgr_gem_set_vma_cache_size(drm_bacon_bufmgr *bufmgr,
 int drm_bacon_gem_bo_map_unsynchronized(drm_bacon_bo *bo);
 int drm_bacon_gem_bo_map_gtt(drm_bacon_bo *bo);
 
-#define HAVE_DRM_INTEL_GEM_BO_DISABLE_IMPLICIT_SYNC 1
-int drm_bacon_bufmgr_gem_can_disable_implicit_sync(drm_bacon_bufmgr *bufmgr);
-void drm_bacon_gem_bo_disable_implicit_sync(drm_bacon_bo *bo);
-void drm_bacon_gem_bo_enable_implicit_sync(drm_bacon_bo *bo);
-
 void *drm_bacon_gem_bo_map__cpu(drm_bacon_bo *bo);
 void *drm_bacon_gem_bo_map__gtt(drm_bacon_bo *bo);
 void *drm_bacon_gem_bo_map__wc(drm_bacon_bo *bo);
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index aa718d714c5..fb02b1258eb 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -149,7 +149,6 @@ typedef struct _drm_bacon_bufmgr {
unsigned int has_llc : 1;
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
-   unsigned int has_exec_async : 1;
 } drm_bacon_bufmgr;
 
 typedef struct _drm_bacon_reloc_target_info {
@@ -2017,57 +2016,6 @@ drm_bacon_bufmgr_gem_enable_reuse(drm_bacon_bufmgr 
*bufmgr)
 }
 
 /**
- * Disables implicit synchronisation before executing the bo
- *
- * This will cause rendering corruption unless you correctly manage explicit
- * fences for all rendering involving this buffer - including use by others.
- * Disabling the implicit serialisation is only required if that serialisation
- * is too coarse (for example, you have split the buffer into many
- * non-overlapping regions and are sharing the whole buffer between concurrent
- * independent command streams).
- *
- * Note the kernel must advertise support via I915_PARAM_HAS_EXEC_ASYNC,
- * which can be checked using drm_bacon_bufmgr_can_disable_implicit_sync,
- * or subsequent execbufs involving the bo will generate EINVAL.
- */
-void
-drm_bacon_gem_bo_disable_implicit_sync(drm_bacon_bo *bo)
-{
-   drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
-
-   bo_gem->kflags |= EXEC_OBJECT_ASYNC;
-}
-
-/**
- * Enables implicit synchronisation before executing the bo
- *
- * This is the default behaviour of the kernel, to wait upon prior writes
- * completing on the object before rendering with it, or to wait for prior
- * reads to complete before writing into the object.
- * drm_bacon_gem_bo_disable_implicit_sync() can stop this behaviour, telling
- * the kernel never to insert a stall before using the object. Then this
- * function can be used to restore the implicit sync before subsequent
- * rendering.
- */
-void
-drm_bacon_gem_bo_enable_implicit_sync(drm_bacon_bo *bo)
-{
-   drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
-
-   bo_gem->kflags &= ~EXEC_OBJECT_ASYNC;
-}
-
-/**
- * Query whether the kernel supports disabling of its implicit synchronisation
- * before execbuf. See drm_bacon_gem_bo_disable_implicit_sync()
- */
-int
-drm_bacon_bufmgr_gem_can_disable_implicit_sync(drm_bacon_bufmgr *bufmgr)
-{
-   return bufmgr->has_exec_async;
-}
-
-/**
  * Return the additional aperture space required by the tree of buffer objects
  * rooted at bo.
  */
@@ -2579,8 +2527,6 @@ drm_bacon_bufmgr_gem_init(struct gen_device_info *devinfo,
 {
drm_bacon_bufmgr *bufmgr;
struct drm_i915_gem_get_aperture aperture;
-   drm_i915_getparam_t gp;
-   int ret, tmp;
 
pthread_mutex_lock(_list_mutex);
 
@@ -2605,13 +2551,6 @@ drm_bacon_bufmgr_gem_init(struct gen_device_info 
*devinfo,
drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, );
bufmgr->gtt_size = aperture.aper_available_size;
 
-   memclear(gp);
-   gp.value = 
-
-   gp.param = I915_PARAM_HAS_EXEC_ASYNC;
-   ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GETPARAM, );
-   bufmgr->has_exec_async = ret == 0;
-
bufmgr->has_llc = devinfo->has_llc;
 
/* Let's go with one relocation per every 2 dwords (but round down a bit
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 27/53] i965/drm: Drop userptr support for now.

[Kenneth Graunke]

We'll probably want this someday, but let's simplify now and add it back
when we actually intend to use it.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  13 --
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 192 +--
 2 files changed, 1 insertion(+), 204 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 11c02604f12..487abe162b3 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -112,19 +112,6 @@ drm_bacon_bo 
*drm_bacon_bo_alloc_for_render(drm_bacon_bufmgr *bufmgr,
unsigned long size,
unsigned int alignment);
 
-bool drm_bacon_has_userptr(drm_bacon_bufmgr *bufmgr);
-
-/**
- * Allocate a buffer object from an existing user accessible
- * address malloc'd with the provided size.
- * Alignment is used when mapping to the gtt.
- * Flags may be I915_VMAP_READ_ONLY or I915_USERPTR_UNSYNCHRONIZED
- */
-drm_bacon_bo *drm_bacon_bo_alloc_userptr(drm_bacon_bufmgr *bufmgr,
-   const char *name,
-   void *addr, uint32_t tiling_mode,
-   uint32_t stride, unsigned long size,
-   unsigned long flags);
 /**
  * Allocate a tiled buffer object.
  *
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 4362b51b04e..e5de94b36f0 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -150,12 +150,6 @@ typedef struct _drm_bacon_bufmgr {
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
unsigned int has_exec_async : 1;
-
-   struct {
-   void *ptr;
-   uint32_t handle;
-   } userptr_active;
-
 } drm_bacon_bufmgr;
 
 typedef struct _drm_bacon_reloc_target_info {
@@ -217,11 +211,6 @@ struct _drm_bacon_bo_gem {
void *gtt_virtual;
/** WC CPU address for the buffer, saved across map/unmap cycles */
void *wc_virtual;
-   /**
-* Virtual address of the buffer allocated by user, used for userptr
-* objects only.
-*/
-   void *user_virtual;
int map_count;
struct list_head vma_list;
 
@@ -261,11 +250,6 @@ struct _drm_bacon_bo_gem {
bool idle;
 
/**
-* Boolean of whether this buffer was allocated with userptr
-*/
-   bool is_userptr;
-
-   /**
 * Size in bytes of this buffer and its relocation descendents.
 *
 * Used to avoid costly tree walking in
@@ -788,130 +772,6 @@ drm_bacon_bo_alloc_tiled(drm_bacon_bufmgr *bufmgr, const 
char *name,
   tiling, stride, 0);
 }
 
-drm_bacon_bo *
-drm_bacon_bo_alloc_userptr(drm_bacon_bufmgr *bufmgr,
-  const char *name,
-  void *addr,
-  uint32_t tiling_mode,
-  uint32_t stride,
-  unsigned long size,
-  unsigned long flags)
-{
-   drm_bacon_bo_gem *bo_gem;
-   int ret;
-   struct drm_i915_gem_userptr userptr;
-
-   /* Tiling with userptr surfaces is not supported
-* on all hardware so refuse it for time being.
-*/
-   if (tiling_mode != I915_TILING_NONE)
-   return NULL;
-
-   bo_gem = calloc(1, sizeof(*bo_gem));
-   if (!bo_gem)
-   return NULL;
-
-   p_atomic_set(_gem->refcount, 1);
-   list_inithead(_gem->vma_list);
-
-   bo_gem->bo.size = size;
-
-   memclear(userptr);
-   userptr.user_ptr = (__u64)((unsigned long)addr);
-   userptr.user_size = size;
-   userptr.flags = flags;
-
-   ret = drmIoctl(bufmgr->fd,
-   DRM_IOCTL_I915_GEM_USERPTR,
-   );
-   if (ret != 0) {
-   DBG("bo_create_userptr: "
-   "ioctl failed with user ptr %p size 0x%lx, "
-   "user flags 0x%lx\n", addr, size, flags);
-   free(bo_gem);
-   return NULL;
-   }
-
-   pthread_mutex_lock(>lock);
-
-   bo_gem->gem_handle = userptr.handle;
-   bo_gem->bo.handle = bo_gem->gem_handle;
-   bo_gem->bo.bufmgr= bufmgr;
-   bo_gem->is_userptr   = true;
-   bo_gem->bo.virtual   = addr;
-   /* Save the address provided by user */
-   bo_gem->user_virtual = addr;
-   bo_gem->tiling_mode  = I915_TILING_NONE;
-   bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
-   bo_gem->stride   = 0;
-
-   HASH_ADD(handle_hh, bufmgr->handle_table,
-gem_handle, sizeof(bo_gem->gem_handle),
-bo_gem);
-
-   bo_gem->name = name;
-   bo_gem->validate_index = -1;
-   bo_gem->used_as_reloc_target = false;

[Mesa-dev] [PATCH 25/53] i965/drm: Drop intel_chipset.h in favor of using gen_device_info.

[Kenneth Graunke]

This moves the PCI ID detection to intel_screen.c and makes
drm_bacon_bufmgr_gem_init() take a devinfo pointer.

We also drop the HAS_LLC query stuff - devinfo has that info already,
without kernel queries, and it makes no sense to have two has_llc flags
set by different mechanisms.
---
 src/mesa/drivers/dri/i965/Makefile.sources   |   1 -
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |   6 +-
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 103 +-
 src/mesa/drivers/dri/i965/intel_chipset.h| 469 ---
 src/mesa/drivers/dri/i965/intel_screen.c |  60 +++-
 5 files changed, 63 insertions(+), 576 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/intel_chipset.h

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 9068bcdde7a..9b550dc17cc 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -132,7 +132,6 @@ i965_FILES = \
intel_buffers.c \
intel_buffers.h \
intel_bufmgr_gem.c \
-   intel_chipset.h \
intel_copy_image.c \
intel_extensions.c \
intel_fbo.c \
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 1e47f75b4a5..11c02604f12 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -42,6 +42,8 @@
 extern "C" {
 #endif
 
+struct gen_device_info;
+
 typedef struct _drm_bacon_bufmgr drm_bacon_bufmgr;
 typedef struct _drm_bacon_context drm_bacon_context;
 typedef struct _drm_bacon_bo drm_bacon_bo;
@@ -293,7 +295,8 @@ int drm_bacon_bo_is_reusable(drm_bacon_bo *bo);
 int drm_bacon_bo_references(drm_bacon_bo *bo, drm_bacon_bo *target_bo);
 
 /* drm_bacon_bufmgr_gem.c */
-drm_bacon_bufmgr *drm_bacon_bufmgr_gem_init(int fd, int batch_size);
+drm_bacon_bufmgr *drm_bacon_bufmgr_gem_init(struct gen_device_info *devinfo,
+   int fd, int batch_size);
 drm_bacon_bo *drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr *bufmgr,
const char *name,
unsigned int handle);
@@ -316,7 +319,6 @@ int drm_bacon_gem_bo_get_reloc_count(drm_bacon_bo *bo);
 void drm_bacon_gem_bo_clear_relocs(drm_bacon_bo *bo, int start);
 void drm_bacon_gem_bo_start_gtt_access(drm_bacon_bo *bo, int write_enable);
 
-int drm_bacon_bufmgr_gem_get_devid(drm_bacon_bufmgr *bufmgr);
 int drm_bacon_gem_bo_wait(drm_bacon_bo *bo, int64_t timeout_ns);
 
 drm_bacon_context *drm_bacon_gem_context_create(drm_bacon_bufmgr *bufmgr);
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 40ad89f87a1..7c8598c1fde 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -57,12 +57,12 @@
 #define ETIME ETIMEDOUT
 #endif
 #include "common/gen_debug.h"
+#include "common/gen_device_info.h"
 #include "libdrm_macros.h"
 #include "main/macros.h"
 #include "util/macros.h"
 #include "util/list.h"
 #include "brw_bufmgr.h"
-#include "intel_chipset.h"
 #include "string.h"
 
 #include "i915_drm.h"
@@ -146,8 +146,6 @@ typedef struct _drm_bacon_bufmgr {
int vma_count, vma_open, vma_max;
 
uint64_t gtt_size;
-   int pci_device;
-   int gen;
unsigned int has_bsd : 1;
unsigned int has_blt : 1;
unsigned int has_llc : 1;
@@ -2636,71 +2634,6 @@ drm_bacon_bufmgr_gem_set_vma_cache_size(drm_bacon_bufmgr 
*bufmgr, int limit)
drm_bacon_gem_bo_purge_vma_cache(bufmgr);
 }
 
-static int
-parse_devid_override(const char *devid_override)
-{
-   static const struct {
-   const char *name;
-   int pci_id;
-   } name_map[] = {
-   { "brw", PCI_CHIP_I965_GM },
-   { "g4x", PCI_CHIP_GM45_GM },
-   { "ilk", PCI_CHIP_ILD_G },
-   { "snb", PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS },
-   { "ivb", PCI_CHIP_IVYBRIDGE_S_GT2 },
-   { "hsw", PCI_CHIP_HASWELL_CRW_E_GT3 },
-   { "byt", PCI_CHIP_VALLEYVIEW_3 },
-   { "bdw", 0x1620 | BDW_ULX },
-   { "skl", PCI_CHIP_SKYLAKE_DT_GT2 },
-   { "kbl", PCI_CHIP_KABYLAKE_DT_GT2 },
-   };
-   unsigned int i;
-
-   for (i = 0; i < ARRAY_SIZE(name_map); i++) {
-   if (!strcmp(name_map[i].name, devid_override))
-   return name_map[i].pci_id;
-   }
-
-   return strtod(devid_override, NULL);
-}
-
-/**
- * Get the PCI ID for the device.  This can be overridden by setting the
- * INTEL_DEVID_OVERRIDE environment variable to the desired ID.
- */
-static int
-get_pci_device_id(drm_bacon_bufmgr *bufmgr)
-{
-   char *devid_override;
-   int devid = 0;
-   int ret;
-   drm_i915_getparam_t gp;
-
-   if (geteuid() == getuid()) {
-   devid_override = getenv("INTEL_DEVID_OVERRIDE");

[Mesa-dev] [PATCH 24/53] i965/drm: Drop deprecated drm_bacon_bo::offset.

[Kenneth Graunke]

This field was the wrong size, so we replaced it with offset64.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   | 6 --
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 3 ---
 src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
 3 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 84e29fbc168..1e47f75b4a5 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -63,12 +63,6 @@ struct _drm_bacon_bo {
unsigned long align;
 
/**
-* Deprecated field containing (possibly the low 32-bits of) the last
-* seen virtual card address.  Use offset64 instead.
-*/
-   unsigned long offset;
-
-   /**
 * Virtual address for accessing the buffer data.  Only valid while
 * mapped.
 */
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 8f9fbdf74be..40ad89f87a1 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -977,7 +977,6 @@ drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr *bufmgr,
list_inithead(_gem->vma_list);
 
bo_gem->bo.size = open_arg.size;
-   bo_gem->bo.offset = 0;
bo_gem->bo.offset64 = 0;
bo_gem->bo.virtual = NULL;
bo_gem->bo.bufmgr = bufmgr;
@@ -1973,7 +1972,6 @@ drm_bacon_update_buffer_offsets2 (drm_bacon_bufmgr 
*bufmgr)
upper_32_bits(bufmgr->exec2_objects[i].offset),
lower_32_bits(bufmgr->exec2_objects[i].offset));
bo->offset64 = bufmgr->exec2_objects[i].offset;
-   bo->offset = bufmgr->exec2_objects[i].offset;
}
}
 }
@@ -2199,7 +2197,6 @@ drm_bacon_bo_set_softpin_offset(drm_bacon_bo *bo, 
uint64_t offset)
drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
 
bo->offset64 = offset;
-   bo->offset = offset;
bo_gem->kflags |= EXEC_OBJECT_PINNED;
 
return 0;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 3801dc60397..9de2ec0cefd 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1398,7 +1398,7 @@ intel_detect_pipelined_register(struct intel_screen 
*screen,
results, offset*sizeof(uint32_t),
I915_GEM_DOMAIN_INSTRUCTION,
I915_GEM_DOMAIN_INSTRUCTION);
-   *batch++ = results->offset + offset*sizeof(uint32_t);
+   *batch++ = ((uint32_t) results->offset64) + offset*sizeof(uint32_t);
 
/* And afterwards clear the register */
if (reset) {
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 19/53] i965/drm: Drop cliprects and dr4 from execbuf variants.

[Kenneth Graunke]

Legacy DRI1 leftovers.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h|  9 ++---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c |  2 +-
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 25 +
 src/mesa/drivers/dri/i965/intel_screen.c  |  1 -
 4 files changed, 12 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 7418b14de0e..84e29fbc168 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -42,8 +42,6 @@
 extern "C" {
 #endif
 
-struct drm_clip_rect;
-
 typedef struct _drm_bacon_bufmgr drm_bacon_bufmgr;
 typedef struct _drm_bacon_context drm_bacon_context;
 typedef struct _drm_bacon_bo drm_bacon_bo;
@@ -198,13 +196,10 @@ void drm_bacon_bo_wait_rendering(drm_bacon_bo *bo);
 void drm_bacon_bufmgr_destroy(drm_bacon_bufmgr *bufmgr);
 
 /** Executes the command buffer pointed to by bo. */
-int drm_bacon_bo_exec(drm_bacon_bo *bo, int used,
- struct drm_clip_rect *cliprects, int num_cliprects, int 
DR4);
+int drm_bacon_bo_exec(drm_bacon_bo *bo, int used);
 
 /** Executes the command buffer pointed to by bo on the selected ring buffer */
-int drm_bacon_bo_mrb_exec(drm_bacon_bo *bo, int used,
-   struct drm_clip_rect *cliprects, int num_cliprects, int 
DR4,
-   unsigned int flags);
+int drm_bacon_bo_mrb_exec(drm_bacon_bo *bo, int used, unsigned int flags);
 int drm_bacon_bufmgr_check_aperture_space(drm_bacon_bo ** bo_array, int count);
 
 /**
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index b1104286578..c35d9ca5bda 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -488,7 +488,7 @@ do_flush_locked(struct brw_context *brw, int in_fence_fd, 
int *out_fence_fd)
 assert(in_fence_fd == -1);
 assert(out_fence_fd == NULL);
 ret = drm_bacon_bo_mrb_exec(batch->bo, 4 * USED_BATCH(*batch),
-NULL, 0, 0, flags);
+flags);
 } else {
ret = drm_bacon_gem_bo_fence_exec(batch->bo, brw->hw_ctx,
 4 * USED_BATCH(*batch),
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 964bdf19dc8..be587ca9282 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -2000,7 +2000,6 @@ drm_bacon_update_buffer_offsets2 (drm_bacon_bufmgr_gem 
*bufmgr_gem)
 
 static int
 do_exec2(drm_bacon_bo *bo, int used, drm_bacon_context *ctx,
-drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
 int in_fence, int *out_fence,
 unsigned int flags)
 {
@@ -2046,10 +2045,10 @@ do_exec2(drm_bacon_bo *bo, int used, drm_bacon_context 
*ctx,
execbuf.buffer_count = bufmgr_gem->exec_count;
execbuf.batch_start_offset = 0;
execbuf.batch_len = used;
-   execbuf.cliprects_ptr = (uintptr_t)cliprects;
-   execbuf.num_cliprects = num_cliprects;
+   execbuf.cliprects_ptr = 0;
+   execbuf.num_cliprects = 0;
execbuf.DR1 = 0;
-   execbuf.DR4 = DR4;
+   execbuf.DR4 = 0;
execbuf.flags = flags;
if (ctx == NULL)
i915_execbuffer2_set_context_id(execbuf, 0);
@@ -2108,28 +2107,22 @@ skip_execution:
 }
 
 int
-drm_bacon_bo_exec(drm_bacon_bo *bo, int used,
- drm_clip_rect_t *cliprects, int num_cliprects,
- int DR4)
+drm_bacon_bo_exec(drm_bacon_bo *bo, int used)
 {
-   return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
-   -1, NULL, I915_EXEC_RENDER);
+   return do_exec2(bo, used, NULL, -1, NULL, I915_EXEC_RENDER);
 }
 
 int
-drm_bacon_bo_mrb_exec(drm_bacon_bo *bo, int used,
- drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
- unsigned int flags)
+drm_bacon_bo_mrb_exec(drm_bacon_bo *bo, int used, unsigned int flags)
 {
-   return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4,
-   -1, NULL, flags);
+   return do_exec2(bo, used, NULL, -1, NULL, flags);
 }
 
 int
 drm_bacon_gem_bo_context_exec(drm_bacon_bo *bo, drm_bacon_context *ctx,
  int used, unsigned int flags)
 {
-   return do_exec2(bo, used, ctx, NULL, 0, 0, -1, NULL, flags);
+   return do_exec2(bo, used, ctx, -1, NULL, flags);
 }
 
 int
@@ -2140,7 +2133,7 @@ drm_bacon_gem_bo_fence_exec(drm_bacon_bo *bo,
int *out_fence,
unsigned int flags)
 {
-   return do_exec2(bo, used, ctx, NULL, 0, 0, in_fence, out_fence, flags);
+   return do_exec2(bo, used, ctx, in_fence, out_fence, flags);
 }
 
 static int
diff --git 

[Mesa-dev] [PATCH 17/53] i965/drm: Check INTEL_DEBUG & DEBUG_BUFMGR directly.

[Kenneth Graunke]

Eliminates some API around this, and more importantly, the last
field in one bufmgr class.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h| 1 -
 src/mesa/drivers/dri/i965/intel_bufmgr.c  | 6 --
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 9 +++--
 src/mesa/drivers/dri/i965/intel_bufmgr_priv.h | 3 ---
 src/mesa/drivers/dri/i965/intel_screen.c  | 3 ---
 5 files changed, 3 insertions(+), 19 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index a9cf0ff85f2..2cc636c7149 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -126,7 +126,6 @@ int drm_bacon_bo_get_subdata(drm_bacon_bo *bo, unsigned 
long offset,
 unsigned long size, void *data);
 void drm_bacon_bo_wait_rendering(drm_bacon_bo *bo);
 
-void drm_bacon_bufmgr_set_debug(drm_bacon_bufmgr *bufmgr, int enable_debug);
 void drm_bacon_bufmgr_destroy(drm_bacon_bufmgr *bufmgr);
 int drm_bacon_bo_exec(drm_bacon_bo *bo, int used,
  struct drm_clip_rect *cliprects, int num_cliprects, int 
DR4);
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr.c
index a8e8ae7da65..a87286c971a 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr.c
@@ -175,12 +175,6 @@ drm_bacon_bo_mrb_exec(drm_bacon_bo *bo, int used,
}
 }
 
-void
-drm_bacon_bufmgr_set_debug(drm_bacon_bufmgr *bufmgr, int enable_debug)
-{
-   bufmgr->debug = enable_debug;
-}
-
 int
 drm_bacon_bufmgr_check_aperture_space(drm_bacon_bo ** bo_array, int count)
 {
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index b981658e920..749326891a0 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -56,6 +56,7 @@
 #ifndef ETIME
 #define ETIME ETIMEDOUT
 #endif
+#include "common/gen_debug.h"
 #include "libdrm_macros.h"
 #include "main/macros.h"
 #include "util/macros.h"
@@ -78,10 +79,7 @@
 
 #define memclear(s) memset(, 0, sizeof(s))
 
-#define DBG(...) do {  \
-   if (bufmgr_gem->bufmgr.debug)   \
-   fprintf(stderr, __VA_ARGS__);   \
-} while (0)
+#define FILE_DEBUG_FLAG DEBUG_BUFMGR
 
 static inline int
 atomic_add_unless(int *v, int add, int unless)
@@ -2107,7 +2105,7 @@ do_exec2(drm_bacon_bo *bo, int used, drm_bacon_context 
*ctx,
*out_fence = execbuf.rsvd2 >> 32;
 
 skip_execution:
-   if (bufmgr_gem->bufmgr.debug)
+   if (INTEL_DEBUG & DEBUG_BUFMGR)
drm_bacon_gem_dump_validation_list(bufmgr_gem);
 
for (i = 0; i < bufmgr_gem->exec_count; i++) {
@@ -3180,7 +3178,6 @@ drm_bacon_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->bufmgr.bo_busy = drm_bacon_gem_bo_busy;
bufmgr_gem->bufmgr.bo_madvise = drm_bacon_gem_bo_madvise;
bufmgr_gem->bufmgr.destroy = drm_bacon_bufmgr_gem_unref;
-   bufmgr_gem->bufmgr.debug = 0;
bufmgr_gem->bufmgr.check_aperture_space =
drm_bacon_gem_check_aperture_space;
bufmgr_gem->bufmgr.bo_disable_reuse = drm_bacon_gem_bo_disable_reuse;
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h 
b/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h
index 26ffd18234a..6bc6c0b8e11 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h
@@ -275,9 +275,6 @@ struct _drm_bacon_bufmgr {
 
/** Returns true if target_bo is in the relocation tree rooted at bo. */
int (*bo_references) (drm_bacon_bo *bo, drm_bacon_bo *target_bo);
-
-   /**< Enables verbose debugging printouts */
-   int debug;
 };
 
 struct _drm_bacon_context {
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index fbe7301c9ba..7dfcb3b9106 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1770,9 +1770,6 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
 
brw_process_intel_debug_variable();
 
-   if (INTEL_DEBUG & DEBUG_BUFMGR)
-  drm_bacon_bufmgr_set_debug(screen->bufmgr, true);
-
if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && devinfo->gen < 7) {
   fprintf(stderr,
   "shader_time debugging requires gen7 (Ivybridge) or better.\n");
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 20/53] i965/drm: Move _drm_bacon_context to intel_bufmgr_gem.c.

[Kenneth Graunke]

This moves us one step closer to killing off intel_bufmgr_priv.h.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 5 +
 src/mesa/drivers/dri/i965/intel_bufmgr_priv.h | 5 -
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index be587ca9282..d0395e78307 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -107,6 +107,11 @@ atomic_add_unless(int *v, int add, int unless)
  */
 #define lower_32_bits(n) ((__u32)(n))
 
+struct _drm_bacon_context {
+   unsigned int ctx_id;
+   struct _drm_bacon_bufmgr *bufmgr;
+};
+
 typedef struct _drm_bacon_bo_gem drm_bacon_bo_gem;
 
 struct drm_bacon_gem_bo_bucket {
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h 
b/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h
index 9f54606e5d1..cccb9e4a972 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h
@@ -42,9 +42,4 @@
 struct _drm_bacon_bufmgr {
 };
 
-struct _drm_bacon_context {
-   unsigned int ctx_id;
-   struct _drm_bacon_bufmgr *bufmgr;
-};
-
 #endif /* INTEL_BUFMGR_PRIV_H */
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 18/53] i965/drm: Devirtualize the bufmgr.

[Kenneth Graunke]

libdrm_bacon used to have a GEM-based bufmgr and a legacy fake bufmgr,
but that's long since dead (and we never imported it to i965).  So,
drop the extra layer of function pointers.
---
 src/mesa/drivers/dri/i965/Makefile.sources|   1 -
 src/mesa/drivers/dri/i965/brw_bufmgr.h| 155 ++-
 src/mesa/drivers/dri/i965/intel_bufmgr.c  | 271 --
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 227 +
 src/mesa/drivers/dri/i965/intel_bufmgr_priv.h | 235 --
 5 files changed, 243 insertions(+), 646 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/intel_bufmgr.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 1d2c6e06f8b..3e73d0f9e2a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -131,7 +131,6 @@ i965_FILES = \
intel_buffer_objects.h \
intel_buffers.c \
intel_buffers.h \
-   intel_bufmgr.c \
intel_bufmgr_gem.c \
intel_bufmgr_priv.h \
intel_chipset.h \
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 2cc636c7149..7418b14de0e 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -34,7 +34,7 @@
 #ifndef INTEL_BUFMGR_H
 #define INTEL_BUFMGR_H
 
-#include 
+#include 
 #include 
 #include 
 
@@ -98,56 +98,209 @@ struct _drm_bacon_bo {
 
 #define BO_ALLOC_FOR_RENDER (1<<0)
 
+/**
+ * Allocate a buffer object.
+ *
+ * Buffer objects are not necessarily initially mapped into CPU virtual
+ * address space or graphics device aperture.  They must be mapped
+ * using bo_map() or drm_bacon_gem_bo_map_gtt() to be used by the CPU.
+ */
 drm_bacon_bo *drm_bacon_bo_alloc(drm_bacon_bufmgr *bufmgr, const char *name,
 unsigned long size, unsigned int alignment);
+/**
+ * Allocate a buffer object, hinting that it will be used as a
+ * render target.
+ *
+ * This is otherwise the same as bo_alloc.
+ */
 drm_bacon_bo *drm_bacon_bo_alloc_for_render(drm_bacon_bufmgr *bufmgr,
const char *name,
unsigned long size,
unsigned int alignment);
+
+bool drm_bacon_has_userptr(drm_bacon_bufmgr *bufmgr);
+
+/**
+ * Allocate a buffer object from an existing user accessible
+ * address malloc'd with the provided size.
+ * Alignment is used when mapping to the gtt.
+ * Flags may be I915_VMAP_READ_ONLY or I915_USERPTR_UNSYNCHRONIZED
+ */
 drm_bacon_bo *drm_bacon_bo_alloc_userptr(drm_bacon_bufmgr *bufmgr,
const char *name,
void *addr, uint32_t tiling_mode,
uint32_t stride, unsigned long size,
unsigned long flags);
+/**
+ * Allocate a tiled buffer object.
+ *
+ * Alignment for tiled objects is set automatically; the 'flags'
+ * argument provides a hint about how the object will be used initially.
+ *
+ * Valid tiling formats are:
+ *  I915_TILING_NONE
+ *  I915_TILING_X
+ *  I915_TILING_Y
+ *
+ * Note the tiling format may be rejected; callers should check the
+ * 'tiling_mode' field on return, as well as the pitch value, which
+ * may have been rounded up to accommodate for tiling restrictions.
+ */
 drm_bacon_bo *drm_bacon_bo_alloc_tiled(drm_bacon_bufmgr *bufmgr,
   const char *name,
   int x, int y, int cpp,
   uint32_t *tiling_mode,
   unsigned long *pitch,
   unsigned long flags);
+
+/** Takes a reference on a buffer object */
 void drm_bacon_bo_reference(drm_bacon_bo *bo);
+
+/**
+ * Releases a reference on a buffer object, freeing the data if
+ * no references remain.
+ */
 void drm_bacon_bo_unreference(drm_bacon_bo *bo);
+
+/**
+ * Maps the buffer into userspace.
+ *
+ * This function will block waiting for any existing execution on the
+ * buffer to complete, first.  The resulting mapping is available at
+ * buf->virtual.
+ */
 int drm_bacon_bo_map(drm_bacon_bo *bo, int write_enable);
+
+/**
+ * Reduces the refcount on the userspace mapping of the buffer
+ * object.
+ */
 int drm_bacon_bo_unmap(drm_bacon_bo *bo);
 
+/** Write data into an object. */
 int drm_bacon_bo_subdata(drm_bacon_bo *bo, unsigned long offset,
 unsigned long size, const void *data);
+/** Read data from an object. */
 int drm_bacon_bo_get_subdata(drm_bacon_bo *bo, unsigned long offset,
 unsigned long size, void *data);
+/**
+ * Waits for rendering to an object by the GPU to have completed.
+ *
+ * This is not required for any access to the BO by bo_map,
+ * bo_subdata, etc. 

[Mesa-dev] [PATCH 16/53] i965/drm: Use Mesa's macros.h instead of duplicating them.

[Kenneth Graunke]

---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  |  5 ++---
 src/mesa/drivers/dri/i965/intel_bufmgr_priv.h |  4 
 src/mesa/drivers/dri/i965/libdrm_macros.h | 10 +-
 3 files changed, 3 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index d2bc3ed66cb..b981658e920 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -57,6 +57,8 @@
 #define ETIME ETIMEDOUT
 #endif
 #include "libdrm_macros.h"
+#include "main/macros.h"
+#include "util/macros.h"
 #include "util/list.h"
 #include "brw_bufmgr.h"
 #include "intel_bufmgr_priv.h"
@@ -81,9 +83,6 @@
fprintf(stderr, __VA_ARGS__);   \
 } while (0)
 
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-#define MAX2(A, B) ((A) > (B) ? (A) : (B))
-
 static inline int
 atomic_add_unless(int *v, int add, int unless)
 {
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h 
b/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h
index 58c21982001..26ffd18234a 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_priv.h
@@ -285,8 +285,4 @@ struct _drm_bacon_context {
struct _drm_bacon_bufmgr *bufmgr;
 };
 
-#define ALIGN(value, alignment)((value + alignment - 1) & ~(alignment 
- 1))
-#define ROUND_UP_TO(x, y)  (((x) + (y) - 1) / (y) * (y))
-#define ROUND_UP_TO_MB(x)  ROUND_UP_TO((x), 1024*1024)
-
 #endif /* INTEL_BUFMGR_PRIV_H */
diff --git a/src/mesa/drivers/dri/i965/libdrm_macros.h 
b/src/mesa/drivers/dri/i965/libdrm_macros.h
index 7427fb18989..8be103c5b7a 100644
--- a/src/mesa/drivers/dri/i965/libdrm_macros.h
+++ b/src/mesa/drivers/dri/i965/libdrm_macros.h
@@ -23,15 +23,7 @@
 #ifndef LIBDRM_LIBDRM_H
 #define LIBDRM_LIBDRM_H
 
-/**
- * Static (compile-time) assertion.
- * Basically, use COND to dimension an array.  If COND is false/zero the
- * array size will be -1 and we'll get a compilation error.
- */
-#define STATIC_ASSERT(COND) \
-   do { \
-  (void) sizeof(char [1 - 2*!(COND)]); \
-   } while (0)
+#include "util/macros.h"
 
 
 #include 
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 13/53] i965/drm: Remove a bunch of gen < 4 stuff

[Kenneth Graunke]

Based on a patch by Kristian Høgsberg.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h|   5 -
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 237 ++
 src/mesa/drivers/dri/i965/intel_bufmgr_priv.h |   5 -
 3 files changed, 13 insertions(+), 234 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index afac9aebdfa..a9cf0ff85f2 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -138,10 +138,6 @@ int drm_bacon_bufmgr_check_aperture_space(drm_bacon_bo ** 
bo_array, int count);
 int drm_bacon_bo_emit_reloc(drm_bacon_bo *bo, uint32_t offset,
drm_bacon_bo *target_bo, uint32_t target_offset,
uint32_t read_domains, uint32_t write_domain);
-int drm_bacon_bo_emit_reloc_fence(drm_bacon_bo *bo, uint32_t offset,
- drm_bacon_bo *target_bo,
- uint32_t target_offset,
- uint32_t read_domains, uint32_t write_domain);
 int drm_bacon_bo_set_tiling(drm_bacon_bo *bo, uint32_t * tiling_mode,
uint32_t stride);
 int drm_bacon_bo_get_tiling(drm_bacon_bo *bo, uint32_t * tiling_mode,
@@ -161,7 +157,6 @@ drm_bacon_bo 
*drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr *bufmgr,
const char *name,
unsigned int handle);
 void drm_bacon_bufmgr_gem_enable_reuse(drm_bacon_bufmgr *bufmgr);
-void drm_bacon_bufmgr_gem_enable_fenced_relocs(drm_bacon_bufmgr *bufmgr);
 void drm_bacon_bufmgr_gem_set_vma_cache_size(drm_bacon_bufmgr *bufmgr,
 int limit);
 int drm_bacon_gem_bo_map_unsynchronized(drm_bacon_bo *bo);
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index b403bd70f09..6f46554d1f7 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -148,19 +148,16 @@ typedef struct _drm_bacon_bufmgr_gem {
int vma_count, vma_open, vma_max;
 
uint64_t gtt_size;
-   int available_fences;
int pci_device;
int gen;
unsigned int has_bsd : 1;
unsigned int has_blt : 1;
-   unsigned int has_relaxed_fencing : 1;
unsigned int has_llc : 1;
unsigned int has_wait_timeout : 1;
unsigned int bo_reuse : 1;
unsigned int no_exec : 1;
unsigned int has_vebox : 1;
unsigned int has_exec_async : 1;
-   bool fenced_relocs;
 
struct {
void *ptr;
@@ -169,11 +166,8 @@ typedef struct _drm_bacon_bufmgr_gem {
 
 } drm_bacon_bufmgr_gem;
 
-#define DRM_INTEL_RELOC_FENCE (1<<0)
-
 typedef struct _drm_bacon_reloc_target_info {
drm_bacon_bo *bo;
-   int flags;
 } drm_bacon_reloc_target;
 
 struct _drm_bacon_bo_gem {
@@ -287,12 +281,6 @@ struct _drm_bacon_bo_gem {
 */
int reloc_tree_size;
 
-   /**
-* Number of potential fence registers required by this buffer and its
-* relocations.
-*/
-   int reloc_tree_fences;
-
/** Flags that we may need to do the SW_FINISH ioctl on unmap. */
bool mapped_cpu_write;
 };
@@ -328,38 +316,11 @@ static unsigned long
 drm_bacon_gem_bo_tile_size(drm_bacon_bufmgr_gem *bufmgr_gem, unsigned long 
size,
   uint32_t *tiling_mode)
 {
-   unsigned long min_size, max_size;
-   unsigned long i;
-
if (*tiling_mode == I915_TILING_NONE)
return size;
 
/* 965+ just need multiples of page size for tiling */
-   if (bufmgr_gem->gen >= 4)
-   return ROUND_UP_TO(size, 4096);
-
-   /* Older chips need powers of two, of at least 512k or 1M */
-   if (bufmgr_gem->gen == 3) {
-   min_size = 1024*1024;
-   max_size = 128*1024*1024;
-   } else {
-   min_size = 512*1024;
-   max_size = 64*1024*1024;
-   }
-
-   if (size > max_size) {
-   *tiling_mode = I915_TILING_NONE;
-   return size;
-   }
-
-   /* Do we need to allocate every page for the fence? */
-   if (bufmgr_gem->has_relaxed_fencing)
-   return ROUND_UP_TO(size, 4096);
-
-   for (i = min_size; i < size; i <<= 1)
-   ;
-
-   return i;
+   return ROUND_UP_TO(size, 4096);
 }
 
 /*
@@ -372,7 +333,6 @@ drm_bacon_gem_bo_tile_pitch(drm_bacon_bufmgr_gem 
*bufmgr_gem,
unsigned long pitch, uint32_t *tiling_mode)
 {
unsigned long tile_width;
-   unsigned long i;
 
/* If untiled, then just align it so that we can do rendering
 * to it with the 3D engine.
@@ -380,30 +340,13 @@ drm_bacon_gem_bo_tile_pitch(drm_bacon_bufmgr_gem 
*bufmgr_gem,
if (*tiling_mode == I915_TILING_NONE)
return 

[Mesa-dev] [PATCH 15/53] i965/drm: Use ALIGN, not ROUND_UP_TO.

[Kenneth Graunke]

ROUND_UP_TO handles a NPOT alignment, but all the alignments we use
are power of two anyway, so there's no need.
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 3b9272b32ba..d2bc3ed66cb 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -319,7 +319,7 @@ drm_bacon_gem_bo_tile_size(drm_bacon_bufmgr_gem 
*bufmgr_gem, unsigned long size,
return size;
 
/* 965+ just need multiples of page size for tiling */
-   return ROUND_UP_TO(size, 4096);
+   return ALIGN(size, 4096);
 }
 
 /*
@@ -345,7 +345,7 @@ drm_bacon_gem_bo_tile_pitch(drm_bacon_bufmgr_gem 
*bufmgr_gem,
tile_width = 128;
 
/* 965 is flexible */
-   return ROUND_UP_TO(pitch, tile_width);
+   return ALIGN(pitch, tile_width);
 }
 
 static struct drm_bacon_gem_bo_bucket *
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 14/53] i965/drm: Delete execbuf1 support.

[Kenneth Graunke]

execbuf2 has been around for years.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c | 183 +--
 1 file changed, 2 insertions(+), 181 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 6f46554d1f7..3b9272b32ba 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -128,7 +128,6 @@ typedef struct _drm_bacon_bufmgr_gem {
 
pthread_mutex_t lock;
 
-   struct drm_i915_gem_exec_object *exec_objects;
struct drm_i915_gem_exec_object2 *exec2_objects;
drm_bacon_bo **exec_bos;
int exec_size;
@@ -428,52 +427,6 @@ drm_bacon_gem_bo_reference(drm_bacon_bo *bo)
p_atomic_inc(_gem->refcount);
 }
 
-/**
- * Adds the given buffer to the list of buffers to be validated (moved into the
- * appropriate memory type) with the next batch submission.
- *
- * If a buffer is validated multiple times in a batch submission, it ends up
- * with the intersection of the memory type flags and the union of the
- * access flags.
- */
-static void
-drm_bacon_add_validate_buffer(drm_bacon_bo *bo)
-{
-   drm_bacon_bufmgr_gem *bufmgr_gem = (drm_bacon_bufmgr_gem *) bo->bufmgr;
-   drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
-   int index;
-
-   if (bo_gem->validate_index != -1)
-   return;
-
-   /* Extend the array of validation entries as necessary. */
-   if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
-   int new_size = bufmgr_gem->exec_size * 2;
-
-   if (new_size == 0)
-   new_size = 5;
-
-   bufmgr_gem->exec_objects =
-   realloc(bufmgr_gem->exec_objects,
-   sizeof(*bufmgr_gem->exec_objects) * new_size);
-   bufmgr_gem->exec_bos =
-   realloc(bufmgr_gem->exec_bos,
-   sizeof(*bufmgr_gem->exec_bos) * new_size);
-   bufmgr_gem->exec_size = new_size;
-   }
-
-   index = bufmgr_gem->exec_count;
-   bo_gem->validate_index = index;
-   /* Fill in array entry */
-   bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
-   bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
-   bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs;
-   bufmgr_gem->exec_objects[index].alignment = bo->align;
-   bufmgr_gem->exec_objects[index].offset = 0;
-   bufmgr_gem->exec_bos[index] = bo;
-   bufmgr_gem->exec_count++;
-}
-
 static void
 drm_bacon_add_validate_buffer2(drm_bacon_bo *bo)
 {
@@ -1796,7 +1749,6 @@ drm_bacon_bufmgr_gem_destroy(drm_bacon_bufmgr *bufmgr)
int i, ret;
 
free(bufmgr_gem->exec2_objects);
-   free(bufmgr_gem->exec_objects);
free(bufmgr_gem->exec_bos);
 
pthread_mutex_destroy(_gem->lock);
@@ -2002,36 +1954,6 @@ drm_bacon_gem_bo_clear_relocs(drm_bacon_bo *bo, int 
start)
 
 }
 
-/**
- * Walk the tree of relocations rooted at BO and accumulate the list of
- * validations to be performed and update the relocation buffers with
- * index values into the validation list.
- */
-static void
-drm_bacon_gem_bo_process_reloc(drm_bacon_bo *bo)
-{
-   drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
-   int i;
-
-   if (bo_gem->relocs == NULL)
-   return;
-
-   for (i = 0; i < bo_gem->reloc_count; i++) {
-   drm_bacon_bo *target_bo = bo_gem->reloc_target_info[i].bo;
-
-   if (target_bo == bo)
-   continue;
-
-   drm_bacon_gem_bo_mark_mmaps_incoherent(bo);
-
-   /* Continue walking the tree depth-first. */
-   drm_bacon_gem_bo_process_reloc(target_bo);
-
-   /* Add the target to the validate list */
-   drm_bacon_add_validate_buffer(target_bo);
-   }
-}
-
 static void
 drm_bacon_gem_bo_process_reloc2(drm_bacon_bo *bo)
 {
@@ -2068,30 +1990,6 @@ drm_bacon_gem_bo_process_reloc2(drm_bacon_bo *bo)
}
 }
 
-
-static void
-drm_bacon_update_buffer_offsets(drm_bacon_bufmgr_gem *bufmgr_gem)
-{
-   int i;
-
-   for (i = 0; i < bufmgr_gem->exec_count; i++) {
-   drm_bacon_bo *bo = bufmgr_gem->exec_bos[i];
-   drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
-
-   /* Update the buffer offset */
-   if (bufmgr_gem->exec_objects[i].offset != bo->offset64) {
-   DBG("BO %d (%s) migrated: 0x%08x %08x -> 0x%08x %08x\n",
-   bo_gem->gem_handle, bo_gem->name,
-   upper_32_bits(bo->offset64),
-   lower_32_bits(bo->offset64),
-   upper_32_bits(bufmgr_gem->exec_objects[i].offset),
-   lower_32_bits(bufmgr_gem->exec_objects[i].offset));
-  

[Mesa-dev] [PATCH 10/53] i965/drm: Port to Mesa's atomic header.

[Kenneth Graunke]

Drop xf86atomic.h in favor of Mesa's util/u_atomic.h.  We replace the
atomic_t wrapper struct with a bare integer, switch to the 'p_atomic'
naming conventions, and move over the one extra helper.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/Makefile.sources   |   3 +-
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c |  40 ++
 src/mesa/drivers/dri/i965/xf86atomic.h   | 113 ---
 3 files changed, 26 insertions(+), 130 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/xf86atomic.h

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index fe20116b9be..9ae764fed58 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -165,8 +165,7 @@ i965_FILES = \
intel_upload.c \
libdrm_lists.h \
libdrm_macros.h \
-   uthash.h \
-   xf86atomic.h
+   uthash.h
 
 i965_gen6_FILES = \
genX_blorp_exec.c
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index 4f9d6be7ac8..c67f813bdf5 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -39,7 +39,7 @@
 #endif
 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -84,6 +84,16 @@
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #define MAX2(A, B) ((A) > (B) ? (A) : (B))
 
+static inline int
+atomic_add_unless(int *v, int add, int unless)
+{
+   int c, old;
+   c = p_atomic_read(v);
+   while (c != unless && (old = p_atomic_cmpxchg(v, c, c + add)) != c)
+  c = old;
+   return c == unless;
+}
+
 /**
  * upper_32_bits - return bits 32-63 of a number
  * @n: the number we're accessing
@@ -110,7 +120,7 @@ struct drm_bacon_gem_bo_bucket {
 typedef struct _drm_bacon_bufmgr_gem {
drm_bacon_bufmgr bufmgr;
 
-   atomic_t refcount;
+   int refcount;
 
int fd;
 
@@ -169,7 +179,7 @@ typedef struct _drm_bacon_reloc_target_info {
 struct _drm_bacon_bo_gem {
drm_bacon_bo bo;
 
-   atomic_t refcount;
+   int refcount;
uint32_t gem_handle;
const char *name;
 
@@ -472,7 +482,7 @@ drm_bacon_gem_bo_reference(drm_bacon_bo *bo)
 {
drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
 
-   atomic_inc(_gem->refcount);
+   p_atomic_inc(_gem->refcount);
 }
 
 /**
@@ -834,7 +844,7 @@ retry:
}
 
bo_gem->name = name;
-   atomic_set(_gem->refcount, 1);
+   p_atomic_set(_gem->refcount, 1);
bo_gem->validate_index = -1;
bo_gem->reloc_tree_fences = 0;
bo_gem->used_as_reloc_target = false;
@@ -954,7 +964,7 @@ drm_bacon_gem_bo_alloc_userptr(drm_bacon_bufmgr *bufmgr,
if (!bo_gem)
return NULL;
 
-   atomic_set(_gem->refcount, 1);
+   p_atomic_set(_gem->refcount, 1);
DRMINITLISTHEAD(_gem->vma_list);
 
bo_gem->bo.size = size;
@@ -1131,7 +1141,7 @@ drm_bacon_bo_gem_create_from_name(drm_bacon_bufmgr 
*bufmgr,
if (!bo_gem)
goto out;
 
-   atomic_set(_gem->refcount, 1);
+   p_atomic_set(_gem->refcount, 1);
DRMINITLISTHEAD(_gem->vma_list);
 
bo_gem->bo.size = open_arg.size;
@@ -1402,8 +1412,8 @@ static void 
drm_bacon_gem_bo_unreference_locked_timed(drm_bacon_bo *bo,
 {
drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
 
-   assert(atomic_read(_gem->refcount) > 0);
-   if (atomic_dec_and_test(_gem->refcount))
+   assert(p_atomic_read(_gem->refcount) > 0);
+   if (p_atomic_dec_zero(_gem->refcount))
drm_bacon_gem_bo_unreference_final(bo, time);
 }
 
@@ -1411,7 +1421,7 @@ static void drm_bacon_gem_bo_unreference(drm_bacon_bo *bo)
 {
drm_bacon_bo_gem *bo_gem = (drm_bacon_bo_gem *) bo;
 
-   assert(atomic_read(_gem->refcount) > 0);
+   assert(p_atomic_read(_gem->refcount) > 0);
 
if (atomic_add_unless(_gem->refcount, -1, 1)) {
drm_bacon_bufmgr_gem *bufmgr_gem =
@@ -1422,7 +1432,7 @@ static void drm_bacon_gem_bo_unreference(drm_bacon_bo *bo)
 
pthread_mutex_lock(_gem->lock);
 
-   if (atomic_dec_and_test(_gem->refcount)) {
+   if (p_atomic_dec_zero(_gem->refcount)) {
drm_bacon_gem_bo_unreference_final(bo, time.tv_sec);
drm_bacon_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec);
}
@@ -2657,7 +2667,7 @@ drm_bacon_bo_gem_create_from_prime(drm_bacon_bufmgr 
*bufmgr, int prime_fd, int s
if (!bo_gem)
goto out;
 
-   atomic_set(_gem->refcount, 1);
+   p_atomic_set(_gem->refcount, 1);
DRMINITLISTHEAD(_gem->vma_list);
 
/* Determine size of bo.  The fd-to-handle ioctl really should
@@ -3368,7 +3378,7 @@ drm_bacon_bufmgr_gem_find(int fd)
 
DRMLISTFOREACHENTRY(bufmgr_gem, _list, managers) {
if (bufmgr_gem->fd == fd) {
- 

[Mesa-dev] [PATCH 12/53] i965/drm: Remove some unused functions and macros.

[Kenneth Graunke]

Based on a patch by Kristian Høgsberg.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h|  12 --
 src/mesa/drivers/dri/i965/intel_bufmgr.c  |  49 
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c  | 170 --
 src/mesa/drivers/dri/i965/intel_bufmgr_priv.h |  28 -
 src/mesa/drivers/dri/i965/libdrm_macros.h |   7 --
 5 files changed, 266 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index cf5e8598a6d..afac9aebdfa 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -142,8 +142,6 @@ int drm_bacon_bo_emit_reloc_fence(drm_bacon_bo *bo, 
uint32_t offset,
  drm_bacon_bo *target_bo,
  uint32_t target_offset,
  uint32_t read_domains, uint32_t write_domain);
-int drm_bacon_bo_pin(drm_bacon_bo *bo, uint32_t alignment);
-int drm_bacon_bo_unpin(drm_bacon_bo *bo);
 int drm_bacon_bo_set_tiling(drm_bacon_bo *bo, uint32_t * tiling_mode,
uint32_t stride);
 int drm_bacon_bo_get_tiling(drm_bacon_bo *bo, uint32_t * tiling_mode,
@@ -151,7 +149,6 @@ int drm_bacon_bo_get_tiling(drm_bacon_bo *bo, uint32_t * 
tiling_mode,
 int drm_bacon_bo_flink(drm_bacon_bo *bo, uint32_t * name);
 int drm_bacon_bo_busy(drm_bacon_bo *bo);
 int drm_bacon_bo_madvise(drm_bacon_bo *bo, int madv);
-int drm_bacon_bo_use_48b_address_range(drm_bacon_bo *bo, uint32_t enable);
 int drm_bacon_bo_set_softpin_offset(drm_bacon_bo *bo, uint64_t offset);
 
 int drm_bacon_bo_disable_reuse(drm_bacon_bo *bo);
@@ -169,7 +166,6 @@ void 
drm_bacon_bufmgr_gem_set_vma_cache_size(drm_bacon_bufmgr *bufmgr,
 int limit);
 int drm_bacon_gem_bo_map_unsynchronized(drm_bacon_bo *bo);
 int drm_bacon_gem_bo_map_gtt(drm_bacon_bo *bo);
-int drm_bacon_gem_bo_unmap_gtt(drm_bacon_bo *bo);
 
 #define HAVE_DRM_INTEL_GEM_BO_DISABLE_IMPLICIT_SYNC 1
 int drm_bacon_bufmgr_gem_can_disable_implicit_sync(drm_bacon_bufmgr *bufmgr);
@@ -184,8 +180,6 @@ int drm_bacon_gem_bo_get_reloc_count(drm_bacon_bo *bo);
 void drm_bacon_gem_bo_clear_relocs(drm_bacon_bo *bo, int start);
 void drm_bacon_gem_bo_start_gtt_access(drm_bacon_bo *bo, int write_enable);
 
-int drm_bacon_get_pipe_from_crtc_id(drm_bacon_bufmgr *bufmgr, int crtc_id);
-
 int drm_bacon_bufmgr_gem_get_devid(drm_bacon_bufmgr *bufmgr);
 int drm_bacon_gem_bo_wait(drm_bacon_bo *bo, int64_t timeout_ns);
 
@@ -215,12 +209,6 @@ int drm_bacon_get_reset_stats(drm_bacon_context *ctx,
  uint32_t *active,
  uint32_t *pending);
 
-int drm_bacon_get_subslice_total(int fd, unsigned int *subslice_total);
-int drm_bacon_get_eu_total(int fd, unsigned int *eu_total);
-
-int drm_bacon_get_pooled_eu(int fd);
-int drm_bacon_get_min_eu_in_pool(int fd);
-
 /** @{ */
 
 #if defined(__cplusplus)
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr.c
index 1adf854dc70..a8e8ae7da65 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr.c
@@ -206,36 +206,6 @@ drm_bacon_bo_emit_reloc(drm_bacon_bo *bo, uint32_t offset,
 read_domains, write_domain);
 }
 
-/* For fence registers, not GL fences */
-int
-drm_bacon_bo_emit_reloc_fence(drm_bacon_bo *bo, uint32_t offset,
- drm_bacon_bo *target_bo, uint32_t target_offset,
- uint32_t read_domains, uint32_t write_domain)
-{
-   return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
-  target_bo, target_offset,
-  read_domains, write_domain);
-}
-
-
-int
-drm_bacon_bo_pin(drm_bacon_bo *bo, uint32_t alignment)
-{
-   if (bo->bufmgr->bo_pin)
-   return bo->bufmgr->bo_pin(bo, alignment);
-
-   return -ENODEV;
-}
-
-int
-drm_bacon_bo_unpin(drm_bacon_bo *bo)
-{
-   if (bo->bufmgr->bo_unpin)
-   return bo->bufmgr->bo_unpin(bo);
-
-   return -ENODEV;
-}
-
 int
 drm_bacon_bo_set_tiling(drm_bacon_bo *bo, uint32_t * tiling_mode,
uint32_t stride)
@@ -301,26 +271,7 @@ drm_bacon_bo_madvise(drm_bacon_bo *bo, int madv)
 }
 
 int
-drm_bacon_bo_use_48b_address_range(drm_bacon_bo *bo, uint32_t enable)
-{
-   if (bo->bufmgr->bo_use_48b_address_range) {
-   bo->bufmgr->bo_use_48b_address_range(bo, enable);
-   return 0;
-   }
-
-   return -ENODEV;
-}
-
-int
 drm_bacon_bo_references(drm_bacon_bo *bo, drm_bacon_bo *target_bo)
 {
return bo->bufmgr->bo_references(bo, target_bo);
 }
-
-int
-drm_bacon_get_pipe_from_crtc_id(drm_bacon_bufmgr *bufmgr, int crtc_id)
-{
-   if (bufmgr->get_pipe_from_crtc_id)
-   return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id);
-   return -1;
-}
diff --git 

[Mesa-dev] [PATCH 11/53] i965/drm: Switch to util/list.h instead of libdrm_lists.h.

[Kenneth Graunke]

Both are kernel style lists, so this is trivial.

Signed-off-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/Makefile.sources   |   1 -
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c |  91 ++---
 src/mesa/drivers/dri/i965/libdrm_lists.h | 118 ---
 3 files changed, 45 insertions(+), 165 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/libdrm_lists.h

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 9ae764fed58..1d2c6e06f8b 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -163,7 +163,6 @@ i965_FILES = \
intel_tiled_memcpy.c \
intel_tiled_memcpy.h \
intel_upload.c \
-   libdrm_lists.h \
libdrm_macros.h \
uthash.h
 
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
index c67f813bdf5..e116788e326 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr_gem.c
@@ -57,7 +57,7 @@
 #define ETIME ETIMEDOUT
 #endif
 #include "libdrm_macros.h"
-#include "libdrm_lists.h"
+#include "util/list.h"
 #include "brw_bufmgr.h"
 #include "intel_bufmgr_priv.h"
 #include "intel_chipset.h"
@@ -113,7 +113,7 @@ atomic_add_unless(int *v, int add, int unless)
 typedef struct _drm_bacon_bo_gem drm_bacon_bo_gem;
 
 struct drm_bacon_gem_bo_bucket {
-   drmMMListHead head;
+   struct list_head head;
unsigned long size;
 };
 
@@ -139,12 +139,12 @@ typedef struct _drm_bacon_bufmgr_gem {
int num_buckets;
time_t time;
 
-   drmMMListHead managers;
+   struct list_head managers;
 
drm_bacon_bo_gem *name_table;
drm_bacon_bo_gem *handle_table;
 
-   drmMMListHead vma_cache;
+   struct list_head vma_cache;
int vma_count, vma_open, vma_max;
 
uint64_t gtt_size;
@@ -237,10 +237,10 @@ struct _drm_bacon_bo_gem {
 */
void *user_virtual;
int map_count;
-   drmMMListHead vma_list;
+   struct list_head vma_list;
 
/** BO cache list */
-   drmMMListHead head;
+   struct list_head head;
 
/**
 * Boolean of whether this BO and its children have been included in
@@ -701,16 +701,16 @@ static void
 drm_bacon_gem_bo_cache_purge_bucket(drm_bacon_bufmgr_gem *bufmgr_gem,
struct drm_bacon_gem_bo_bucket *bucket)
 {
-   while (!DRMLISTEMPTY(>head)) {
+   while (!list_empty(>head)) {
drm_bacon_bo_gem *bo_gem;
 
-   bo_gem = DRMLISTENTRY(drm_bacon_bo_gem,
- bucket->head.next, head);
+   bo_gem = LIST_ENTRY(drm_bacon_bo_gem,
+   bucket->head.next, head);
if (drm_bacon_gem_bo_madvise_internal
(bufmgr_gem, bo_gem, I915_MADV_DONTNEED))
break;
 
-   DRMLISTDEL(_gem->head);
+   list_del(_gem->head);
drm_bacon_gem_bo_free(_gem->bo);
}
 }
@@ -754,15 +754,15 @@ drm_bacon_gem_bo_alloc_internal(drm_bacon_bufmgr *bufmgr,
/* Get a buffer out of the cache if available */
 retry:
alloc_from_cache = false;
-   if (bucket != NULL && !DRMLISTEMPTY(>head)) {
+   if (bucket != NULL && !list_empty(>head)) {
if (for_render) {
/* Allocate new render-target BOs from the tail (MRU)
 * of the list, as it will likely be hot in the GPU
 * cache and in the aperture for us.
 */
-   bo_gem = DRMLISTENTRY(drm_bacon_bo_gem,
- bucket->head.prev, head);
-   DRMLISTDEL(_gem->head);
+   bo_gem = LIST_ENTRY(drm_bacon_bo_gem,
+   bucket->head.prev, head);
+   list_del(_gem->head);
alloc_from_cache = true;
bo_gem->bo.align = alignment;
} else {
@@ -774,11 +774,11 @@ retry:
 * allocating a new buffer is probably faster than
 * waiting for the GPU to finish.
 */
-   bo_gem = DRMLISTENTRY(drm_bacon_bo_gem,
- bucket->head.next, head);
+   bo_gem = LIST_ENTRY(drm_bacon_bo_gem,
+   bucket->head.next, head);
if (!drm_bacon_gem_bo_busy(_gem->bo)) {
alloc_from_cache = true;
-   DRMLISTDEL(_gem->head);
+   list_del(_gem->head);
}
}
 
@@ -807,9 +807,9 @@ retry:
if 

[Mesa-dev] [PATCH 01/53] i965: Fix GLX_MESA_query_renderer video memory on 32-bit.

[Kenneth Graunke]

On modern systems with 4GB apertures, the size in bytes is 4294967296,
or (1ull << 32).  The kernel gives us the aperture size as a __u64,
which works out great.

Unfortunately, libdrm "helpfully" returns the data as a size_t, which
on 32-bit systems means it truncates the aperture size to 0 bytes.
We've happily reported this value as 0 MB of video memory via
GLX_MESA_query_renderer since it was originally exposed.

This patch bypasses libdrm and calls the ioctl ourselves so we can
use a proper uint64_t, avoiding the 32-bit integer overflow.  We now
report a proper video memory size on 32-bit systems.
---
 src/mesa/drivers/dri/i965/intel_screen.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 811a9c5a867..f94e8a77c10 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -950,6 +950,17 @@ static const __DRIimageExtension intelImageExtension = {
 .createImageWithModifiers   = intel_create_image_with_modifiers,
 };
 
+static uint64_t
+get_aperture_size(int fd)
+{
+   struct drm_i915_gem_get_aperture aperture;
+
+   if (drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, ) != 0)
+  return 0;
+
+   return aperture.aper_size;
+}
+
 static int
 brw_query_renderer_integer(__DRIscreen *dri_screen,
int param, unsigned int *value)
@@ -972,10 +983,7 @@ brw_query_renderer_integer(__DRIscreen *dri_screen,
* assume that there's some fragmentation, and we start doing extra
* flushing, etc.  That's the big cliff apps will care about.
*/
-  size_t aper_size;
-  size_t mappable_size;
-
-  drm_intel_get_aperture_sizes(dri_screen->fd, _size, _size);
+  uint64_t aper_size = get_aperture_size(dri_screen->fd);
 
   const unsigned gpu_mappable_megabytes =
  (aper_size / (1024 * 1024)) * 3 / 4;
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 00/53] i965: Eat libdrm_intel for breakfast

[Kenneth Graunke]

Hello,

This series imports libdrm_intel into the i965 driver, hacks and
slashes it down to size, and greatly simplifies our relocation
handling.

Some of the patches may be held for moderation.  You can find the
series in git here:

https://cgit.freedesktop.org/~kwg/mesa/log/?h=bacondrm

A couple of us have been talking about this in person and IRC for
a while, but I realize I haven't mentioned anything about it on the
mailing list yet, so this may come as a bit of a surprise.

libdrm_intel is about 15 source files and almost 13,000 lines of code.
This series adds 3 files (one .c, two .h) and only 2,137 lines of code:

60 files changed, 2784 insertions(+), 647 deletions(-)

The rest of the library is basically useless to us.  It contains a lot
of legacy cruft from the pre-GEM, DRI1, or 8xx/9xx era.  But even the
parts we do use are in bad shape.  BO offset tracking is non-threadsafe.
Relocation handling is way too complicated.  These things waste memory,
burn CPU time, and make it difficult for us to take advantage of new
kernel features like I915_EXEC_NO_RELOC which would reduce overhead
further.  The unsynchronized mapping API performs a synchronized mapping
on non-LLC platforms, which can massively hurt performance on Atoms.
Mesa is also using uncached GTT mappings for almost everything on Atoms,
rather than fast CPU or WC maps where possible.

Evolving this code in libdrm is very painful, as we aren't allowed to
break the ABI.  All the legacy cruft and design mistakes (in hindsight)
make it difficult to follow what's going on.  We could keep piling new
layers on top, but that only makes it worse.  Furthermore, there's a
bunch of complexity that comes from defending against or supporting
broken or badly designed callers.

This series begins making incremental progress towards a better future
by importing libdrm_intel, and adjusting it to fit our needs.  libdrm
provides some fairly foundational pieces of the driver, so it's not
easy to move away from it in one swoop.  The series does not yet solve
most of the problems, but it does cut 85% of the code out, and removes
ABI-guarantee problems, which should make it much easier to work with.

I apologize that it may be difficult to review: most people aren't
familiar with this code (I learned a lot myself), and it's kind of
huge.  I tried.

Thanks to Chris and Daniel for telling us to do this for years.
Thanks for Kristian and Emil for both independently trying to clean
up this mess in the past.  Let's finally do it!

--Ken

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 02/53] i965: Stop calling drm_intel_bufmgr_gem_enable_fenced_relocs().

[Kenneth Graunke]

This does nothing on Gen4+, which is the only hardware we support.
---
 src/mesa/drivers/dri/i965/intel_screen.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index f94e8a77c10..fd15c37e943 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1280,8 +1280,6 @@ intel_init_bufmgr(struct intel_screen *screen)
   return false;
}
 
-   drm_intel_bufmgr_gem_enable_fenced_relocs(screen->bufmgr);
-
if (!intel_get_boolean(screen, I915_PARAM_HAS_WAIT_TIMEOUT)) {
   fprintf(stderr, "[%s: %u] Kernel 3.6 required.\n", __func__, __LINE__);
   return false;
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 03/53] i965: Make sure we don't use CPU maps for the scanout buffer.

[Kenneth Graunke]

Using an incoherent CPU map on the active scanout buffer is really
sketchy - we may need extra flushing via GEM_SW_FINISH, or using
drmModeDirtyFB() and kernel commit a6a7cc4b7db6d (4.10+).

Chris suggests "never ever do that", which seems like a wise plan!

intel_miptree_map_raw() uses CPU maps on linear buffers.

Having a linear scanout buffer should be really rare, and mapping the
front buffer should be similarly rare.  Together, it should basically
never happen.  But, in case it does somehow...make sure that mapping
the scanout buffer always goes through an uncached GTT map.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 467ada5079b..272eb49867e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2460,7 +2460,7 @@ intel_miptree_map_raw(struct brw_context *brw, struct 
intel_mipmap_tree *mt)
if (drm_intel_bo_references(brw->batch.bo, bo))
   intel_batchbuffer_flush(brw);
 
-   if (mt->tiling != I915_TILING_NONE)
+   if (mt->tiling != I915_TILING_NONE || mt->is_scanout)
   brw_bo_map_gtt(brw, bo, "miptree");
else
   brw_bo_map(brw, bo, true, "miptree");
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 05/53] i965/drm: remove legacy defines, aub functions, and decoder prototypes

[Kenneth Graunke]

We never imported any of this code, so drop the prototypes, unused
enums, and defines.

Based on patches by Emil Velikov.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   | 110 ---
 src/mesa/drivers/dri/i965/intel_bufmgr_gem.c |  66 
 2 files changed, 176 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 693472a527f..0a6f70c665a 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -96,19 +96,6 @@ struct _drm_intel_bo {
uint64_t offset64;
 };
 
-enum aub_dump_bmp_format {
-   AUB_DUMP_BMP_FORMAT_8BIT = 1,
-   AUB_DUMP_BMP_FORMAT_ARGB_ = 4,
-   AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
-   AUB_DUMP_BMP_FORMAT_ARGB_ = 7,
-};
-
-typedef struct _drm_intel_aub_annotation {
-   uint32_t type;
-   uint32_t subtype;
-   uint32_t ending_offset;
-} drm_intel_aub_annotation;
-
 #define BO_ALLOC_FOR_RENDER (1<<0)
 
 drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
@@ -197,19 +184,6 @@ int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
 void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
 void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
 
-void
-drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
- const char *filename);
-void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
-void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
-  int x1, int y1, int width, int height,
-  enum aub_dump_bmp_format format,
-  int pitch, int offset);
-void
-drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
-drm_intel_aub_annotation *annotations,
-unsigned count);
-
 int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
 
 int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
@@ -233,51 +207,6 @@ int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int 
*prime_fd);
 drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
int prime_fd, int size);
 
-/* drm_intel_bufmgr_fake.c */
-drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
-unsigned long low_offset,
-void *low_virtual,
-unsigned long size,
-volatile unsigned int
-*last_dispatch);
-void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
-volatile unsigned int
-*last_dispatch);
-void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
-int (*exec) (drm_intel_bo *bo,
- unsigned int used,
- void *priv),
-void *priv);
-void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
- unsigned int (*emit) (void *priv),
- void (*wait) (unsigned int fence,
-   void *priv),
- void *priv);
-drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
-const char *name,
-unsigned long offset,
-unsigned long size, void *virt);
-void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
-void (*invalidate_cb) (drm_intel_bo
-   * bo,
-   void *ptr),
-void *ptr);
-
-void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
-void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
-
-struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
-void drm_intel_decode_context_free(struct drm_intel_decode *ctx);
-void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
-   void *data, uint32_t hw_offset,
-   int count);
-void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
-   int dump_past_end);
-void 

[Mesa-dev] [PATCH 06/53] i965/drm: Use __typeof__ rather than typeof.

[Kenneth Graunke]

typeof doesn't seem to exist.  This code is going to die soon anyway.
---
 src/mesa/drivers/dri/i965/libdrm_lists.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/libdrm_lists.h 
b/src/mesa/drivers/dri/i965/libdrm_lists.h
index 8926d8d1a67..d0a2528847f 100644
--- a/src/mesa/drivers/dri/i965/libdrm_lists.h
+++ b/src/mesa/drivers/dri/i965/libdrm_lists.h
@@ -96,18 +96,18 @@ typedef struct _drmMMListHead
 (__item) = (__temp), (__temp) = (__item)->prev)
 
 #define DRMLISTFOREACHENTRY(__item, __list, __head)
\
-   for ((__item) = DRMLISTENTRY(typeof(*__item), (__list)->next, __head); \
+   for ((__item) = DRMLISTENTRY(__typeof__(*__item), (__list)->next, 
__head); \
 &(__item)->__head != (__list);\
-(__item) = DRMLISTENTRY(typeof(*__item),  \
+(__item) = DRMLISTENTRY(__typeof__(*__item),   
   \
 (__item)->__head.next, __head))
 
 #define DRMLISTFOREACHENTRYSAFE(__item, __temp, __list, __head)
\
-   for ((__item) = DRMLISTENTRY(typeof(*__item), (__list)->next, __head), \
-(__temp) = DRMLISTENTRY(typeof(*__item),  \
+   for ((__item) = DRMLISTENTRY(__typeof__(*__item), (__list)->next, 
__head), \
+(__temp) = DRMLISTENTRY(__typeof__(*__item),   
   \
 (__item)->__head.next, __head);   \
 &(__item)->__head != (__list);\
 (__item) = (__temp),  \
-(__temp) = DRMLISTENTRY(typeof(*__item),  \
+(__temp) = DRMLISTENTRY(__typeof__(*__item),   
   \
 (__temp)->__head.next, __head))
 
 #define DRMLISTJOIN(__list, __join) if (!DRMLISTEMPTY(__list)) {   \
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 07/53] i965/drm: Drop libpciaccess dependencies.

[Kenneth Graunke]

i965 doesn't use drm_intel_get_aperture_sizes(), so we can delete
support for it.  This avoids a build dependency on libpciaccess.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.h   |  1 -
 src/mesa/drivers/dri/i965/intel_bufmgr.c | 48 
 2 files changed, 49 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 0a6f70c665a..29620ca5a99 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -186,7 +186,6 @@ void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, 
int write_enable);
 
 int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
 
-int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
 int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
 int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
 
diff --git a/src/mesa/drivers/dri/i965/intel_bufmgr.c 
b/src/mesa/drivers/dri/i965/intel_bufmgr.c
index a285340039f..cdb4359739b 100644
--- a/src/mesa/drivers/dri/i965/intel_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/intel_bufmgr.c
@@ -36,7 +36,6 @@
 #include 
 #include 
 #include 
-#include 
 #include "libdrm_macros.h"
 #include "intel_bufmgr.h"
 #include "intel_bufmgr_priv.h"
@@ -325,50 +324,3 @@ drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, 
int crtc_id)
return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id);
return -1;
 }
-
-static size_t
-drm_intel_probe_agp_aperture_size(int fd)
-{
-   struct pci_device *pci_dev;
-   size_t size = 0;
-   int ret;
-
-   ret = pci_system_init();
-   if (ret)
-   goto err;
-
-   /* XXX handle multiple adaptors? */
-   pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
-   if (pci_dev == NULL)
-   goto err;
-
-   ret = pci_device_probe(pci_dev);
-   if (ret)
-   goto err;
-
-   size = pci_dev->regions[2].size;
-err:
-   pci_system_cleanup ();
-   return size;
-}
-
-int
-drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total)
-{
-
-   struct drm_i915_gem_get_aperture aperture;
-   int ret;
-
-   ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, );
-   if (ret)
-   return ret;
-
-   *mappable = 0;
-   /* XXX add a query for the kernel value? */
-   if (*mappable == 0)
-   *mappable = drm_intel_probe_agp_aperture_size(fd);
-   if (*mappable == 0)
-   *mappable = 64 * 1024 * 1024; /* minimum possible value */
-   *total = aperture.aper_size;
-   return 0;
-}
-- 
2.12.1

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 100569] core/resource.cpp:36:33: error: non-constant-expression cannot be narrowed from type 'int' to 'int16_t' (aka 'short') in initializer list [-Wc++11-narrowing]

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100569

Vinson Lee  changed:

   What|Removed |Added

 CC||curroje...@riseup.net

-- 
You are receiving this mail because:
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

--- Comment #18 from Jonathan Gray  ---
(In reply to Matt Turner from comment #16)
> (In reply to Jonathan Gray from comment #15)
> > Shocking as it may seem Mesa runs on more than just Linux.
> 
> Don't act like that. Grazvydas wrote code to fix a bug you reported more
> than two years ago. You should be thankful, not sarcastic.
> 
> Presumably if you don't piss him off he'd be amenable to fixing other things
> in this area.

The problem was clearly stated in the original report.  The changes that went
in have not addressed this.  Only a variant that concerns a subset.  Closing
the bug because it fixed the case he cared about and not the actual reported
problem isn't helping anyone.

I've had to workaround the breakage for years to be able to ship builds of Mesa
on multiple architectures.

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

--- Comment #17 from Matt Turner  ---
(In reply to Grazvydas Ignotas from comment #14)
> Yes but any affected platforms we actually care about?
> 
> Newer gcc should cover some of the cases mentioned in this bug. I think
> pre-v6 ARM now has 32bit atomics on Linux thanks to a kernel helper.
> Others you mentioned are hppa and superh, is anyone actually building mesa
> for those?
> 
> Otherwise it will just be wasted effort for some dead code that nobody ever
> uses.

Gentoo supports both hppa and sh. I find it doubtful that anyone would use Mesa
on sh, but hppa is well maintained. I should have a system running in a few
days on which I can test.

You figured out the solution -- I'm happy to copy-and-paste your small amount
of code to support hppa.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

--- Comment #16 from Matt Turner  ---
(In reply to Jonathan Gray from comment #15)
> Shocking as it may seem Mesa runs on more than just Linux.

Don't act like that. Grazvydas wrote code to fix a bug you reported more than
two years ago. You should be thankful, not sarcastic.

Presumably if you don't piss him off he'd be amenable to fixing other things in
this area.

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

--- Comment #15 from Jonathan Gray  ---
Shocking as it may seem Mesa runs on more than just Linux.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

--- Comment #14 from Grazvydas Ignotas  ---
Yes but any affected platforms we actually care about?

Newer gcc should cover some of the cases mentioned in this bug. I think pre-v6
ARM now has 32bit atomics on Linux thanks to a kernel helper.
Others you mentioned are hppa and superh, is anyone actually building mesa for
those?

Otherwise it will just be wasted effort for some dead code that nobody ever
uses.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/fs: Always provide a default LOD of 0 for TXS and TXL

[Anuj Phogat]

On Tue, Apr 4, 2017 at 3:38 PM, Jason Ekstrand  wrote:
> We already provide a default LOD for textureQueryLevels and texture() on
> non-fragment stages.  However, there are more cases where one is needed
> such as textureSize(gsampler2DMS*) in SPIR-V.  Instead of trying to list
> out all of the cases one at a time, just provide the default for all TXS
> and TXL operations.  This fixes a shader validation error in the new
> Sascha deferredmultisampling demo which uses textureSize(gsampler2DMS).
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391
> Cc: Lionel Landwerlin 
> Cc: "13.0 17.0" 
> ---
>  src/intel/compiler/brw_fs_nir.cpp | 18 +-
>  1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/src/intel/compiler/brw_fs_nir.cpp 
> b/src/intel/compiler/brw_fs_nir.cpp
> index bc1ccfb..23cd4b7 100644
> --- a/src/intel/compiler/brw_fs_nir.cpp
> +++ b/src/intel/compiler/brw_fs_nir.cpp
> @@ -4380,15 +4380,6 @@ fs_visitor::nir_emit_texture(const fs_builder , 
> nir_tex_instr *instr)
> srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = 
> brw_imm_d(instr->coord_components);
> srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(lod_components);
>
> -   if (instr->op == nir_texop_query_levels ||
> -   (instr->op == nir_texop_tex && stage != MESA_SHADER_FRAGMENT)) {
> -  /* textureQueryLevels() and texture() are implemented in terms of TXS
> -   * and TXL respectively, so we need to pass a valid LOD argument.
> -   */
> -  assert(srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE);
> -  srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u);
> -   }
> -
> enum opcode opcode;
> switch (instr->op) {
> case nir_texop_tex:
> @@ -4455,6 +4446,15 @@ fs_visitor::nir_emit_texture(const fs_builder , 
> nir_tex_instr *instr)
>unreachable("unknown texture opcode");
> }
>
> +   /* TXS and TXL require a LOD but not everything we implement using those
> +* two opcodes provides one.  Provide a default LOD of 0.
> +*/
> +   if ((opcode == SHADER_OPCODE_TXS_LOGICAL ||
> +opcode == SHADER_OPCODE_TXL_LOGICAL) &&
> +   srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE) {
> +  srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u);
> +   }
> +
> if (instr->op == nir_texop_tg4) {
>if (instr->component == 1 &&
>key_tex->gather_channel_quirk_mask & (1 << texture)) {
> --
> 2.5.0.400.gff86faf
>
> ___
> mesa-stable mailing list
> mesa-sta...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-stable

Looks fine to me.
Reviewed-by: Anuj Phogat 
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2] glsl/blob: handle NULL ptr in blob_write_string/blob_read_string

[Timothy Arceri]

On 05/04/17 02:29, Gregory Hainaut wrote:

Context:
Nouveau uses NULL strings for unnamed parameter of texture gather
offsets opcode.

Fix piglit crashes of the 'texturegatheroffsets' tests on Nouveau

v2: based on Nicolai feedback


Hi Gregory,

Nicolai suggested you change the caller of create a new helper function 
for the case where string can be NULL. e.g blob_write_optional_string()


The change below causes an extra read/write which is not required for 
ever other use of this function. Please create the additional function 
as a wrapper around blob_write_string()


Thanks,
Tim


Adds an extra flag byte that will be null if the string is null.
This way, null strings are handled transparently for Mesa.

Signed-off-by: Gregory Hainaut 
---
 src/compiler/glsl/blob.c | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/src/compiler/glsl/blob.c b/src/compiler/glsl/blob.c
index 769ebf1..b520044 100644
--- a/src/compiler/glsl/blob.c
+++ b/src/compiler/glsl/blob.c
@@ -176,7 +176,18 @@ blob_write_intptr(struct blob *blob, intptr_t value)
 bool
 blob_write_string(struct blob *blob, const char *str)
 {
-   return blob_write_bytes(blob, str, strlen(str) + 1);
+   bool ret = true;
+   const uint8_t flag = str != NULL ? 1 : 0;
+
+   ret = blob_write_bytes(blob, , 1);
+
+   if (!ret)
+  return false;
+
+   if (flag)
+  ret = blob_write_bytes(blob, str, strlen(str) + 1);
+
+   return ret;
 }

 void
@@ -293,8 +304,15 @@ blob_read_string(struct blob_reader *blob)
 {
int size;
char *ret;
+   uint8_t *flag;
uint8_t *nul;

+   flag = (uint8_t *)blob_read_bytes(blob, 1);
+
+   if (flag == NULL || *flag == 0) {
+  return NULL;
+   }
+
/* If we're already at the end, then this is an overrun. */
if (blob->current >= blob->end) {
   blob->overrun = true;


___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2] libgl-xlib: Link with libunwind.

[Rob Clark]

On Tue, Apr 4, 2017 at 6:04 PM, Vinson Lee  wrote:
> Fix linking error.
>
>   CXXLDlibGL.la
> ../../../../src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In 
> function `debug_backtrace_capture':
> src/gallium/auxiliary/util/u_debug_stack.c:59: undefined reference to 
> `_Ux86_64_getcontext'
> src/gallium/auxiliary/util/u_debug_stack.c:60: undefined reference to 
> `_ULx86_64_init_local'
> src/gallium/auxiliary/util/u_debug_stack.c:62: undefined reference to 
> `_ULx86_64_step'
> src/gallium/auxiliary/util/u_debug_stack.c:71: undefined reference to 
> `_ULx86_64_get_proc_info'
> src/gallium/auxiliary/util/u_debug_stack.c:73: undefined reference to 
> `_ULx86_64_get_proc_name'
> src/gallium/auxiliary/util/u_debug_stack.c:65: undefined reference to 
> `_ULx86_64_step'
>
> Fixes: 70c272004f72 ("gallium/util: libunwind support")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100562
> Signed-off-by: Vinson Lee 

thanks,

Reviewed-by: Rob Clark 

> ---
>  src/gallium/targets/libgl-xlib/Makefile.am | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/targets/libgl-xlib/Makefile.am 
> b/src/gallium/targets/libgl-xlib/Makefile.am
> index 6f966c3aebe2..d2fd2ed7b686 100644
> --- a/src/gallium/targets/libgl-xlib/Makefile.am
> +++ b/src/gallium/targets/libgl-xlib/Makefile.am
> @@ -73,7 +73,8 @@ lib@GL_LIB@_la_LIBADD = \
> $(top_builddir)/src/gallium/auxiliary/libgallium.la \
> $(SHARED_GLAPI_LIB) \
> $(GL_LIB_DEPS) \
> -   $(CLOCK_LIB)
> +   $(CLOCK_LIB) \
> +   $(LIBUNWIND_LIBS)
>
>  if HAVE_GALLIUM_LLVM
>  lib@GL_LIB@_la_LIBADD += 
> $(top_builddir)/src/gallium/drivers/llvmpipe/libllvmpipe.la $(LLVM_LIBS)
> --
> 2.9.3
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 8/8] intel/blorp: Use ISL for emitting depth/stencil/hiz

[Jason Ekstrand]

---
 src/intel/blorp/blorp_genX_exec.h | 120 +++---
 1 file changed, 35 insertions(+), 85 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 3791462..e1acb07 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -792,107 +792,57 @@ static void
 blorp_emit_depth_stencil_config(struct blorp_batch *batch,
 const struct blorp_params *params)
 {
-#if GEN_GEN >= 7
-   const uint32_t mocs = 1; /* GEN7_MOCS_L3 */
-#else
-   const uint32_t mocs = 0;
-#endif
-
-   blorp_emit(batch, GENX(3DSTATE_DEPTH_BUFFER), db) {
-#if GEN_GEN >= 7
-  db.DepthWriteEnable = params->depth.enabled;
-  db.StencilWriteEnable = params->stencil.enabled;
-#endif
+   const struct isl_device *isl_dev = batch->blorp->isl_dev;
 
-#if GEN_GEN <= 6
-  db.SeparateStencilBufferEnable = true;
-#endif
+   uint32_t *dw = blorp_emit_dwords(batch, isl_dev->ds.size / 4);
+   if (dw == NULL)
+  return;
 
-  if (params->depth.enabled) {
- db.SurfaceFormat = params->depth_format;
- db.SurfaceType = isl_to_gen_ds_surftype[params->depth.surf.dim];
+   struct isl_depth_stencil_hiz_emit_info info = {
+  .fb_extent = {
+ .width = params->dst.surf.logical_level0_px.width,
+ .height = params->dst.surf.logical_level0_px.height,
+  },
 
-#if GEN_GEN <= 6
- db.TiledSurface = true;
- db.TileWalk = TILEWALK_YMAJOR;
- db.MIPMapLayoutMode = MIPLAYOUT_BELOW;
+#if GEN_GEN >= 7
+  .mocs = 1, /* GEN7_MOCS_L3 */
+#else
+  .mocs = 0,
 #endif
+   };
 
- db.HierarchicalDepthBufferEnable =
-params->depth.aux_usage == ISL_AUX_USAGE_HIZ;
-
- db.Width = params->depth.surf.logical_level0_px.width - 1;
- db.Height = params->depth.surf.logical_level0_px.height - 1;
- db.RenderTargetViewExtent = db.Depth =
-params->depth.view.array_len - 1;
-
- db.LOD = params->depth.view.base_level;
- db.MinimumArrayElement = params->depth.view.base_array_layer;
+   if (params->depth.enabled) {
+  info.view = >depth.view;
+   } else if (params->stencil.enabled) {
+  info.view = >stencil.view;
+   }
 
- db.SurfacePitch = params->depth.surf.row_pitch - 1;
-#if GEN_GEN >= 8
- db.SurfaceQPitch =
-isl_surf_get_array_pitch_el_rows(>depth.surf) >> 2,
-#endif
+   if (params->depth.enabled) {
+  info.depth_surf = >depth.surf;
 
- db.SurfaceBaseAddress = params->depth.addr;
- db.DepthBufferMOCS = mocs;
-  } else if (params->stencil.enabled) {
- db.SurfaceFormat = D32_FLOAT;
- db.SurfaceType = isl_to_gen_ds_surftype[params->stencil.surf.dim];
+  blorp_emit_reloc(batch, dw + isl_dev->ds.depth_offset / 4,
+   params->depth.addr, 0);
 
- db.Width = params->stencil.surf.logical_level0_px.width - 1;
- db.Height = params->stencil.surf.logical_level0_px.height - 1;
- db.RenderTargetViewExtent = db.Depth =
-params->stencil.view.array_len - 1;
+  info.hiz_usage = params->depth.aux_usage;
+  if (info.hiz_usage == ISL_AUX_USAGE_HIZ) {
+ info.hiz_surf = >depth.aux_surf;
+ info.hiz_usage = ISL_AUX_USAGE_HIZ;
 
- db.LOD = params->stencil.view.base_level;
- db.MinimumArrayElement = params->stencil.view.base_array_layer;
-  } else {
- db.SurfaceType = SURFTYPE_NULL;
- db.SurfaceFormat = D32_FLOAT;
-  }
-   }
+ blorp_emit_reloc(batch, dw + isl_dev->ds.hiz_offset / 4,
+  params->depth.aux_addr, 0);
 
-   blorp_emit(batch, GENX(3DSTATE_HIER_DEPTH_BUFFER), hiz) {
-  if (params->depth.aux_usage == ISL_AUX_USAGE_HIZ) {
- hiz.SurfacePitch = params->depth.aux_surf.row_pitch - 1;
- hiz.SurfaceBaseAddress = params->depth.aux_addr;
- hiz.HierarchicalDepthBufferMOCS = mocs;
-#if GEN_GEN >= 8
- hiz.SurfaceQPitch =
-isl_surf_get_array_pitch_sa_rows(>depth.aux_surf) >> 2;
-#endif
+ info.depth_clear_value = params->depth.clear_color.u32[0];
   }
}
 
-   blorp_emit(batch, GENX(3DSTATE_STENCIL_BUFFER), sb) {
-  if (params->stencil.enabled) {
-#if GEN_GEN >= 8 || GEN_IS_HASWELL
- sb.StencilBufferEnable = true;
-#endif
-
- sb.SurfacePitch = params->stencil.surf.row_pitch - 1,
-#if GEN_GEN >= 8
- sb.SurfaceQPitch =
-isl_surf_get_array_pitch_el_rows(>stencil.surf) >> 2,
-#endif
+   if (params->stencil.enabled) {
+  info.stencil_surf = >stencil.surf;
 
- sb.SurfaceBaseAddress = params->stencil.addr;
- sb.StencilBufferMOCS = batch->blorp->mocs.tex;
-  }
+  blorp_emit_reloc(batch, dw + isl_dev->ds.stencil_offset / 4,
+   params->stencil.addr, 0);
}
 
-   /* 3DSTATE_CLEAR_PARAMS
-*
-* From the Sandybridge PRM, Volume 2, Part 1, Section 

[Mesa-dev] [PATCH 6/8] intel/isl: Add support for emitting depth/stencil/hiz

[Jason Ekstrand]

---
 src/intel/Makefile.sources |   7 ++
 src/intel/isl/isl.c|  93 
 src/intel/isl/isl.h|  82 ++
 src/intel/isl/isl_emit_depth_stencil.c | 189 +
 src/intel/isl/isl_priv.h   |  28 +
 5 files changed, 399 insertions(+)
 create mode 100644 src/intel/isl/isl_emit_depth_stencil.c

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index c568916..df8c868 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -150,32 +150,39 @@ ISL_FILES = \
 ISL_GEN4_FILES = \
isl/isl_gen4.c \
isl/isl_gen4.h \
+   isl/isl_emit_depth_stencil.c \
isl/isl_surface_state.c
 
 ISL_GEN5_FILES = \
+   isl/isl_emit_depth_stencil.c \
isl/isl_surface_state.c
 
 ISL_GEN6_FILES = \
isl/isl_gen6.c \
isl/isl_gen6.h \
+   isl/isl_emit_depth_stencil.c \
isl/isl_surface_state.c
 
 ISL_GEN7_FILES = \
isl/isl_gen7.c \
isl/isl_gen7.h \
+   isl/isl_emit_depth_stencil.c \
isl/isl_surface_state.c
 
 ISL_GEN75_FILES = \
+   isl/isl_emit_depth_stencil.c \
isl/isl_surface_state.c
 
 ISL_GEN8_FILES = \
isl/isl_gen8.c \
isl/isl_gen8.h \
+   isl/isl_emit_depth_stencil.c \
isl/isl_surface_state.c
 
 ISL_GEN9_FILES = \
isl/isl_gen9.c \
isl/isl_gen9.h \
+   isl/isl_emit_depth_stencil.c \
isl/isl_surface_state.c
 
 ISL_GENERATED_FILES = \
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 4e89991..f89f351 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -83,6 +83,32 @@ isl_device_init(struct isl_device *dev,
 */
dev->ss.aux_addr_offset =
   (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info) & ~31) / 8;
+
+   dev->ds.size =
+  _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
+  _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
+  _3DSTATE_HIER_DEPTH_BUFFER_length(info) * 4 +
+  _3DSTATE_CLEAR_PARAMS_length(info) * 4;
+
+   assert(_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+   dev->ds.depth_offset =
+  _3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
+
+   if (info->has_hiz_and_separate_stencil) {
+  assert(_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) % 8 == 0);
+  dev->ds.stencil_offset =
+ _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(info) / 8;
+
+  assert(_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) % 8 == 
0);
+  dev->ds.hiz_offset =
+ _3DSTATE_DEPTH_BUFFER_length(info) * 4 +
+ _3DSTATE_STENCIL_BUFFER_length(info) * 4 +
+ _3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(info) / 8;
+   } else {
+  dev->ds.stencil_offset = 0;
+  dev->ds.hiz_offset = 0;
+   }
 }
 
 /**
@@ -1684,6 +1710,73 @@ isl_buffer_fill_state_s(const struct isl_device *dev, 
void *state,
}
 }
 
+void
+isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
+ const struct isl_depth_stencil_hiz_emit_info 
*restrict info)
+{
+   if (info->depth_surf && info->stencil_surf) {
+  if (!dev->info->has_hiz_and_separate_stencil) {
+ assert(info->depth_surf == info->stencil_surf);
+ assert(info->depth_address == info->stencil_address);
+  }
+  assert(info->depth_surf->dim == info->stencil_surf->dim);
+   }
+
+   if (info->depth_surf) {
+  assert((info->depth_surf->usage & ISL_SURF_USAGE_DEPTH_BIT));
+  if (info->depth_surf->dim == ISL_SURF_DIM_3D) {
+ assert(info->view->base_array_layer + info->view->array_len <=
+info->depth_surf->logical_level0_px.depth);
+  } else {
+ assert(info->view->base_array_layer + info->view->array_len <=
+info->depth_surf->logical_level0_px.array_len);
+  }
+   }
+
+   if (info->stencil_surf) {
+  assert((info->stencil_surf->usage & ISL_SURF_USAGE_STENCIL_BIT));
+  if (info->stencil_surf->dim == ISL_SURF_DIM_3D) {
+ assert(info->view->base_array_layer + info->view->array_len <=
+info->stencil_surf->logical_level0_px.depth);
+  } else {
+ assert(info->view->base_array_layer + info->view->array_len <=
+info->stencil_surf->logical_level0_px.array_len);
+  }
+   }
+
+   switch (ISL_DEV_GEN(dev)) {
+   case 4:
+  if (ISL_DEV_IS_G4X(dev)) {
+ /* G45 surface state is the same as gen5 */
+ isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info);
+  } else {
+ isl_gen4_emit_depth_stencil_hiz_s(dev, batch, info);
+  }
+  break;
+   case 5:
+  isl_gen5_emit_depth_stencil_hiz_s(dev, batch, info);
+  break;
+   case 6:
+  isl_gen6_emit_depth_stencil_hiz_s(dev, batch, info);
+  break;
+   case 7:
+  if (ISL_DEV_IS_HASWELL(dev)) {
+ isl_gen75_emit_depth_stencil_hiz_s(dev, batch, info);
+ 

[Mesa-dev] [PATCH 7/8] anv: Use ISL for emitting depth/stencil/hiz

[Jason Ekstrand]

---
 src/intel/vulkan/genX_cmd_buffer.c | 215 +++--
 1 file changed, 37 insertions(+), 178 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 1ce549a..4e519cd 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2215,51 +2215,6 @@ genX(cmd_buffer_emit_gen7_depth_flush)(struct 
anv_cmd_buffer *cmd_buffer)
}
 }
 
-static uint32_t
-depth_stencil_surface_type(enum isl_surf_dim dim)
-{
-   switch (dim) {
-   case ISL_SURF_DIM_1D:
-  if (GEN_GEN >= 9) {
- /* From the Sky Lake PRM, 3DSTATAE_DEPTH_BUFFER::SurfaceType
-  *
-  *Programming Notes:
-  *The Surface Type of the depth buffer must be the same as the
-  *Surface Type of the render target(s) (defined in
-  *SURFACE_STATE), unless either the depth buffer or render
-  *targets are SURFTYPE_NULL (see exception below for SKL).  1D
-  *surface type not allowed for depth surface and stencil surface.
-  *
-  *Workaround:
-  *If depth/stencil is enabled with 1D render target,
-  *depth/stencil surface type needs to be set to 2D surface type
-  *and height set to 1. Depth will use (legacy) TileY and stencil
-  *will use TileW. For this case only, the Surface Type of the
-  *depth buffer can be 2D while the Surface Type of the render
-  *target(s) are 1D, representing an exception to a programming
-  *note above.
-  */
- return SURFTYPE_2D;
-  } else {
- return SURFTYPE_1D;
-  }
-   case ISL_SURF_DIM_2D:
-  return SURFTYPE_2D;
-   case ISL_SURF_DIM_3D:
-  if (GEN_GEN >= 9) {
- /* The Sky Lake docs list the value for 3D as "Reserved".  However,
-  * they have the exact same layout as 2D arrays on gen9+, so we can
-  * just use 2D here.
-  */
- return SURFTYPE_2D;
-  } else {
- return SURFTYPE_3D;
-  }
-   default:
-  unreachable("Invalid surface dimension");
-   }
-}
-
 static void
 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
 {
@@ -2268,155 +2223,59 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer 
*cmd_buffer)
const struct anv_image_view *iview =
   anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
const struct anv_image *image = iview ? iview->image : NULL;
-   const bool has_depth = image && (image->aspects & 
VK_IMAGE_ASPECT_DEPTH_BIT);
-   const uint32_t ds = 
cmd_buffer->state.subpass->depth_stencil_attachment.attachment;
-   const bool has_hiz = image != NULL &&
-  cmd_buffer->state.attachments[ds].aux_usage == ISL_AUX_USAGE_HIZ;
-   const bool has_stencil =
-  image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
-
-   cmd_buffer->state.hiz_enabled = has_hiz;
 
/* FIXME: Width and Height are wrong */
 
genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer);
 
-   /* Emit 3DSTATE_DEPTH_BUFFER */
-   if (has_depth) {
-  anv_batch_emit(_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER), db) {
- db.SurfaceType   =
-depth_stencil_surface_type(image->depth_surface.isl.dim);
- db.DepthWriteEnable  = true;
- db.StencilWriteEnable= has_stencil;
- db.HierarchicalDepthBufferEnable = has_hiz;
-
- db.SurfaceFormat = isl_surf_get_depth_format(>isl_dev,
-  
>depth_surface.isl);
-
- db.SurfaceBaseAddress = (struct anv_address) {
-.bo = image->bo,
-.offset = image->offset + image->depth_surface.offset,
- };
- db.DepthBufferObjectControlState = GENX(MOCS);
+   uint32_t *dw = anv_batch_emit_dwords(_buffer->batch,
+device->isl_dev.ds.size / 4);
+   if (dw == NULL)
+  return;
 
- db.SurfacePitch = image->depth_surface.isl.row_pitch - 1;
- db.Height   = image->extent.height - 1;
- db.Width= image->extent.width - 1;
- db.LOD  = iview->isl.base_level;
- db.MinimumArrayElement  = iview->isl.base_array_layer;
+   struct isl_depth_stencil_hiz_emit_info info = {
+  .fb_extent = isl_extent2d(fb->width, fb->height),
+  .mocs = device->default_mocs,
+   };
 
- assert(image->depth_surface.isl.dim != ISL_SURF_DIM_3D);
- db.Depth =
- db.RenderTargetViewExtent = iview->isl.array_len - 1;
+   if (iview)
+  info.view = >isl;
 
-#if GEN_GEN >= 8
- db.SurfaceQPitch =
-isl_surf_get_array_pitch_el_rows(>depth_surface.isl) >> 2;
-#endif
-  }
-   } else {
-  /* Even when no depth buffer is present, the hardware requires that
-   * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
-   *
-   *If a null depth 

[Mesa-dev] [PATCH 5/8] intel/isl: Use genx_bits.h instead of a hand-rolled table

[Jason Ekstrand]

This gets rid of one piece of ugliness with the way ISL handles surface
emitting surface states.  I've never liked that hand-rolled table but it
was the best we had at the time.
---
 src/intel/isl/isl.c | 31 +--
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index c7072d0..4e89991 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -48,20 +48,6 @@ __isl_finishme(const char *file, int line, const char *fmt, 
...)
fprintf(stderr, "%s:%d: FINISHME: %s\n", file, line, buf);
 }
 
-static const struct {
-   uint8_t size;
-   uint8_t align;
-   uint8_t addr_offset;
-   uint8_t aux_addr_offset;
-} ss_infos[] = {
-   [4] = {24, 32,  4},
-   [5] = {24, 32,  4},
-   [6] = {24, 32,  4},
-   [7] = {32, 32,  4, 24},
-   [8] = {64, 64, 32, 40},
-   [9] = {64, 64, 32, 40},
-};
-
 void
 isl_device_init(struct isl_device *dev,
 const struct gen_device_info *info,
@@ -84,10 +70,19 @@ isl_device_init(struct isl_device *dev,
if (info->must_use_separate_stencil)
   assert(ISL_DEV_USE_SEPARATE_STENCIL(dev));
 
-   dev->ss.size = ss_infos[ISL_DEV_GEN(dev)].size;
-   dev->ss.align = ss_infos[ISL_DEV_GEN(dev)].align;
-   dev->ss.addr_offset = ss_infos[ISL_DEV_GEN(dev)].addr_offset;
-   dev->ss.aux_addr_offset = ss_infos[ISL_DEV_GEN(dev)].aux_addr_offset;
+   dev->ss.size = RENDER_SURFACE_STATE_length(info) * 4;
+   dev->ss.align = isl_align(dev->ss.size, 32);
+
+   assert(RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) % 8 == 0);
+   dev->ss.addr_offset =
+  RENDER_SURFACE_STATE_SurfaceBaseAddress_start(info) / 8;
+
+   /* The "Auxiliary Surface Base Address" field starts a bit higher up
+* because the bottom 12 bits are used for other things.  Round down to
+* the nearest dword before.
+*/
+   dev->ss.aux_addr_offset =
+  (RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(info) & ~31) / 8;
 }
 
 /**
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 4/8] intel/genxml/bits: Emit per-container _length helpers

[Jason Ekstrand]

---
 src/intel/genxml/gen_bits_header.py | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/src/intel/genxml/gen_bits_header.py 
b/src/intel/genxml/gen_bits_header.py
index fc31baa..ac8ec4c 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -107,6 +107,11 @@ ${item.token_name}_${prop}(const struct gen_device_info 
*devinfo)
 extern "C" {
 #endif
 % for _, container in sorted(containers.iteritems(), key=itemgetter(0)):
+
+/* ${container.name} */
+
+${emit_per_gen_prop_func(container, 'length')}
+
 % for _, field in sorted(container.fields.iteritems(), key=itemgetter(0)):
 
 /* ${container.name}::${field.name} */
@@ -191,8 +196,15 @@ class Container(object):
 
 def __init__(self, name):
 self.name = name
+self.token_name = safe_name(name)
+self.length_by_gen = {}
 self.fields = {}
 
+def add_gen(self, gen, xml_attrs):
+assert isinstance(gen, Gen)
+if 'length' in xml_attrs:
+self.length_by_gen[gen] = xml_attrs['length']
+
 def get_field(self, field_name, create=False):
 if field_name not in self.fields:
 if create:
@@ -201,6 +213,27 @@ class Container(object):
 return None
 return self.fields[field_name]
 
+def has_prop(self, prop):
+if prop == 'length':
+return bool(self.length_by_gen)
+else:
+raise ValueError('Invalid property: "{0}"'.format(prop))
+
+def iter_prop(self, prop):
+if prop == 'length':
+return self.length_by_gen.iteritems()
+else:
+raise ValueError('Invalid property: "{0}"'.format(prop))
+
+def get_prop(self, prop, gen):
+if not isinstance(gen, Gen):
+gen = Gen(gen)
+
+if prop == 'length':
+return self.length_by_gen.get(gen, 0)
+else:
+raise ValueError('Invalid property: "{0}"'.format(prop))
+
 class Field(object):
 
 def __init__(self, container, name):
@@ -277,6 +310,7 @@ class XmlParser(object):
 if name not in self.containers:
 self.containers[name] = Container(name)
 self.container = self.containers[name]
+self.container.add_gen(self.gen, attrs)
 
 def start_field(self, attrs):
 if self.container is None:
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 3/8] intel/genxml/bits: Emit per-field _start helpers

[Jason Ekstrand]

---
 src/intel/genxml/gen_bits_header.py | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/intel/genxml/gen_bits_header.py 
b/src/intel/genxml/gen_bits_header.py
index cfe2a89..fc31baa 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -113,6 +113,8 @@ extern "C" {
 
 ${emit_per_gen_prop_func(field, 'bits')}
 
+${emit_per_gen_prop_func(field, 'start')}
+
 % endfor
 % endfor
 
@@ -205,11 +207,13 @@ class Field(object):
 self.name = name
 self.token_name = safe_name('_'.join([container.name, self.name]))
 self.bits_by_gen = {}
+self.start_by_gen = {}
 
 def add_gen(self, gen, xml_attrs):
 assert isinstance(gen, Gen)
 start = int(xml_attrs['start'])
 end = int(xml_attrs['end'])
+self.start_by_gen[gen] = start
 self.bits_by_gen[gen] = 1 + end - start
 
 def has_prop(self, prop):
@@ -218,6 +222,8 @@ class Field(object):
 def iter_prop(self, prop):
 if prop == 'bits':
 return self.bits_by_gen.iteritems()
+elif prop == 'start':
+return self.start_by_gen.iteritems()
 else:
 raise ValueError('Invalid property: "{0}"'.format(prop))
 
@@ -227,6 +233,8 @@ class Field(object):
 
 if prop == 'bits':
 return self.bits_by_gen.get(gen, 0)
+elif prop == 'start':
+return self.start_by_gen.get(gen, 0)
 else:
 raise ValueError('Invalid property: "{0}"'.format(prop))
 
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 0/8] intel/isl: Emit depth/stencil/hiz packets

[Jason Ekstrand]

This little series adds support to ISL for emitting the packets required
for depth and stencil buffers:

 - 3DSTATE_DEPTH_BUFFER
 - 3DSTATE_STENCIL_BUFFER
 - 3DSTATE_HIER_DEPTH_BUFFER
 - 3DSTATE_CLEAR_PARAMS

The approach taken here is to have a single function which emits all four
commands in one go.  The reasoning behind doing it this way is that the
four packets are very closely intertwined.  For instance,
3DSTATE_STENCIL_BUFFER and 3DSTATE_HIER_DEPTH_BUFFER do not have any extent
fields, they rely on 3DSTATE_DEPTH_BUFFER for that information.  Also, the
HiZ enable bit is in 3DSTATE_DEPTH_BUFFER but the details about the HiZ
buffer are in 3DSTATE_HIER_DEPTH_BUFFER.

The alternate approach, which Topi tried in some patches of his is to
re-use the isl_surf_state_fill_info struct that we use for filling out
RENDER_SURFACE_STATE.  However, this requires unlinking depth and stencil
(at the very least) which is problematic in the case where you have stencil
but no depth.

Jason Ekstrand (8):
  genxml/bits: Refactor to add a container class
  genxml/bits: Pull the function emit code into a helper block
  genxml/bits: Emit per-field _start helpers
  genxml/bits: Emit per-container _length helpers
  isl: Use genx_bits.h instead of a hand-rolled table
  isl: Add support for emitting depth/stencil/hiz
  anv: Use ISL for emitting depth/stencil/hiz
  intel/blorp: Use ISL for emitting depth/stencil/hiz

 src/intel/Makefile.sources |   7 ++
 src/intel/blorp/blorp_genX_exec.h  | 120 ++
 src/intel/genxml/gen_bits_header.py| 159 +---
 src/intel/isl/isl.c| 124 ---
 src/intel/isl/isl.h|  82 +
 src/intel/isl/isl_emit_depth_stencil.c | 189 +
 src/intel/isl/isl_priv.h   |  28 +
 src/intel/vulkan/genX_cmd_buffer.c | 215 ++---
 8 files changed, 601 insertions(+), 323 deletions(-)
 create mode 100644 src/intel/isl/isl_emit_depth_stencil.c

-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/8] intel/genxml/bits: Pull the function emit code into a helper block

[Jason Ekstrand]

The helper block is extremely general.  It takes an string property name
and an object that supports three methods: has_prop, iter_prop, and
get_prop.  This way we can easily generalize it to emit more different
types of getter functions.
---
 src/intel/genxml/gen_bits_header.py | 69 +++--
 1 file changed, 43 insertions(+), 26 deletions(-)

diff --git a/src/intel/genxml/gen_bits_header.py 
b/src/intel/genxml/gen_bits_header.py
index 9a89da4..cfe2a89 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -70,41 +70,48 @@ from operator import itemgetter
 #include "common/gen_device_info.h"
 #include "util/macros.h"
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-% for _, container in sorted(containers.iteritems(), key=itemgetter(0)):
-% for _, field in sorted(container.fields.iteritems(), key=itemgetter(0)):
-
-/* ${container.name}::${field.name} */
-% for gen, bits in sorted(field.bits_by_gen.iteritems(), reverse=True):
-#define ${gen.prefix(field.token_name, padded=True)}${bits}
+<%def name="emit_per_gen_prop_func(item, prop)">
+%if item.has_prop(prop):
+% for gen, value in sorted(item.iter_prop(prop), reverse=True):
+#define ${gen.prefix(item.token_name)}_${prop}  ${value}
 % endfor
 
 static inline uint32_t ATTRIBUTE_PURE
-${field.token_name}(const struct gen_device_info *devinfo)
+${item.token_name}_${prop}(const struct gen_device_info *devinfo)
 {
switch (devinfo->gen) {
-   case 9: return ${field.bits(9)};
-   case 8: return ${field.bits(8)};
+   case 9: return ${item.get_prop(prop, 9)};
+   case 8: return ${item.get_prop(prop, 8)};
case 7:
   if (devinfo->is_haswell) {
- return ${field.bits(7.5)};
+ return ${item.get_prop(prop, 7.5)};
   } else {
- return ${field.bits(7)};
+ return ${item.get_prop(prop, 7)};
   }
-   case 6: return ${field.bits(6)};
-   case 5: return ${field.bits(5)};
+   case 6: return ${item.get_prop(prop, 6)};
+   case 5: return ${item.get_prop(prop, 5)};
case 4:
   if (devinfo->is_g4x) {
- return ${field.bits(4.5)};
+ return ${item.get_prop(prop, 4.5)};
   } else {
- return ${field.bits(4)};
+ return ${item.get_prop(prop, 4)};
   }
default:
   unreachable("Invalid hardware generation");
}
 }
+%endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+% for _, container in sorted(containers.iteritems(), key=itemgetter(0)):
+% for _, field in sorted(container.fields.iteritems(), key=itemgetter(0)):
+
+/* ${container.name}::${field.name} */
+
+${emit_per_gen_prop_func(field, 'bits')}
 
 % endfor
 % endfor
@@ -167,19 +174,16 @@ class Gen(object):
 def __eq__(self, other):
 return self.tenx == other.tenx
 
-def prefix(self, token, padded=False):
+def prefix(self, token):
 gen = self.tenx
-pad = ''
 
 if gen % 10 == 0:
 gen //= 10
-if padded:
-pad = ' '
 
 if token[0] == '_':
 token = token[1:]
 
-return 'GEN{}_{}{}'.format(gen, token, pad)
+return 'GEN{}_{}'.format(gen, token)
 
 class Container(object):
 
@@ -199,7 +203,7 @@ class Field(object):
 
 def __init__(self, container, name):
 self.name = name
-self.token_name = safe_name('_'.join([container.name, self.name, 
'bits']))
+self.token_name = safe_name('_'.join([container.name, self.name]))
 self.bits_by_gen = {}
 
 def add_gen(self, gen, xml_attrs):
@@ -208,10 +212,23 @@ class Field(object):
 end = int(xml_attrs['end'])
 self.bits_by_gen[gen] = 1 + end - start
 
-def bits(self, gen):
+def has_prop(self, prop):
+return True
+
+def iter_prop(self, prop):
+if prop == 'bits':
+return self.bits_by_gen.iteritems()
+else:
+raise ValueError('Invalid property: "{0}"'.format(prop))
+
+def get_prop(self, prop, gen):
 if not isinstance(gen, Gen):
 gen = Gen(gen)
-return self.bits_by_gen.get(gen, 0)
+
+if prop == 'bits':
+return self.bits_by_gen.get(gen, 0)
+else:
+raise ValueError('Invalid property: "{0}"'.format(prop))
 
 class XmlParser(object):
 
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 1/8] intel/genxml/bits: Refactor to add a container class

[Jason Ekstrand]

---
 src/intel/genxml/gen_bits_header.py | 56 -
 1 file changed, 36 insertions(+), 20 deletions(-)

diff --git a/src/intel/genxml/gen_bits_header.py 
b/src/intel/genxml/gen_bits_header.py
index 808e6cf..9a89da4 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -73,9 +73,10 @@ from operator import itemgetter
 #ifdef __cplusplus
 extern "C" {
 #endif
-% for _, field in sorted(fields.iteritems(), key=itemgetter(0)):
+% for _, container in sorted(containers.iteritems(), key=itemgetter(0)):
+% for _, field in sorted(container.fields.iteritems(), key=itemgetter(0)):
 
-/* ${field.container_name}::${field.name} */
+/* ${container.name}::${field.name} */
 % for gen, bits in sorted(field.bits_by_gen.iteritems(), reverse=True):
 #define ${gen.prefix(field.token_name, padded=True)}${bits}
 % endfor
@@ -104,6 +105,8 @@ ${field.token_name}(const struct gen_device_info *devinfo)
   unreachable("Invalid hardware generation");
}
 }
+
+% endfor
 % endfor
 
 #ifdef __cplusplus
@@ -178,12 +181,25 @@ class Gen(object):
 
 return 'GEN{}_{}{}'.format(gen, token, pad)
 
+class Container(object):
+
+def __init__(self, name):
+self.name = name
+self.fields = {}
+
+def get_field(self, field_name, create=False):
+if field_name not in self.fields:
+if create:
+self.fields[field_name] = Field(self, field_name)
+else:
+return None
+return self.fields[field_name]
+
 class Field(object):
 
-def __init__(self, container_name, name):
-self.container_name = container_name
+def __init__(self, container, name):
 self.name = name
-self.token_name = safe_name('_'.join([self.container_name, self.name, 
'bits']))
+self.token_name = safe_name('_'.join([container.name, self.name, 
'bits']))
 self.bits_by_gen = {}
 
 def add_gen(self, gen, xml_attrs):
@@ -199,14 +215,14 @@ class Field(object):
 
 class XmlParser(object):
 
-def __init__(self, fields):
+def __init__(self, containers):
 self.parser = xml.parsers.expat.ParserCreate()
 self.parser.StartElementHandler = self.start_element
 self.parser.EndElementHandler = self.end_element
 
 self.gen = None
-self.container_name = None
-self.fields = fields
+self.containers = containers
+self.container = None
 
 def parse(self, filename):
 with open(filename) as f:
@@ -226,26 +242,26 @@ class XmlParser(object):
 if name == 'genxml':
 self.gen = None
 elif name in ('instruction', 'struct', 'register'):
-self.container_name = None
+self.container = None
 else:
 pass
 
 def start_container(self, attrs):
-assert self.container_name is None
-self.container_name = attrs['name']
+assert self.container is None
+name = attrs['name']
+if name not in self.containers:
+self.containers[name] = Container(name)
+self.container = self.containers[name]
 
 def start_field(self, attrs):
-if self.container_name is None:
+if self.container is None:
 return
 
 field_name = attrs.get('name', None)
 if not field_name:
 return
 
-key = (self.container_name, field_name)
-if key not in self.fields:
-self.fields[key] = Field(self.container_name, field_name)
-self.fields[key].add_gen(self.gen, attrs)
+self.container.get_field(field_name, True).add_gen(self.gen, attrs)
 
 def parse_args():
 p = argparse.ArgumentParser()
@@ -268,14 +284,14 @@ def parse_args():
 def main():
 pargs = parse_args()
 
-# Maps (container_name, field_name) => Field
-fields = {}
+# Maps name => Container
+containers = {}
 
 for source in pargs.xml_sources:
-XmlParser(fields).parse(source)
+XmlParser(containers).parse(source)
 
 with open(pargs.output, 'wb') as f:
-f.write(TEMPLATE.render(fields=fields, guard=pargs.cpp_guard))
+f.write(TEMPLATE.render(containers=containers, guard=pargs.cpp_guard))
 
 if __name__ == '__main__':
 main()
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] i965/fs: Always provide a default LOD of 0 for TXS and TXL

[Jason Ekstrand]

We already provide a default LOD for textureQueryLevels and texture() on
non-fragment stages.  However, there are more cases where one is needed
such as textureSize(gsampler2DMS*) in SPIR-V.  Instead of trying to list
out all of the cases one at a time, just provide the default for all TXS
and TXL operations.  This fixes a shader validation error in the new
Sascha deferredmultisampling demo which uses textureSize(gsampler2DMS).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391
Cc: Lionel Landwerlin 
Cc: "13.0 17.0" 
---
 src/intel/compiler/brw_fs_nir.cpp | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index bc1ccfb..23cd4b7 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4380,15 +4380,6 @@ fs_visitor::nir_emit_texture(const fs_builder , 
nir_tex_instr *instr)
srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(instr->coord_components);
srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(lod_components);
 
-   if (instr->op == nir_texop_query_levels ||
-   (instr->op == nir_texop_tex && stage != MESA_SHADER_FRAGMENT)) {
-  /* textureQueryLevels() and texture() are implemented in terms of TXS
-   * and TXL respectively, so we need to pass a valid LOD argument.
-   */
-  assert(srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE);
-  srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u);
-   }
-
enum opcode opcode;
switch (instr->op) {
case nir_texop_tex:
@@ -4455,6 +4446,15 @@ fs_visitor::nir_emit_texture(const fs_builder , 
nir_tex_instr *instr)
   unreachable("unknown texture opcode");
}
 
+   /* TXS and TXL require a LOD but not everything we implement using those
+* two opcodes provides one.  Provide a default LOD of 0.
+*/
+   if ((opcode == SHADER_OPCODE_TXS_LOGICAL ||
+opcode == SHADER_OPCODE_TXL_LOGICAL) &&
+   srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE) {
+  srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u);
+   }
+
if (instr->op == nir_texop_tg4) {
   if (instr->component == 1 &&
   key_tex->gather_channel_quirk_mask & (1 << texture)) {
-- 
2.5.0.400.gff86faf

___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] anv/pipeline: Properly handle unset gl_Layer and gl_ViewportIndex

[Kenneth Graunke]

On Tuesday, April 4, 2017 11:12:32 AM PDT Jason Ekstrand wrote:
> When the shader does not set one of these values, they are supposed to
> get a default value of 0.  We have hardware bits in 3DSTATE_CLIP for
> this but haven't been setting them.  This fixes the intermittent failure
> of dEQP-VK.geometry.layered.3d.render_to_default_layer.
> 
> Cc: "13.0 17.0" 
> ---
>  src/intel/vulkan/genX_pipeline.c | 27 ---
>  1 file changed, 24 insertions(+), 3 deletions(-)

Reviewed-by: Kenneth Graunke 


signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] gallium/hud: set the dump file streams to line buffered

[Julien Isorce]

I confirm it works, awesome!  Thx!
Should you check that fopen succeeded  ? because I think setvbuf would
crash otherwise.
That's said:
Tested-by: Julien Isorce 

On 4 April 2017 at 21:52, Edmondo Tommasina 
wrote:

> Flush the HUD value streams to the dump files after every newline.
> ---
>  src/gallium/auxiliary/hud/hud_context.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/gallium/auxiliary/hud/hud_context.c
> b/src/gallium/auxiliary/hud/hud_context.c
> index 29ef9eee31..633e3650cc 100644
> --- a/src/gallium/auxiliary/hud/hud_context.c
> +++ b/src/gallium/auxiliary/hud/hud_context.c
> @@ -972,6 +972,7 @@ hud_graph_set_dump_file(struct hud_graph *gr)
>   strcat(dump_file, "/");
>   strcat_without_spaces(dump_file, gr->name);
>   gr->fd = fopen(dump_file, "w+");
> + setvbuf(gr->fd, NULL, _IOLBF, 0);
>   free(dump_file);
>}
> }
> --
> 2.11.0
>
> ___
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] anv: Check for device loss at the end of WaitForFences

[Kenneth Graunke]

On Tuesday, March 28, 2017 2:39:53 PM PDT Jason Ekstrand wrote:
> It's possible that the device could have been lost while we were
> waiting.  We should let the user know if this has happened.
> ---
>  src/intel/vulkan/anv_device.c | 19 ++-
>  1 file changed, 14 insertions(+), 5 deletions(-)

Reviewed-by: Kenneth Graunke 


signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 2/2] anv: Query the kernel for reset status

[Kenneth Graunke]

On Wednesday, March 29, 2017 12:37:50 PM PDT Jason Ekstrand wrote:
> When a client causes a GPU hang (or experiences issues due to a hang in
> another client) we want to let it know as soon as possible.  In
> particular, if it submits work with a fence and calls vkWaitForFences or
> vkQueueQaitIdle and it returns VK_SUCCESS, then the client should be
> able to trust the results of that rendering.  In order to provide this
> guarantee, we have to ask the kernel for context status in a few key
> locations.
> ---
>  src/intel/vulkan/anv_device.c  | 114 
> +
>  src/intel/vulkan/anv_gem.c |  17 ++
>  src/intel/vulkan/anv_private.h |   5 ++
>  src/intel/vulkan/genX_query.c  |  11 ++--
>  4 files changed, 107 insertions(+), 40 deletions(-)

Reviewed-by: Kenneth Graunke 


signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

Jonathan Gray  changed:

   What|Removed |Added

 Status|RESOLVED|REOPENED
 Resolution|FIXED   |---

--- Comment #13 from Jonathan Gray  ---
This is still not handled for 32 bit atomics.

-- 
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH V2] util/disk_cache: compress individual cache entries

[Brian Paul]

On 03/04/2017 07:12 AM, Emil Velikov wrote:

On 2 March 2017 at 21:52, Timothy Arceri  wrote:


On 03/03/17 01:49, Emil Velikov wrote:


Hi Tim,

On 2 March 2017 at 01:36, Timothy Arceri  wrote:


This reduces the cache size for Deus Ex from ~160M to ~30M for
radeonsi.

I'm also seeing the following improvements in minimum fps in the
Shadow of Mordor benchmark:

no-cache:~10fps
with-cache-no-compression:   ~15fps
with-cache-and-compression:  ~20fps

Note the with cache results are from the second run after closing
and opening the game to avoid the in-memory cache.

Since we only really care about decompression I went with
Z_BEST_COMPRESSION as suggested on irc by Steinar H. Gunderson
who has benchmarked decompression speeds.


Attempting to side-step the "which compression is best" topic, I'll
just mention:
zlib has been around for a long time than many others so,
a) chances are smaller that vendors that ship their own, but even if they
do
b) the API should be stable across the system and bundled one.

If not we can reconsider if things get hairy ;-)

A couple of small suggestions below.



+ZLIB_REQUIRED=1.2.8


Any particular reason behind this version - afaict it's released in
2013 and I'm wondering if some distros may be slow/missing it.



It's what's shipped with Fedora and therefore what I tested with. If distros
are lagging behind I don't think this is a problem we need to be concerned
with, it may prompt them to upgrade which I don't think is a bad thing.


I was thinking about Debian and friends, which tend to be slower than others.

From what I can tell they rarely consider external factors as a reason

to update.

That aside, they have 1.2.7 for "oldstable" and 1.2.8 for everything
else so everything's fine.


FWIW, RHEL 7.2 (haven't looked at 7.3 yet) only has zlib 1.2.7.  Mesa 
builds fine with 1.2.7 if I override ZLIB_CFLAGS and ZLIB_LIBS, but I 
haven't tested the shader cache.


Can we lower the check to 1.2.7?  Otherwise, I guess I could hack around 
it in our build script.


-Brian


___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [Bug 93089] mesa fails to check for gcc atomic primitives before using them

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=93089

Grazvydas Ignotas  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #12 from Grazvydas Ignotas  ---
Fixes (partial at least) pushed as a6a38a038bd62e6d9558905f00bef81b5e7e6fcc and
b384c23b9e804916f125354e06c735bd3bb22811. Please reopen if there is still a
problem and specify the environment (architecture, compiler version, any extra
flags).

-- 
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the bug.___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/4] anv/blorp: Align vertex buffers to 64B

[Kenneth Graunke]

On Friday, March 31, 2017 4:17:08 PM PDT Jason Ekstrand wrote:
> This fixes issues seen when adding support for full 48-bit addresses.
> The 48-bit addresses themselves have nothing to do with it other than
> that it caused the kernel to place buffers slightly differently so they
> interacted differently with the caches.
> 
> Cc: "13.0 17.0" 
> ---
>  src/intel/vulkan/genX_blorp_exec.c | 14 +-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/src/intel/vulkan/genX_blorp_exec.c 
> b/src/intel/vulkan/genX_blorp_exec.c
> index 1d07fd7..402f6d2 100644
> --- a/src/intel/vulkan/genX_blorp_exec.c
> +++ b/src/intel/vulkan/genX_blorp_exec.c
> @@ -115,8 +115,20 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, 
> uint32_t size,
>struct blorp_address *addr)
>  {
> struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
> +
> +   /* From the Sky Lake PRM, 3DSTATE_VERTEX_BUFFERS:

Skylake PRM.  Might be worth mentioning that this workaround is needed
starting with Broadwell (according to the internal docs), though it
doesn't seem to be in the PRMs until Skylake.

> +*
> +*"The VF cache needs to be invalidated before binding and then using
> +*Vertex Buffers that overlap with any previously bound Vertex Buffer
> +*(at a 64B granularity) since the last invalidation.  A VF cache
> +*invalidate is performed by setting the "VF Cache Invalidation 
> Enable"
> +*bit in PIPE_CONTROL."
> +*
> +* In order to avoid this problem, we align all vertex buffer allocations
> +* to 64 bytes.

I see, because we're streaming out vertex data in the dynamic state
buffer, if we align it, it will never overlap at a 64B granularity.
Nice and simple fix.

Patches 1-2 are:
Reviewed-by: Kenneth Graunke 


signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev