Re: [Mesa-dev] [PATCH] i965: Ignore INTEL_SCALAR_* debug variables on Gen10+.

[Jason Ekstrand]

R-b

On Sat, May 13, 2017 at 12:14 PM, Kenneth Graunke 
wrote:

> Scalar mode has been default since Broadwell, and vector mode is getting
> increasingly unmaintained.  There are a few things that don't even fully
> work in vector mode on Skylake, but we've never cared because nobody
> uses it.  There's no point in porting it forward to new platforms.
>
> So, just ignore the debug options to force it on.
> ---
>  src/intel/compiler/brw_compiler.c | 26 --
>  1 file changed, 16 insertions(+), 10 deletions(-)
>
>  Only compile tested.
>
> diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_
> compiler.c
> index cd9473f9a3b..aa896b9a336 100644
> --- a/src/intel/compiler/brw_compiler.c
> +++ b/src/intel/compiler/brw_compiler.c
> @@ -112,16 +112,22 @@ brw_compiler_create(void *mem_ctx, const struct
> gen_device_info *devinfo)
>
> compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG",
> false);
>
> -   compiler->scalar_stage[MESA_SHADER_VERTEX] =
> -  devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
> -   compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
> -  devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
> -   compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
> -  devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
> -   compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
> -  devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
> -   compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
> -   compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
> +   if (devinfo->gen >= 10) {
> +  /* We don't support vec4 mode on Cannonlake. */
> +  for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
> + compiler->scalar_stage[i] = true;
> +   } else {
> +  compiler->scalar_stage[MESA_SHADER_VERTEX] =
> + devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
> +  compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
> + devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS",
> true);
> +  compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
> + devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES",
> true);
> +  compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
> + devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS",
> true);
> +  compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
> +  compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
> +   }
>
> /* We want the GLSL compiler to emit code that uses condition codes */
> for (int i = 0; i < MESA_SHADER_STAGES; i++) {
> --
> 2.12.2
>
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Re: [Mesa-dev] [PATCH 24/24] i965: Simplify get_l3_way_size() function

[Francisco Jerez]

Francisco Jerez  writes:

> Anuj Phogat  writes:
>
>> Cherryview and Broxton are always gt1. So, remove the redundant checks.
>>
>> Signed-off-by: Anuj Phogat 
>> ---
>>  src/intel/common/gen_l3_config.c | 10 --
>>  1 file changed, 4 insertions(+), 6 deletions(-)
>>
>> diff --git a/src/intel/common/gen_l3_config.c 
>> b/src/intel/common/gen_l3_config.c
>> index 4fe3503..0720079 100644
>> --- a/src/intel/common/gen_l3_config.c
>> +++ b/src/intel/common/gen_l3_config.c
>> @@ -258,13 +258,11 @@ get_l3_way_size(const struct gen_device_info *devinfo)
>> if (devinfo->is_baytrail)
>>return 2;
>>  
>> -   else if (devinfo->gt == 1 ||
>> -devinfo->is_cherryview ||
>> -devinfo->is_broxton)
>> -  return 4;
>> +   /* Cherryview and Broxton are always gt1 */
>> +   if (devinfo->gt == 1)
>> +   return 4;
>>  
>
> I don't feel that replacing self-documenting code with equivalent
> non-self-documenting code plus a comment containing the same information
> as the code you removed actually simplifies anything.  That said, this
> function *could* be simplified appreciably by using the l3_banks field
> you added to gen_device_info to calculate the way size consistently
> across all gens up to Gen10.  Care to do that instead?
>

Please consider the above a NAK of this patch in its current form.

>> -   else
>> -  return 8 * devinfo->num_slices;
>> +   return 8 * devinfo->num_slices;
>>  }
>>  
>>  /**
>> -- 
>> 2.9.3
>>
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Re: [Mesa-dev] [PATCH] radeonsi: bugfix in performance counters

[Marek Olšák]

Reviewed-by: Marek Olšák 

Note that this is not meant for master, because master doesn't need this
fix anymore.

Marek

On Sat, May 13, 2017 at 12:07 AM, Mauro Rossi  wrote:

> 'if (regs->counters)' expression at line 623 is always true,
> spotted because of an error when building android-x86.
>
> 'if (regs->counters[idx])' is used instead.
>
> Fixes the following building error in Android:
>
> external/mesa/src/gallium/drivers/radeonsi/si_perfcounter.c:617:14:
> error: address of array 'regs->counters' will always evaluate to 'true'
> [-Werror,-Wpointer-bool-conversion]
> if (regs->counters)
> ~~  ~~^~~~
>
> Fixes: ad22006 "radeonsi: implement AMD_performance_monitor for CIK+"
> ---
>  src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c
> b/src/gallium/drivers/radeonsi/si_perfcounter.c
> index 41dd52edb1..85b6e5c55a 100644
> --- a/src/gallium/drivers/radeonsi/si_perfcounter.c
> +++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
> @@ -620,7 +620,7 @@ static void si_pc_emit_read(struct r600_common_context
> *ctx,
> reg_delta = -reg_delta;
>
> for (idx = 0; idx < count; ++idx) {
> -   if (regs->counters)
> +   if (regs->counters[idx])
> reg = regs->counters[idx];
>
> radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
> --
> 2.11.0
>
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Re: [Mesa-dev] [PATCH] virgl: fix virgl_bo_transfer_{put, get} box struct copy

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Sat, May 13, 2017 at 12:05 AM, Rob Herring  wrote:

> Commit 3dfe61ed6ec6 ("gallium: decrease the size of pipe_box - 24 -> 16
> bytes") changed the size of pipe_box, but the virgl code was relying on
> pipe_box and drm_virtgpu_3d_box structs having the same size/layout doing
> a struct copy. Copy the fields one by one instead.
>
> Cc: Marek Olšák 
> Cc: Dave Airlie 
> Signed-off-by: Rob Herring 
> ---
>  src/gallium/winsys/virgl/drm/virgl_drm_winsys.c | 14 --
>  1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
> b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
> index 4708126aed9d..0edae4767e6b 100644
> --- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
> +++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
> @@ -264,7 +264,12 @@ virgl_bo_transfer_put(struct virgl_winsys *vws,
>
> memset(, 0, sizeof(tohostcmd));
> tohostcmd.bo_handle = res->bo_handle;
> -   tohostcmd.box = *(struct drm_virtgpu_3d_box *)box;
> +   tohostcmd.box.x = box->x;
> +   tohostcmd.box.y = box->y;
> +   tohostcmd.box.z = box->z;
> +   tohostcmd.box.w = box->width;
> +   tohostcmd.box.h = box->height;
> +   tohostcmd.box.d = box->depth;
> tohostcmd.offset = buf_offset;
> tohostcmd.level = level;
>// tohostcmd.stride = stride;
> @@ -288,7 +293,12 @@ virgl_bo_transfer_get(struct virgl_winsys *vws,
> fromhostcmd.offset = buf_offset;
>// fromhostcmd.stride = stride;
>// fromhostcmd.layer_stride = layer_stride;
> -   fromhostcmd.box = *(struct drm_virtgpu_3d_box *)box;
> +   fromhostcmd.box.x = box->x;
> +   fromhostcmd.box.y = box->y;
> +   fromhostcmd.box.z = box->z;
> +   fromhostcmd.box.w = box->width;
> +   fromhostcmd.box.h = box->height;
> +   fromhostcmd.box.d = box->depth;
> return drmIoctl(vdws->fd, DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST,
> );
>  }
>
> --
> 2.11.0
>
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[Mesa-dev] [PATCH 3/3] i965: Use the upload BO for push constants on Gen7.5-Gen8.

[Kenneth Graunke]

We can easily use the upload BO for push constants on Gen7.5/Gen8 too,
at the cost of a relocation when emitting 3DSTATE_CONSTANT_XS.  We can
simply switch to using constant buffer pointer 2 instead of pointer 0,
like we do on Gen9+.

Ivybridge and Baytrail can't do this trick because they require the
constant buffers to be enabled in order, starting with 0.  We'd have
to set the INSTPM bit to make the constant buffer pointer not relative
to dynamic state base address, which would need kernel command parser
support.

Improves performance in GLBenchmark 2.7/TRex Offscreen by:
- Broadwell GT2: 0.305608% +/- 0.19877% (n = 68)
- Braswell: No difference proven (n = 742)
- Haswell GT3e: 0.180755% +/- 0.0237505% (n = 30)
---
 src/mesa/drivers/dri/i965/gen6_constant_state.c | 2 +-
 src/mesa/drivers/dri/i965/genX_state_upload.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c 
b/src/mesa/drivers/dri/i965/gen6_constant_state.c
index 749e77e958f..f3927c5dba2 100644
--- a/src/mesa/drivers/dri/i965/gen6_constant_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c
@@ -64,7 +64,7 @@ gen6_upload_push_constants(struct brw_context *brw,
   int i;
   const int size = prog_data->nr_params * sizeof(gl_constant_value);
   gl_constant_value *param;
-  if (brw->gen >= 9) {
+  if (brw->gen >= 8 || brw->is_haswell) {
  param = intel_upload_space(brw, size, 32, >curbe.curbe_bo,
 _state->push_const_offset);
   } else {
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index f7128ae8960..5fad3b72e27 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2597,7 +2597,7 @@ upload_constant_state(struct brw_context *brw,
brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), pkt) {
   pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
   if (active) {
-#if GEN_GEN >= 9
+#if GEN_GEN >= 8 || GEN_IS_HASWELL
  pkt.ConstantBody.ConstantBuffer2ReadLength =
 stage_state->push_const_size;
  pkt.ConstantBody.PointerToConstantBuffer2 =
-- 
2.12.2

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[Mesa-dev] [PATCH 1/3] i965: Drop BRW_NEW_PUSH_CONSTANT_ALLOCATION from CS packets.

[Kenneth Graunke]

I don't think CS push constant uploading uses the section of L3
controlled by 3DSTATE_PUSH_CONSTANT_ALLOC_XS.  So I don't think
it needs to be re-emitted when that space is reallocated.

The programming note in gen7_allocate_push_constants doesn't
indicate this is necessary, at least.
---
 src/mesa/drivers/dri/i965/gen7_cs_state.c | 3 +--
 src/mesa/drivers/dri/i965/genX_state_upload.c | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_cs_state.c 
b/src/mesa/drivers/dri/i965/gen7_cs_state.c
index cbb6bb1ef26..26e4264018f 100644
--- a/src/mesa/drivers/dri/i965/gen7_cs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_cs_state.c
@@ -133,8 +133,7 @@ const struct brw_tracked_state gen7_cs_push_constants = {
   .brw = BRW_NEW_BATCH |
  BRW_NEW_BLORP |
  BRW_NEW_COMPUTE_PROGRAM |
- BRW_NEW_CS_PROG_DATA |
- BRW_NEW_PUSH_CONSTANT_ALLOCATION,
+ BRW_NEW_CS_PROG_DATA,
},
.emit = gen7_upload_cs_push_constants,
 };
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 3921a6f2d4b..64ba3577383 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -3735,7 +3735,6 @@ static const struct brw_tracked_state genX(cs_state) = {
   .brw = BRW_NEW_BATCH |
  BRW_NEW_BLORP |
  BRW_NEW_CS_PROG_DATA |
- BRW_NEW_PUSH_CONSTANT_ALLOCATION |
  BRW_NEW_SAMPLER_STATE_TABLE |
  BRW_NEW_SURFACES,
},
-- 
2.12.2

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[Mesa-dev] [PATCH 2/3] i965: Use the upload BO for push constants on Gen9+.

[Kenneth Graunke]

Shaders can use quite a bit of uniform data.  Better to put it in the
upload buffers, like we do for client vertex data, rather than the
batch buffer state area, which is primarly used for indirect state.

This should free up batch space, allowing us to emit more commands in a
batch before flushing.  Because BRW_NEW_BATCH also causes a lot of state
to be re-emitted, it may also reduce CPU overhead a little bit.

We took this approach on Gen4-5, but switched to using the batch area
on Gen6+ because buffer 0 is relative to Dynamic State Base Address by
default, which is set to the start of the batch.

On Gen9+, we already use a relocation due to a workaround, so this is
trivial to change and has basically no downside.

Unfortunately we can't change compute shader push constants because
MEDIA_CURBE_LOAD always uses an offset from dynamic state base address.

Improves performance in GLBenchmark 2.7/TRex Offscreen by:
- Skylake GT4e: 0.52821% +/- 0.113402% (n = 190)
- Apollolake: 0.510225% +/- 0.273064% (n = 70)
---
 src/mesa/drivers/dri/i965/gen6_constant_state.c | 15 ++-
 src/mesa/drivers/dri/i965/genX_state_upload.c   |  2 +-
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c 
b/src/mesa/drivers/dri/i965/gen6_constant_state.c
index 460f1c51457..749e77e958f 100644
--- a/src/mesa/drivers/dri/i965/gen6_constant_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c
@@ -25,6 +25,7 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "intel_batchbuffer.h"
+#include "intel_buffer_objects.h"
 #include "program/prog_parameter.h"
 
 /**
@@ -60,12 +61,16 @@ gen6_upload_push_constants(struct brw_context *brw,
   if (prog)
  _mesa_load_state_parameters(ctx, prog->Parameters);
 
-  gl_constant_value *param;
   int i;
-
-  param = brw_state_batch(brw,
-  prog_data->nr_params * sizeof(gl_constant_value),
-  32, _state->push_const_offset);
+  const int size = prog_data->nr_params * sizeof(gl_constant_value);
+  gl_constant_value *param;
+  if (brw->gen >= 9) {
+ param = intel_upload_space(brw, size, 32, >curbe.curbe_bo,
+_state->push_const_offset);
+  } else {
+ param = brw_state_batch(brw, size, 32,
+ _state->push_const_offset);
+  }
 
   STATIC_ASSERT(sizeof(gl_constant_value) == sizeof(float));
 
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c 
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index 64ba3577383..f7128ae8960 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -2601,7 +2601,7 @@ upload_constant_state(struct brw_context *brw,
  pkt.ConstantBody.ConstantBuffer2ReadLength =
 stage_state->push_const_size;
  pkt.ConstantBody.PointerToConstantBuffer2 =
-render_ro_bo(brw->batch.bo, stage_state->push_const_offset);
+render_ro_bo(brw->curbe.curbe_bo, stage_state->push_const_offset);
 #else
  pkt.ConstantBody.ConstantBuffer0ReadLength =
 stage_state->push_const_size;
-- 
2.12.2

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Re: [Mesa-dev] [PATCH 21/24] i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3

[Kenneth Graunke]

On Friday, May 12, 2017 4:38:25 PM PDT Anuj Phogat wrote:
> v1: By Ben Widawsky 
> v2: Add the restriction for GS, HS and DS and make sure
> the allocated sizes are not multiple of 3.
> 
> Signed-off-by: Anuj Phogat 
> Cc: Ben Widawsky 
> ---
>  src/mesa/drivers/dri/i965/gen7_urb.c | 12 
>  1 file changed, 12 insertions(+)
> 
> diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
> b/src/mesa/drivers/dri/i965/gen7_urb.c
> index 028161d..dc6826a 100644
> --- a/src/mesa/drivers/dri/i965/gen7_urb.c
> +++ b/src/mesa/drivers/dri/i965/gen7_urb.c
> @@ -194,6 +194,17 @@ gen7_upload_urb(struct brw_context *brw, unsigned 
> vs_size,
>entry_size[i] = prog_data[i] ? prog_data[i]->urb_entry_size : 1;
> }
>  
> +   /* For Cannonlake:
> +* Software shall not program an allocation size that specifies a size
> +* that is a multiple of 3 64B (512-bit) cachelines.
> +*/
> +   if (brw->gen == 10) {
> +  for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
> + if (entry_size[i] % 3 == 0)
> +entry_size[i]++;
> +  }
> +   }
> +

This is wrong - you shouldn't be changing this in the state upload code.

You should change it in the compiler.  In src/intel/compiler, git grep
for urb_entry_size.  You'll find it in brw_compile_{vs,tcs,tes,gs}.
Just increment prog_data->base.urb_entry_size, like you're doing here.

Your commit message says that the restriction applies to GS, HS, and DS,
but your code applies it to VS as well.  Is that intentional?

> /* If we're just switching between programs with the same URB 
> requirements,
>  * skip the rest of the logic.
>  */
> @@ -224,6 +235,7 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
>  
> BEGIN_BATCH(8);
> for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
> +  assert(brw->gen != 10 || entry_size[i] % 3);

The assert is good.

>OUT_BATCH((_3DSTATE_URB_VS + i) << 16 | (2 - 2));
>OUT_BATCH(entries[i] |
>  ((entry_size[i] - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) |
> 


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[Mesa-dev] [PATCH] i965: Ignore INTEL_SCALAR_* debug variables on Gen10+.

[Kenneth Graunke]

Scalar mode has been default since Broadwell, and vector mode is getting
increasingly unmaintained.  There are a few things that don't even fully
work in vector mode on Skylake, but we've never cared because nobody
uses it.  There's no point in porting it forward to new platforms.

So, just ignore the debug options to force it on.
---
 src/intel/compiler/brw_compiler.c | 26 --
 1 file changed, 16 insertions(+), 10 deletions(-)

 Only compile tested.

diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c
index cd9473f9a3b..aa896b9a336 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -112,16 +112,22 @@ brw_compiler_create(void *mem_ctx, const struct 
gen_device_info *devinfo)
 
compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 
-   compiler->scalar_stage[MESA_SHADER_VERTEX] =
-  devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
-   compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
-  devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
-   compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
-  devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
-   compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
-  devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
-   compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
-   compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
+   if (devinfo->gen >= 10) {
+  /* We don't support vec4 mode on Cannonlake. */
+  for (int i = MESA_SHADER_VERTEX; i < MESA_SHADER_STAGES; i++)
+ compiler->scalar_stage[i] = true;
+   } else {
+  compiler->scalar_stage[MESA_SHADER_VERTEX] =
+ devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
+  compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
+ devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
+  compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
+ devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
+  compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
+ devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
+  compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
+  compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
+   }
 
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i < MESA_SHADER_STAGES; i++) {
-- 
2.12.2

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Re: [Mesa-dev] [PATCH 24/24] i965: Simplify get_l3_way_size() function

[Francisco Jerez]

Anuj Phogat  writes:

> Cherryview and Broxton are always gt1. So, remove the redundant checks.
>
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/common/gen_l3_config.c | 10 --
>  1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/src/intel/common/gen_l3_config.c 
> b/src/intel/common/gen_l3_config.c
> index 4fe3503..0720079 100644
> --- a/src/intel/common/gen_l3_config.c
> +++ b/src/intel/common/gen_l3_config.c
> @@ -258,13 +258,11 @@ get_l3_way_size(const struct gen_device_info *devinfo)
> if (devinfo->is_baytrail)
>return 2;
>  
> -   else if (devinfo->gt == 1 ||
> -devinfo->is_cherryview ||
> -devinfo->is_broxton)
> -  return 4;
> +   /* Cherryview and Broxton are always gt1 */
> +   if (devinfo->gt == 1)
> +   return 4;
>  

I don't feel that replacing self-documenting code with equivalent
non-self-documenting code plus a comment containing the same information
as the code you removed actually simplifies anything.  That said, this
function *could* be simplified appreciably by using the l3_banks field
you added to gen_device_info to calculate the way size consistently
across all gens up to Gen10.  Care to do that instead?

> -   else
> -  return 8 * devinfo->num_slices;
> +   return 8 * devinfo->num_slices;
>  }
>  
>  /**
> -- 
> 2.9.3
>
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Re: [Mesa-dev] [PATCH 24/24] i965: Simplify get_l3_way_size() function

[Kenneth Graunke]

On Friday, May 12, 2017 4:38:28 PM PDT Anuj Phogat wrote:
> Cherryview and Broxton are always gt1. So, remove the redundant checks.
> 
> Signed-off-by: Anuj Phogat 
> ---
>  src/intel/common/gen_l3_config.c | 10 --
>  1 file changed, 4 insertions(+), 6 deletions(-)
> 
> diff --git a/src/intel/common/gen_l3_config.c 
> b/src/intel/common/gen_l3_config.c
> index 4fe3503..0720079 100644
> --- a/src/intel/common/gen_l3_config.c
> +++ b/src/intel/common/gen_l3_config.c
> @@ -258,13 +258,11 @@ get_l3_way_size(const struct gen_device_info *devinfo)
> if (devinfo->is_baytrail)
>return 2;
>  
> -   else if (devinfo->gt == 1 ||
> -devinfo->is_cherryview ||
> -devinfo->is_broxton)
> -  return 4;
> +   /* Cherryview and Broxton are always gt1 */
> +   if (devinfo->gt == 1)
> +   return 4;
>  
> -   else
> -  return 8 * devinfo->num_slices;
> +   return 8 * devinfo->num_slices;
>  }
>  
>  /**
> 

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH 1/2] Clang doesn't have 64bit __atomic* builtins on i386

[Aaron Watry]

Saying nothing about the correctness, these two patches at least fix the
mesa build for me when running with clang/clang++ where-as they were broken
before when targetting i686-linux-gnu.

--Aaron



On Sat, May 13, 2017 at 4:20 AM, Jan Beich  wrote:

> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function
> `disk_cache_remove':
> disk_cache.c:(.text+0x763): undefined reference to `__atomic_fetch_add_8'
> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function
> `cache_put':
> disk_cache.c:(.text+0xabc): undefined reference to `__atomic_fetch_add_8'
> disk_cache.c:(.text+0xec1): undefined reference to `__atomic_fetch_add_8'
> c++: error: linker command failed with exit code 1 (use -v to see
> invocation)
>
> Signed-off-by: Jan Beich 
> ---
>  configure.ac| 13 -
>  src/util/u_atomic.c |  4 
>  2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/configure.ac b/configure.ac
> index ce5301f3e4..08d8879986 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -415,13 +415,24 @@ AM_CONDITIONAL([GCC_ATOMIC_BUILTINS_SUPPORTED],
> [test x$GCC_ATOMIC_BUILTINS_SUPP
>
>  dnl Check if host supports 64-bit atomics
>  dnl note that lack of support usually results in link (not compile) error
> -AC_MSG_CHECKING(whether __sync_add_and_fetch_8 is supported)
> +save_CFLAGS=$CFLAGS
> +if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
> +CFLAGS="$CFLAGS -DUSE_GCC_ATOMIC_BUILTINS"
> +AC_MSG_CHECKING(whether __atomic_fetch_add_8 is supported)
> +else
> +AC_MSG_CHECKING(whether __sync_add_and_fetch_8 is supported)
> +fi
>  AC_LINK_IFELSE([AC_LANG_SOURCE([[
>  #include 
>  uint64_t v;
>  int main() {
> +#ifdef USE_GCC_ATOMIC_BUILTINS
> +return __atomic_add_fetch(, 1, __ATOMIC_ACQ_REL);
> +#else
>  return __sync_add_and_fetch(, (uint64_t)1);
> +#endif
>  }]])], GCC_64BIT_ATOMICS_SUPPORTED=yes, GCC_64BIT_ATOMICS_SUPPORTED=no)
> +CFLAGS=$save_CFLAGS
>  if test "x$GCC_64BIT_ATOMICS_SUPPORTED" != xyes; then
>  DEFINES="$DEFINES -DMISSING_64BIT_ATOMICS"
>  fi
> diff --git a/src/util/u_atomic.c b/src/util/u_atomic.c
> index 44b75fb0c0..691c34cf30 100644
> --- a/src/util/u_atomic.c
> +++ b/src/util/u_atomic.c
> @@ -34,6 +34,7 @@
>
>  static pthread_mutex_t sync_mutex = PTHREAD_MUTEX_INITIALIZER;
>
> +#ifndef USE_GCC_ATOMIC_BUILTINS
>  WEAK uint64_t
>  __sync_add_and_fetch_8(uint64_t *ptr, uint64_t val)
>  {
> @@ -60,6 +61,8 @@ __sync_sub_and_fetch_8(uint64_t *ptr, uint64_t val)
> return r;
>  }
>
> +#else
> +
>  WEAK uint64_t
>  __atomic_fetch_add_8(uint64_t *ptr, uint64_t val, int memorder)
>  {
> @@ -71,5 +74,6 @@ __atomic_fetch_sub_8(uint64_t *ptr, uint64_t val, int
> memorder)
>  {
> return __sync_sub_and_fetch(ptr, val);
>  }
> +#endif /* !USE_GCC_ATOMIC_BUILTINS */
>
>  #endif
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Re: [Mesa-dev] [PATCH 3/4] intel/isl: Refactor gen6_choose_image_alignment_el

[Jason Ekstrand]

On Fri, May 12, 2017 at 3:35 PM, Chad Versace 
wrote:

> On Thu 11 May 2017, Jason Ekstrand wrote:
> > On Thu, May 11, 2017 at 9:08 PM, Chad Versace 
> > wrote:
> >
> > > On Thu 11 May 2017, Jason Ekstrand wrote:
> > > > On Thu, May 11, 2017 at 7:03 AM, Pohjolainen, Topi <
> > > > topi.pohjolai...@gmail.com> wrote:
> > > >
> > > > > On Wed, May 10, 2017 at 02:30:31PM -0700, Jason Ekstrand wrote:
> > > > > > ---
> > > > > >  src/intel/isl/isl_gen6.c | 30 --
> > > > > >  1 file changed, 12 insertions(+), 18 deletions(-)
> > > > > >
> > > > > > diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c
> > > > > > index b746903..0de9620 100644
> > > > > > --- a/src/intel/isl/isl_gen6.c
> > > > > > +++ b/src/intel/isl/isl_gen6.c
> > > > > > @@ -88,6 +88,8 @@ isl_gen6_choose_image_alignment_el(const
> struct
> > > > > isl_device *dev,
> > > > > >  *| format | halign | valign |
> > > > > >  *++++
> > > > > >  *| YUV 4:2:2 formats  |  4 |  * |
> > > > > > +*| BC1-5  |  4 |  4 |
> > > > > > +*| FXT1   |  8 |  4 |
> > > > > >  *| uncompressed formats   |  4 |  * |
> > > > > >  *++++
> > > > > >  *
> > > > > > @@ -110,29 +112,13 @@ isl_gen6_choose_image_alignment_el(const
> > > struct
> > > > > isl_device *dev,
> > > > > >  */
> > > > > >
> > > > > > if (isl_format_is_compressed(info->format)) {
> > > > > > +  /* Compressed formats have an alignment equal to their
> block
> > > size
> > > > > */
> > > > > >*image_align_el = isl_extent3d(1, 1, 1);
> > > > > >return;
> > > > > > }
> > > > > >
> > > > > > -   if (isl_format_is_yuv(info->format)) {
> > > > > > -  *image_align_el = isl_extent3d(4, 2, 1);
> > > > > > -  return;
> > > > > > -   }
> > > > > > -
> > > > > > -   if (info->samples > 1) {
> > > > > > -  *image_align_el = isl_extent3d(4, 4, 1);
> > > > > > -  return;
> > > > > > -   }
> > > > > > -
> > > > > > -   if (isl_surf_usage_is_depth_or_stencil(info->usage) &&
> > > > > > -   !ISL_DEV_USE_SEPARATE_STENCIL(dev)) {
> > > > >
> > > > > Maybe mention in the commit that we drop this as it is always
> false on
> > > > > gen6+?
> > > > > In isl.c: "dev->use_separate_stencil = ISL_DEV_GEN(dev) >= 6;"
> > > > >
> > > >
> > > > No, I dropped it not because we always use separate stencil but
> because
> > > > it's redundant with the regular depth case.  The PRM says to use a
> 4x4
> > > > alignment for all depth buffers but 4x2 for separate stencil.
> Combined
> > > > depth-stencil falls under the "depth" case so I didn't think we
> needed to
> > > > call it out explicitly.
> > >
> > > I admit that the condition I wrote
> > >
> > > if (isl_surf_usage_is_depth_or_stencil(info->usage) &&
> > > !ISL_DEV_USE_SEPARATE_STENCIL(dev))
> > >
> > > was poorly chosen. I should've written it without relying on
> > > ISL_DEV_USE_SEPARATE_STENCIL.
> > >
> > > Topi has a point because a surface with
> > > format=ISL_FORMAT_X24_TYPELESS_G8_UINT will necessarily have
> > > usage=ISL_SURF_USAGE_STENCIL_BIT (no depth bit). The hardware requires
> > > the surface to have valign=4, and my badly written (but correct)
> > > condition ensured valign=4 in this case. After this patch, the function
> > > wrongly chooses valign=2.
> > >
> >
> > No it won't.  It's hard to see in patch form, but after this patch is
> > applied we check for depth first and then stencil.  If it has ANY depth
> > component, then it will get 4x4 aligned.  Only separate stencil gets 4x2.
>
> This function, pre-patch and post-patch, does not inspect the format for
> a depth component.  It checks if the depth usage flag is set. That's the
> key difference.
>
> On gen6, it's possible to create a usable surface with format
> X24_TYPELESS_G8_UINT with ISL_SURF_USAGE_STENCIL_BIT and no depth bit.
> And, if I understand this patch correctly, that surface does not satisfy
> the depth check in this patch:
>
> if (isl_surf_usage_is_depth(info->usage)) {
>/* depth buffer (possibly interleaved with stencil) */
>*image_align_el = isl_extent3d(4, 4, 1);
>return;
> }
>
> Instead, that surface eventually hits this at the bottom of the
> function:
>
>*image_align_el = isl_extent3d(4, 2, 1);
>
> Of course, such a surface is only usable as a stencil buffer if hiz is
> disabled. So we'll probably never observe such a surface in real life.
> But we should at least assert that's the case.
>

Since this verions preserves the original broken behavior, how about I make
a follow-on patch which changes it to do

/* Separate stencil requires 4x2 alignment */
if (isl_surf_usage_is_stencil(info->usage) && info->format ==
ISL_FORMAT_R8) {
   *image_align_el = isl_extent3d(4, 2, 1);

Re: [Mesa-dev] anv: finishing bay trail support

[Jason Ekstrand]

Jonas,

Welcome to mesa-dev!

On May 11, 2017 12:08:01 PM Jonas Kulla  wrote:


Hello everyone,

I'm a student who's looking to create a small Vulkan demo for my computer
graphics class; my laptop (CPU: Intel N3540) has an integrated Bay Trail
chip if I looked that up right, which should be capable of supporting
Vulkan.


Yes, that is a Bay Trail which can mostly support Vulkan. (More on that later.)



I saw that Bay Trail support in anv is marked "experimental", and indeed
running vulkaninfo crashes with

info.c:518: failed with VK_ERROR_INITIALIZATION_FAILED


That doesn't seem right.  I don't know that I've ever fired up our driver 
on a Bay Trail personally but it should mostly work.  I guess you've found 
the first step in your project.  :-)  Getting vulkaninfo working should be 
easy.  Just set a breakpoint in the driver and figure out why it's throwing 
VK_ERROR_INITIALIZATION_FAILED.  If you have a debug build it will probably 
even print the reason out to stderr for you.



I was wondering if someone could comment on how much work would be
involved in completing the Bay Trail code in anv, and if it's not too much,
whether someone would be willing to offer me light mentorship in doing
so.


Bay trail should be working basically exactly as well as Ivy Bridge which 
means lots of stuff should run though it won't be close to conformant.  
What's missing?  First off, there's probably a bunch of regular bug-fixing 
to do.  Most of the gen7 code is shared with gen8 but there are still a 
bunch of gen7 bugs that no one has bothered to track down.  It shouldn't be 
too bad as we do run Haswell in our CI system and it's down to a couple 
hundred CTS fails last I checked.  Fortunately, the Vulkan test suite is 
fully open-source so you can easily download and run it once you get 
vulkaninfo working.


Beyond just bugfixing, there are also a number of core Vulkan features for 
which gen7 lacks hardware support.  Most of these are features we expose in 
GL so we have some sort of workaround.  The workarounds will have to be 
ported to Vulkan somehow (though it may not be the same workaround in the 
end). Off the top of my head:


- Texture Swizzle
- Stencil Texturing
- Some missing VkFormats
- vkCmdWaitEvent
- Missing the MI_MATH stuff required for queries

There may be more that I'm just not remembering.


I'm mostly comfortable with OpenGL and general graphics / GPU concepts,
but I have no experience in driver code aside from following Mesa
development
as a bystander.


Everyone starts somewhere.  Feel free to dive right in and give it a go!   
If you have any questions along the way, the best way to get answers is 
probably to ask them on #dri-devel or #intel-gfx on IRC.  I'm usually on 
(nick: jekstrand) and am happy to answer questions.


--Jason
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[Mesa-dev] [PATCH] radv: Save descriptor set even if vertex buffers are not saved.

[Bas Nieuwenhuizen]

Totally independent.

Signed-off-by: Bas Nieuwenhuizen 
Fixes: 0e6d532d327 "radv/meta: add support for save/restore meta without vertex 
data."
---
 src/amd/vulkan/radv_meta.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 973316103aa..4f359bd6a9d 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -36,6 +36,7 @@ radv_meta_save_novertex(struct radv_meta_saved_state *state,
   uint32_t dynamic_mask)
 {
state->old_pipeline = cmd_buffer->state.pipeline;
+   state->old_descriptor_set0 = cmd_buffer->state.descriptors[0];
 
state->dynamic_mask = dynamic_mask;
radv_dynamic_state_copy(>dynamic, _buffer->state.dynamic,
@@ -50,9 +51,9 @@ radv_meta_restore(const struct radv_meta_saved_state *state,
  struct radv_cmd_buffer *cmd_buffer)
 {
cmd_buffer->state.pipeline = state->old_pipeline;
+   cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
+   cmd_buffer->state.descriptors_dirty |= (1u << 0);
if (state->vertex_saved) {
-   cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
-   cmd_buffer->state.descriptors_dirty |= (1u << 0);
memcpy(cmd_buffer->state.vertex_bindings, 
state->old_vertex_bindings,
   sizeof(state->old_vertex_bindings));
cmd_buffer->state.vb_dirty |= (1 << 
RADV_META_VERTEX_BINDING_COUNT) - 1;
-- 
2.12.2

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Re: [Mesa-dev] [PATCH 14/24] i965/cnl: Handle gen10 in switch cases across the driver

[Jason Ekstrand]

Most of these still point to gen9 functions even though we have gen10 
versions now.  We should point to the gen10 versions.  Yes, I know some of 
that is in a later patch but I see no reason why we can't roll those into 
this patch and also fix up blorp and the few other things in this patch 
while were here.



On May 12, 2017 4:40:20 PM Anuj Phogat  wrote:


We are still using some gen9 functions for gen10 in this patch.
They will be replaced by gen10 functions in later patches.

Signed-off-by: Anuj Phogat 
---
 src/intel/common/gen_l3_config.c| 1 +
 src/intel/compiler/brw_eu.c | 2 ++
 src/intel/compiler/brw_eu_compact.c | 1 +
 src/intel/isl/isl.c | 3 +++
 src/intel/vulkan/anv_cmd_buffer.c   | 1 +
 src/intel/vulkan/anv_device.c   | 1 +
 src/intel/vulkan/anv_entrypoints_gen.py | 1 +
 src/mesa/drivers/dri/i965/brw_blorp.c   | 1 +
 src/mesa/drivers/dri/i965/brw_formatquery.c | 1 +
 src/mesa/drivers/dri/i965/intel_screen.c| 1 +
 10 files changed, 13 insertions(+)

diff --git a/src/intel/common/gen_l3_config.c 
b/src/intel/common/gen_l3_config.c

index 0783217..4fe3503 100644
--- a/src/intel/common/gen_l3_config.c
+++ b/src/intel/common/gen_l3_config.c
@@ -116,6 +116,7 @@ get_l3_configs(const struct gen_device_info *devinfo)
   return (devinfo->is_cherryview ? chv_l3_configs : bdw_l3_configs);

case 9:
+   case 10:
   return chv_l3_configs;

default:
diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index 77400c1..2c0dc27 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -412,6 +412,7 @@ enum gen {
GEN75 = (1 << 5),
GEN8  = (1 << 6),
GEN9  = (1 << 7),
+   GEN10  = (1 << 8),
GEN_ALL = ~0
 };

@@ -688,6 +689,7 @@ gen_from_devinfo(const struct gen_device_info *devinfo)
case 7: return devinfo->is_haswell ? GEN75 : GEN7;
case 8: return GEN8;
case 9: return GEN9;
+   case 10: return GEN10;
default:
   unreachable("not reached");
}
diff --git a/src/intel/compiler/brw_eu_compact.c 
b/src/intel/compiler/brw_eu_compact.c

index b2af76d..740a395 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -1362,6 +1362,7 @@ brw_init_compaction_tables(const struct 
gen_device_info *devinfo)

assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0);

switch (devinfo->gen) {
+   case 10:
case 9:
case 8:
   control_index_table = gen8_control_index_table;
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f89f351..5dc41fa 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1672,6 +1672,7 @@ isl_surf_fill_state_s(const struct isl_device *dev, 
void *state,

   isl_gen8_surf_fill_state_s(dev, state, info);
   break;
case 9:
+   case 10:
   isl_gen9_surf_fill_state_s(dev, state, info);
   break;
default:
@@ -1703,6 +1704,7 @@ isl_buffer_fill_state_s(const struct isl_device *dev, 
void *state,

   isl_gen8_buffer_fill_state_s(state, info);
   break;
case 9:
+   case 10:
   isl_gen9_buffer_fill_state_s(state, info);
   break;
default:
@@ -1770,6 +1772,7 @@ isl_emit_depth_stencil_hiz_s(const struct isl_device 
*dev, void *batch,

   isl_gen8_emit_depth_stencil_hiz_s(dev, batch, info);
   break;
case 9:
+   case 10:
   isl_gen9_emit_depth_stencil_hiz_s(dev, batch, info);
   break;
default:
diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c

index 120b864..d34f9f8 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -334,6 +334,7 @@ anv_cmd_buffer_emit_state_base_address(struct 
anv_cmd_buffer *cmd_buffer)

case 8:
   return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
case 9:
+   case 10:
   return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
default:
   unreachable("unsupported gen\n");
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 35e4030..455c5f9 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1141,6 +1141,7 @@ VkResult anv_CreateDevice(
   result = gen8_init_device_state(device);
   break;
case 9:
+   case 10:
   result = gen9_init_device_state(device);
   break;
default:
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py

index a21228c..f293848 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -183,6 +183,7 @@ TEMPLATE_C = Template(textwrap.dedent(u"""\
}

switch (devinfo->gen) {
+   case 10:
case 9:
   if (gen9_layer.entrypoints[index])
  return gen9_layer.entrypoints[index];
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c

index 

Re: [Mesa-dev] [PATCH 13/24] i965/cnl: Update few assertions

[Jason Ekstrand]

On May 12, 2017 4:41:36 PM Anuj Phogat  wrote:


Signed-off-by: Anuj Phogat 
---
 src/intel/compiler/brw_compiler.h   | 2 +-
 src/mesa/drivers/dri/i965/brw_program.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_compiler.h 
b/src/intel/compiler/brw_compiler.h

index b5b1ee9..d6bbda1 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -1042,7 +1042,7 @@ brw_stage_has_packed_dispatch(const struct 
gen_device_info *devinfo,

 * to do a full test run with brw_fs_test_dispatch_packing() hooked up to
 * the NIR front-end before changing this assertion.
 */
-   assert(devinfo->gen <= 9);
+   assert(devinfo->gen <= 10);


Did you actually do the test described in the above comment?



switch (stage) {
case MESA_SHADER_FRAGMENT: {
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c

index d26dce0..f442d55 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -290,7 +290,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield 
barriers)

unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
 PIPE_CONTROL_NO_WRITE |
 PIPE_CONTROL_CS_STALL);
-   assert(brw->gen >= 7 && brw->gen <= 9);
+   assert(brw->gen >= 7 && brw->gen <= 10);

if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
GL_ELEMENT_ARRAY_BARRIER_BIT |
--
2.9.3

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Re: [Mesa-dev] [PATCH 12/24] i965/cnl: Add cnl bits in aubinator

[Jason Ekstrand]

On May 12, 2017 4:41:22 PM Anuj Phogat  wrote:


Signed-off-by: Anuj Phogat 
---
 src/intel/tools/aubinator.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index 53b2a27..d15476d 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -970,7 +970,8 @@ struct {
{ "bdw", MAKE_GEN(8, 0) },
{ "skl", MAKE_GEN(9, 0) },
{ "chv", MAKE_GEN(8, 0) },
-   { "bxt", MAKE_GEN(9, 0) }
+   { "bxt", MAKE_GEN(9, 0) },
+   { "cnl", MAKE_GEN(10, 0) }


Mind leaving a trailing comma?  That way the next person to add an entry 
doesn't have to change two lines.



 };

 enum {
@@ -1138,7 +1139,7 @@ print_help(const char *progname, FILE *file)
"Decode aub file contents from either FILE or the standard 
input.\n\n"
"A valid --gen option must be provided.\n\n"
"  --help  display this help and exit\n"
-   "  --gen=platform  decode for given platform (ivb, byt, 
hsw, bdw, chv, skl, kbl or bxt)\n"
+   "  --gen=platform  decode for given platform (ivb, byt, 
hsw, bdw, chv, skl, kbl, bxt or cnl)\n"

"  --headers   decode only command headers\n"
"  --color[=WHEN]  colorize the output; WHEN can be 'auto' 
(default\n"
"if omitted), 'always', or 'never'\n"
@@ -1166,7 +1167,8 @@ int main(int argc, char *argv[])
   { "chv", 0x22B3 }, /* Intel(R) HD Graphics (Cherryview) */
   { "skl", 0x1912 }, /* Intel(R) HD Graphics 530 (Skylake GT2) */
   { "kbl", 0x591D }, /* Intel(R) Kabylake GT2 */
-  { "bxt", 0x0A84 }  /* Intel(R) HD Graphics (Broxton) */
+  { "bxt", 0x0A84 },  /* Intel(R) HD Graphics (Broxton) */
+  { "cnl", 0x5A52 }  /* Intel(R) HD Graphics (Cannonlake) */


Same here.


};
const struct option aubinator_opts[] = {
   { "help",   no_argument,   (int *) , true },
--
2.9.3

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Re: [Mesa-dev] [PATCH 08/24] i965/cnl: Add isl_gen10 header and source files

[Jason Ekstrand]

If everything truely is the same here, I see no reason why we should add a 
gen10 version.  I know this appears to contradict what I said before but 
the difference is that this file is handwritten and not just a recompile of 
an already multi-gen file.  We don't, for instance have separate gen7 and 
gen75 isl files.



On May 12, 2017 4:40:42 PM Anuj Phogat  wrote:


Signed-off-by: Anuj Phogat 
---
 src/intel/isl/isl_gen10.c | 41 +
 src/intel/isl/isl_gen10.h | 45 +
 2 files changed, 86 insertions(+)
 create mode 100644 src/intel/isl/isl_gen10.c
 create mode 100644 src/intel/isl/isl_gen10.h

diff --git a/src/intel/isl/isl_gen10.c b/src/intel/isl/isl_gen10.c
new file mode 100644
index 000..3652d58
--- /dev/null
+++ b/src/intel/isl/isl_gen10.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2017 Intel Corporation
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files (the "Software"),
+ *  to deal in the Software without restriction, including without limitation
+ *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ *  Software is furnished to do so, subject to the following conditions:
+ *
+ *  The above copyright notice and this permission notice (including the next
+ *  paragraph) shall be included in all copies or substantial portions of the
+ *  Software.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
DEALINGS

+ *  IN THE SOFTWARE.
+ */
+
+#include "isl_gen9.h"
+#include "isl_gen10.h"
+#include "isl_priv.h"
+
+void
+isl_gen10_choose_image_alignment_el(const struct isl_device *dev,
+const struct isl_surf_init_info 
*restrict info,

+enum isl_tiling tiling,
+enum isl_dim_layout dim_layout,
+enum isl_msaa_layout msaa_layout,
+struct isl_extent3d *image_align_el)
+{
+   /* No changes in image alignment fields from gen9 to gen10. So, just use
+* the gen9 function.
+*/
+   isl_gen9_choose_image_alignment_el(dev, info, tiling, dim_layout,
+  msaa_layout, image_align_el);
+}
diff --git a/src/intel/isl/isl_gen10.h b/src/intel/isl/isl_gen10.h
new file mode 100644
index 000..35c12cf
--- /dev/null
+++ b/src/intel/isl/isl_gen10.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Intel Corporation
+ *
+ *  Permission is hereby granted, free of charge, to any person obtaining a
+ *  copy of this software and associated documentation files (the "Software"),
+ *  to deal in the Software without restriction, including without limitation
+ *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ *  and/or sell copies of the Software, and to permit persons to whom the
+ *  Software is furnished to do so, subject to the following conditions:
+ *
+ *  The above copyright notice and this permission notice (including the next
+ *  paragraph) shall be included in all copies or substantial portions of the
+ *  Software.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
DEALINGS

+ *  IN THE SOFTWARE.
+ */
+
+#ifndef ISL_GEN10_H
+#define ISL_GEN10_H
+
+#include "isl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void
+isl_gen10_choose_image_alignment_el(const struct isl_device *dev,
+const struct isl_surf_init_info 
*restrict info,

+enum isl_tiling tiling,
+enum isl_dim_layout dim_layout,
+enum isl_msaa_layout msaa_layout,
+struct isl_extent3d *image_align_el);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ISL_GEN10_H */
--
2.9.3

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Re: [Mesa-dev] [PATCH 07/24] i965/cnl: Update the script generating genX_bits.h

[Jason Ekstrand]

On May 12, 2017 4:41:26 PM Anuj Phogat  wrote:


Signed-off-by: Anuj Phogat 
Reviewed-by: Jason Ekstrand 
---
 src/intel/genxml/gen_bits_header.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/intel/genxml/gen_bits_header.py 
b/src/intel/genxml/gen_bits_header.py

index ac8ec4c..2fb5f0c 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -80,6 +80,7 @@ static inline uint32_t ATTRIBUTE_PURE
 ${item.token_name}_${prop}(const struct gen_device_info *devinfo)
 {
switch (devinfo->gen) {
+   case 10: return ${item.get_prop(prop, 10)};
case 9: return ${item.get_prop(prop, 9)};
case 8: return ${item.get_prop(prop, 8)};
case 7:
@@ -168,9 +169,8 @@ class Gen(object):
 def __init__(self, z):
 # Convert potential "major.minor" string
 z = float(z)
-if z < 10:
-z *= 10
-self.tenx = int(z)
+z *= 10
+self.tenx = int(float(z) * 10)


You're multiplying by 10 twice here and converting to float twice.  Both 
the "z = float(z)" and the "z *= 10" lines can and should be dropped.




 def __lt__(self, other):
 return self.tenx < other.tenx
--
2.9.3

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Re: [Mesa-dev] [PATCH 0/2] Allow redeclaration of GLSL builtins; fixes Dying Light and Dead Island Definitive Edition

[Samuel Pitoiset]

In an ideal world, I would prefer the compiler to be less strict for 
dump things like that, but it might require more work, so your solution 
is fine by me.


I can confirm this fixes Dying Light, not sure why we didn't find this 
before (we probably followed a wrong path), but it's a nice find. Thanks! :)


The "compat" issue is a different problem which should be investigated a 
bit more. Again, in an ideal world, I would like users to be able to 
launch the games without any overrides.


Cheers,
Samuel.

On 05/12/2017 03:39 PM, John Brooks wrote:

Since release, Dying Light and Dead Island Definitive Edition have been broken
on Mesa, producing at best only a black screen after loading. I found that the
root of the problem is that their vertex shaders redeclare the GLSL builtin
gl_VertexID, which Mesa's compiler considers to be an error:

 error: `gl_VertexID' redeclared

These patches make the compiler more lenient so that the shaders compile.
Because such redeclarations are not explicitly valid in the spec, this
behaviour is selectively activated by the new allow_glsl_builtin_redeclaration
driconf option, which has been enabled for both games in the default drirc.

With this change, both games work on Mesa and render correctly. Note that the
games require OpenGL 4.4+, and so it is necessary to launch them with
MESA_GL_VERSION_OVERRIDE and MESA_GLSL_VERSION_OVERRIDE set to OpenGL 4.4 (GLSL
440) or higher.

Contrary to popular belief, this problem actually had nothing whatsoever to do
with compatibility profiles. Forcing Mesa to create a higher version
compatibility profile with MESA_GL_VERSION_OVERRIDE=4.5COMPAT or
allow_higher_compat_version results in graphical glitches, so don't use that.


A few extra notes for users reading this: I had terrible, unplayable
performance with Dying Light on a configuration with an R9 290, Mesa 17.1-rc3,
and the radeon kernel driver on kernel 4.10. Switching to the amdgpu driver
(enable CONFIG_DRM_AMDGPU_CIK, blacklist radeon, install amdgpu DDX and set
Driver "amdgpu" in xorg.conf) on kernel 4.11 made it playable.  With amdgpu it
hovers around 25-35fps except in select areas (such as the Tower lobby and near
Zere's trailer) near the start of the game where the framerate plummets for no
apparent reason. Dead Island Definitive Edition performs much better in general
than Dying Light, at least on amdgpu. I did not test DIDE on radeon. Ongoing
TTM optimization work may mitigate the performance problems in the future.


The main thing I'm unsure of is whether allowing GLSL builtin redeclarations
should be a driconf option or default behaviour. I looked through the GLSL spec
and initially thought that such redeclarations were permitted because of this
line from page 66 of 
:

 in vec4 gl_FragCoord; // redeclaration that changes nothing is allowed

But others on IRC interpreted it as referring only to gl_FragCoord, which I
agree would make sense given the context. So to be on the safe side I made it
conditional on a driconf option. I leave the final decision to the reviewers.
Let me know what you think.

Thank you to to funfunctor, notaz, and others from the #radeon IRC channel for
their suggestions and their help with analyzing the game binaries.

--
John Brooks
Frogging101 on IRC and elsewhere


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Re: [Mesa-dev] [PATCH 2/3] glsl: Conditionally allow redeclaration of builtins

[Samuel Pitoiset]

On 05/12/2017 03:39 PM, John Brooks wrote:

Conditional on allow_glsl_builtin_redeclaration driconf option.

Signed-off-by: John Brooks 
---
  src/compiler/glsl/ast_to_hir.cpp | 16 
  src/compiler/glsl/glsl_parser_extras.cpp |  2 ++
  src/compiler/glsl/glsl_parser_extras.h   |  1 +
  3 files changed, 19 insertions(+)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 0dc69ef..c743dfe 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -4276,6 +4276,22 @@ get_variable_being_redeclared(ir_variable *var, YYLTYPE 
loc,
 */
earlier->data.precision = var->data.precision;
  
+   } else if(earlier->data.how_declared == ir_var_declared_implicitly &&

+ state->allow_builtin_redeclaration) {
+  /* Allow verbatim redeclarations of built-in variables. Not explicitly
+   * valid, but some applications do it.
+   */
+  if(earlier->data.mode != var->data.mode &&
+ !(earlier->data.mode == ir_var_system_value &&
+   var->data.mode == ir_var_shader_in)) {
+ _mesa_glsl_error(, state,
+  "redeclaration of `%s' with incorrect qualifiers",
+  var->name);
+  } else if (earlier->type != var->type) {
+ _mesa_glsl_error(, state,
+  "redeclaration of `%s' has incorrect type",
+  var->name);
+  }


Style: please put spaces after 'if'.


 } else if (allow_all_redeclarations) {
if (earlier->data.mode != var->data.mode) {
   _mesa_glsl_error(, state,
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp 
b/src/compiler/glsl/glsl_parser_extras.cpp
index d731e35..1405a7e 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -305,6 +305,8 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct 
gl_context *_ctx,
sizeof(this->atomic_counter_offsets));
 this->allow_extension_directive_midshader =
ctx->Const.AllowGLSLExtensionDirectiveMidShader;
+   this->allow_builtin_redeclaration =
+  ctx->Const.AllowGLSLBuiltinRedeclaration;
  
 this->cs_input_local_size_variable_specified = false;
  
diff --git a/src/compiler/glsl/glsl_parser_extras.h b/src/compiler/glsl/glsl_parser_extras.h

index 3a84d65..3981994 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -842,6 +842,7 @@ struct _mesa_glsl_parse_state {
 unsigned atomic_counter_offsets[MAX_COMBINED_ATOMIC_BUFFERS];
  
 bool allow_extension_directive_midshader;

+   bool allow_builtin_redeclaration;
  
 /**

  * Known subroutine type declarations.


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Re: [Mesa-dev] [PATCH 1/3] driconf: Add allow_glsl_builtin_redeclaration option

[Samuel Pitoiset]

I would rename to allow_glsl_builtin_variable_redeclaration.

On 05/12/2017 03:39 PM, John Brooks wrote:

This option will allow GLSL builtins to be redeclared verbatim (e.g.
redeclaring "in int gl_VertexID" in a vertex shader). This is not strictly
valid and would normally fail to compile, but some applications (such as
newer Techland ports) do it and need more leniency.

Signed-off-by: John Brooks 
---
  src/gallium/include/state_tracker/st_api.h  | 1 +
  src/gallium/state_trackers/dri/dri_screen.c | 3 +++
  src/mesa/drivers/dri/common/xmlpool/t_options.h | 5 +
  src/mesa/drivers/dri/i965/brw_context.c | 3 +++
  src/mesa/drivers/dri/i965/intel_screen.c| 1 +
  src/mesa/main/mtypes.h  | 5 +
  src/mesa/state_tracker/st_extensions.c  | 2 ++
  7 files changed, 20 insertions(+)

diff --git a/src/gallium/include/state_tracker/st_api.h 
b/src/gallium/include/state_tracker/st_api.h
index 9d0eb3a..8dda438 100644
--- a/src/gallium/include/state_tracker/st_api.h
+++ b/src/gallium/include/state_tracker/st_api.h
@@ -246,6 +246,7 @@ struct st_config_options
 unsigned force_glsl_version;
 boolean force_s3tc_enable;
 boolean allow_glsl_extension_directive_midshader;
+   boolean allow_glsl_builtin_redeclaration;
 boolean allow_higher_compat_version;
 boolean glsl_zero_init;
 boolean force_glsl_abs_sqrt;
diff --git a/src/gallium/state_trackers/dri/dri_screen.c 
b/src/gallium/state_trackers/dri/dri_screen.c
index 998e8ef..2ea892d 100644
--- a/src/gallium/state_trackers/dri/dri_screen.c
+++ b/src/gallium/state_trackers/dri/dri_screen.c
@@ -75,6 +75,7 @@ const __DRIconfigOptionsExtension gallium_config_options = {
   DRI_CONF_DISABLE_SHADER_BIT_ENCODING("false")
   DRI_CONF_FORCE_GLSL_VERSION(0)
   DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
+ DRI_CONF_ALLOW_GLSL_BUILTIN_REDECLARATION("false")
   DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
   DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
DRI_CONF_SECTION_END
@@ -108,6 +109,8 @@ dri_fill_st_options(struct dri_screen *screen)
driQueryOptionb(optionCache, "force_s3tc_enable");
 options->allow_glsl_extension_directive_midshader =
driQueryOptionb(optionCache, 
"allow_glsl_extension_directive_midshader");
+   options->allow_glsl_builtin_redeclaration =
+  driQueryOptionb(optionCache, "allow_glsl_builtin_redeclaration");
 options->allow_higher_compat_version =
driQueryOptionb(optionCache, "allow_higher_compat_version");
 options->glsl_zero_init = driQueryOptionb(optionCache, "glsl_zero_init");
diff --git a/src/mesa/drivers/dri/common/xmlpool/t_options.h 
b/src/mesa/drivers/dri/common/xmlpool/t_options.h
index cd4f025..c873f31 100644
--- a/src/mesa/drivers/dri/common/xmlpool/t_options.h
+++ b/src/mesa/drivers/dri/common/xmlpool/t_options.h
@@ -115,6 +115,11 @@ 
DRI_CONF_OPT_BEGIN_B(allow_glsl_extension_directive_midshader, def) \
  DRI_CONF_DESC(en,gettext("Allow GLSL #extension directives in the middle 
of shaders")) \
  DRI_CONF_OPT_END
  
+#define DRI_CONF_ALLOW_GLSL_BUILTIN_REDECLARATION(def) \

+DRI_CONF_OPT_BEGIN_B(allow_glsl_builtin_redeclaration, def) \
+DRI_CONF_DESC(en,gettext("Allow GLSL built-in variables to be redeclared 
verbatim")) \
+DRI_CONF_OPT_END
+
  #define DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION(def) \
  DRI_CONF_OPT_BEGIN_B(allow_higher_compat_version, def) \
  DRI_CONF_DESC(en,gettext("Allow a higher compat profile (version 3.1+) for 
apps that request it")) \
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 5055dd7..f6bce4d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -934,6 +934,9 @@ brw_process_driconf_options(struct brw_context *brw)
 ctx->Const.AllowGLSLExtensionDirectiveMidShader =
driQueryOptionb(options, "allow_glsl_extension_directive_midshader");
  
+   ctx->Const.AllowGLSLBuiltinRedeclaration =

+  driQueryOptionb(options, "allow_glsl_builtin_redeclaration");
+
 ctx->Const.AllowHigherCompatVersion =
driQueryOptionb(options, "allow_higher_compat_version");
  
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c

index 3717728..9f9cdc8 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -89,6 +89,7 @@ DRI_CONF_BEGIN
DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED("false")
DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION("false")
DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER("false")
+  DRI_CONF_ALLOW_GLSL_BUILTIN_REDECLARATION("false")
DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION("false")
DRI_CONF_FORCE_GLSL_ABS_SQRT("false")
  
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h

index 28d3d948..47b8b8d 100644
--- a/src/mesa/main/mtypes.h
+++ 

Re: [Mesa-dev] [PATCH] mesa: don't crash in KHR_no_error uniform variants when location == -1

[Samuel Pitoiset]

Mmh, this can still crash if location is < -1 or greater than the number 
of uniforms. How about:


struct gl_uniform_storage *uni = NULL;
if (_mesa_is_no_error_enabled(ctx)) {
  if (location >= 0 && location < shProg->NumUniformRemapTable)
uni = shProg->UniformRemapTable[location];
  if (!uni)
return;
  ...
} else {
  ...
}

On 05/13/2017 08:31 AM, Timothy Arceri wrote:

---
  src/mesa/main/uniform_query.cpp | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 0e02a76..5f38aa5 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -904,20 +904,23 @@ validate_uniform(GLint location, GLsizei count, const 
GLvoid *values,
  extern "C" void
  _mesa_uniform(GLint location, GLsizei count, const GLvoid *values,
struct gl_context *ctx, struct gl_shader_program *shProg,
enum glsl_base_type basicType, unsigned src_components)
  {
 unsigned offset;
 int size_mul = glsl_base_type_is_64bit(basicType) ? 2 : 1;
  
 struct gl_uniform_storage *uni;

 if (_mesa_is_no_error_enabled(ctx)) {
+  if (location == -1)
+ return;
+
uni = shProg->UniformRemapTable[location];
  
/* The array index specified by the uniform location is just the

 * uniform location minus the base location of of the uniform.
 */
assert(uni->array_elements > 0 || location == (int)uni->remap_location);
offset = location - uni->remap_location;
 } else {
uni = validate_uniform(location, count, values, , ctx, shProg,
   basicType, src_components);


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Re: [Mesa-dev] Fix __atomic* builtins detection for Clang

[Jonathan Gray]

On Sat, May 13, 2017 at 09:01:49AM +0200, Jan Beich wrote:
> Jonathan Gray  writes:
> 
> > On Sat, May 13, 2017 at 02:22:30AM +0200, Jan Beich wrote:
> >
> >> "int" isn't large enough and lack of builtins only manifests at link time.
> >> This was breaking build on FreeBSD 11.0 i386 with Clang 3.8.0.
> >> 
> >> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
> >> `disk_cache_remove':
> >> disk_cache.c:(.text+0x763): undefined reference to `__atomic_fetch_add_8'
> >> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
> >> `cache_put':
> >> disk_cache.c:(.text+0xabc): undefined reference to `__atomic_fetch_add_8'
> >> disk_cache.c:(.text+0xec1): undefined reference to `__atomic_fetch_add_8'
> >> c++: error: linker command failed with exit code 1 (use -v to see 
> >> invocation)
> >
> > You should be building with -march=i586 on i386 for CX8.
> 
> -march=i586 doesn't help. Dimitry, could this be a Clang bug?

As it is accepted by clang 4.0 on amd64 but not with -m32 looks like.

> 
> $ cat a.c
> #include 
> int main() {
> uint64_t n;
> return __atomic_load_n(, __ATOMIC_ACQUIRE);
> }
> 
> $ clang40 -m32 -march=i586 a.c
> /tmp/a-d984ec.o: In function `main':
> a.c:(.text+0x21): undefined reference to `__atomic_load_8'
> clang-4.0: error: linker command failed with exit code 1 (use -v to see 
> invocation)
> 
> full build log: http://sprunge.us/LJdh
> 
> >
> > The diff is wrong as it will break other architectures, ie powerpc.
> 
> And it's not broken already? -latomic isn't passed anywhere.

It is broken for different reasons on platforms that aren't linux.

It used to be you could disable the building the shader cache and not
build the i965 driver to avoid 64 bit atomics in Mesa.  The situation
may have gotten worse in recent releases, not sure.  If you are using
a compiler with __sync but not __atomic builtins it seems to have
gotten worse.

> 
> >
> > commit a6a38a038bd62e6d9558905f00bef81b5e7e6fcc
> > Author: Grazvydas Ignotas 
> > Date:   Fri Mar 31 01:26:25 2017 +0300
> >
> > util/u_atomic: provide 64bit atomics where they're missing
> >
> > attempts to handle powerpc like situations, though not sync
> > builtins being missing entirely.
> >
> >> ---
> >>  configure.ac | 5 +++--
> >>  1 file changed, 3 insertions(+), 2 deletions(-)
> >> 
> >> diff --git a/configure.ac b/configure.ac
> >> index 957d15df8c..5b11941a0c 100644
> >> --- a/configure.ac
> >> +++ b/configure.ac
> >> @@ -403,9 +403,10 @@ AM_CONDITIONAL([SSE41_SUPPORTED], [test 
> >> x$SSE41_SUPPORTED = x1])
> >>  AC_SUBST([SSE41_CFLAGS], $SSE41_CFLAGS)
> >>  
> >>  dnl Check for new-style atomic builtins
> >> -AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
> >> +AC_LINK_IFELSE([AC_LANG_SOURCE([[
> >> +#include 
> >>  int main() {
> >> -int n;
> >> +uint64_t n;
> >>  return __atomic_load_n(, __ATOMIC_ACQUIRE);
> >>  }]])], GCC_ATOMIC_BUILTINS_SUPPORTED=1)
> >>  if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
> >> ___
> >> mesa-dev mailing list
> >> mesa-dev@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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Re: [Mesa-dev] Fix __atomic* builtins detection for Clang

[Jan Beich]

Jan Beich  writes:

> "int" isn't large enough and lack of builtins only manifests at link time.
> This was breaking build on FreeBSD 11.0 i386 with Clang 3.8.0.
>
> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
> `disk_cache_remove':
> disk_cache.c:(.text+0x763): undefined reference to `__atomic_fetch_add_8'
> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
> `cache_put':
> disk_cache.c:(.text+0xabc): undefined reference to `__atomic_fetch_add_8'
> disk_cache.c:(.text+0xec1): undefined reference to `__atomic_fetch_add_8'
> c++: error: linker command failed with exit code 1 (use -v to see invocation)

v2 is https://lists.freedesktop.org/archives/mesa-dev/2017-May/155499.html
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[Mesa-dev] [PATCH 1/2] Clang doesn't have 64bit __atomic* builtins on i386

[Jan Beich]

glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
`disk_cache_remove':
disk_cache.c:(.text+0x763): undefined reference to `__atomic_fetch_add_8'
glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
`cache_put':
disk_cache.c:(.text+0xabc): undefined reference to `__atomic_fetch_add_8'
disk_cache.c:(.text+0xec1): undefined reference to `__atomic_fetch_add_8'
c++: error: linker command failed with exit code 1 (use -v to see invocation)

Signed-off-by: Jan Beich 
---
 configure.ac| 13 -
 src/util/u_atomic.c |  4 
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index ce5301f3e4..08d8879986 100644
--- a/configure.ac
+++ b/configure.ac
@@ -415,13 +415,24 @@ AM_CONDITIONAL([GCC_ATOMIC_BUILTINS_SUPPORTED], [test 
x$GCC_ATOMIC_BUILTINS_SUPP
 
 dnl Check if host supports 64-bit atomics
 dnl note that lack of support usually results in link (not compile) error
-AC_MSG_CHECKING(whether __sync_add_and_fetch_8 is supported)
+save_CFLAGS=$CFLAGS
+if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
+CFLAGS="$CFLAGS -DUSE_GCC_ATOMIC_BUILTINS"
+AC_MSG_CHECKING(whether __atomic_fetch_add_8 is supported)
+else
+AC_MSG_CHECKING(whether __sync_add_and_fetch_8 is supported)
+fi
 AC_LINK_IFELSE([AC_LANG_SOURCE([[
 #include 
 uint64_t v;
 int main() {
+#ifdef USE_GCC_ATOMIC_BUILTINS
+return __atomic_add_fetch(, 1, __ATOMIC_ACQ_REL);
+#else
 return __sync_add_and_fetch(, (uint64_t)1);
+#endif
 }]])], GCC_64BIT_ATOMICS_SUPPORTED=yes, GCC_64BIT_ATOMICS_SUPPORTED=no)
+CFLAGS=$save_CFLAGS
 if test "x$GCC_64BIT_ATOMICS_SUPPORTED" != xyes; then
 DEFINES="$DEFINES -DMISSING_64BIT_ATOMICS"
 fi
diff --git a/src/util/u_atomic.c b/src/util/u_atomic.c
index 44b75fb0c0..691c34cf30 100644
--- a/src/util/u_atomic.c
+++ b/src/util/u_atomic.c
@@ -34,6 +34,7 @@
 
 static pthread_mutex_t sync_mutex = PTHREAD_MUTEX_INITIALIZER;
 
+#ifndef USE_GCC_ATOMIC_BUILTINS
 WEAK uint64_t
 __sync_add_and_fetch_8(uint64_t *ptr, uint64_t val)
 {
@@ -60,6 +61,8 @@ __sync_sub_and_fetch_8(uint64_t *ptr, uint64_t val)
return r;
 }
 
+#else
+
 WEAK uint64_t
 __atomic_fetch_add_8(uint64_t *ptr, uint64_t val, int memorder)
 {
@@ -71,5 +74,6 @@ __atomic_fetch_sub_8(uint64_t *ptr, uint64_t val, int 
memorder)
 {
return __sync_sub_and_fetch(ptr, val);
 }
+#endif /* !USE_GCC_ATOMIC_BUILTINS */
 
 #endif
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[Mesa-dev] [PATCH 2/2] Add prototypes for 64bit atomics fallback

[Jan Beich]

u_atomic.c:67:1: error: no previous prototype for function 
'__atomic_fetch_add_8'
  [-Werror,-Wmissing-prototypes]
__atomic_fetch_add_8(uint64_t *ptr, uint64_t val, int memorder)
^
u_atomic.c:73:1: error: no previous prototype for function 
'__atomic_fetch_sub_8'
  [-Werror,-Wmissing-prototypes]
__atomic_fetch_sub_8(uint64_t *ptr, uint64_t val, int memorder)
^
2 errors generated.

Signed-off-by: Jan Beich 
---
 src/util/u_atomic.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/util/u_atomic.c b/src/util/u_atomic.c
index 691c34cf30..ce600aeeed 100644
--- a/src/util/u_atomic.c
+++ b/src/util/u_atomic.c
@@ -34,6 +34,14 @@
 
 static pthread_mutex_t sync_mutex = PTHREAD_MUTEX_INITIALIZER;
 
+#ifdef USE_GCC_ATOMIC_BUILTINS
+uint64_t __atomic_fetch_add_8(uint64_t *ptr, uint64_t val, int memorder);
+uint64_t __atomic_fetch_sub_8(uint64_t *ptr, uint64_t val, int memorder);
+#else
+uint64_t __sync_add_and_fetch_8(uint64_t *ptr, uint64_t val);
+uint64_t __sync_sub_and_fetch_8(uint64_t *ptr, uint64_t val);
+#endif
+
 #ifndef USE_GCC_ATOMIC_BUILTINS
 WEAK uint64_t
 __sync_add_and_fetch_8(uint64_t *ptr, uint64_t val)
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Re: [Mesa-dev] Fix __atomic* builtins detection for Clang

[Jan Beich]

Jonathan Gray  writes:

> commit a6a38a038bd62e6d9558905f00bef81b5e7e6fcc
> Author: Grazvydas Ignotas 
> Date:   Fri Mar 31 01:26:25 2017 +0300
>
> util/u_atomic: provide 64bit atomics where they're missing
>
> attempts to handle powerpc like situations, though not sync
> builtins being missing entirely.

Not ready for Clang on i386 which has __sync* but not __atomic*.
Teaching configure.ac about 64bit __atomic* isn't enough.

  #include 
  uint64_t v;
  int main() {
  #ifdef USE_GCC_ATOMIC_BUILTINS
  return __atomic_add_fetch(, 1, __ATOMIC_ACQ_REL);
  #else
  return __sync_add_and_fetch(, (uint64_t)1);
  #endif
  }

leads to

  u_atomic.c:38:1: error: conflicting types for '__sync_add_and_fetch_8'
  __sync_add_and_fetch_8(uint64_t *ptr, uint64_t val)
  ^
  u_atomic.c:38:1: note: '__sync_add_and_fetch_8' is a builtin with type 'long 
long (volatile long long *, long long, ...)'
  u_atomic.c:38:1: error: definition of builtin function 
'__sync_add_and_fetch_8'
  __sync_add_and_fetch_8(uint64_t *ptr, uint64_t val)
  ^
  u_atomic.c:51:1: error: conflicting types for '__sync_sub_and_fetch_8'
  __sync_sub_and_fetch_8(uint64_t *ptr, uint64_t val)
  ^
  u_atomic.c:51:1: note: '__sync_sub_and_fetch_8' is a builtin with type 'long 
long (volatile long long *, long long, ...)'
  u_atomic.c:51:1: error: definition of builtin function 
'__sync_sub_and_fetch_8'
  __sync_sub_and_fetch_8(uint64_t *ptr, uint64_t val)
  ^
  u_atomic.c:64:1: error: no previous prototype for function 
'__atomic_fetch_add_8' [-Werror,-Wmissing-prototypes]
  __atomic_fetch_add_8(uint64_t *ptr, uint64_t val, int memorder)
  ^
  u_atomic.c:70:1: error: no previous prototype for function 
'__atomic_fetch_sub_8' [-Werror,-Wmissing-prototypes]
  __atomic_fetch_sub_8(uint64_t *ptr, uint64_t val, int memorder)
  ^
  6 errors generated.
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[Mesa-dev] [Bug 100259] [EGL] [GBM] undefined reference to `gbm_bo_create_with_modifiers'

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100259

Laurent carlier  changed:

   What|Removed |Added

 Status|RESOLVED|REOPENED
 Resolution|FIXED   |---

--- Comment #16 from Laurent carlier  ---
Still broken here with ArchLinux in a multilib chroot:

Making install in egl
make[3]: Entering directory '/build/lib32-mesa/src/mesa-17.1.0/src/egl'
make  install-am
make[4]: Entering directory '/build/lib32-mesa/src/mesa-17.1.0/src/egl'
make[5]: Entering directory '/build/lib32-mesa/src/mesa-17.1.0/src/egl'
 /usr/bin/mkdir -p '/build/lib32-mesa/src/fakeinstall/usr/include/EGL'
 /usr/bin/mkdir -p '/build/lib32-mesa/src/fakeinstall/usr/include/KHR'
 /usr/bin/mkdir -p '/build/lib32-mesa/src/fakeinstall/usr/lib32/pkgconfig'
 /usr/bin/mkdir -p '/build/lib32-mesa/src/fakeinstall/usr/lib32'
 /bin/sh ../../libtool   --mode=install /usr/bin/install -c   libEGL_mesa.la
'/build/lib32-mesa/src/fakeinstall/usr/lib32'
 /usr/bin/mkdir -p
'/build/lib32-mesa/src/fakeinstall/usr/share/glvnd/egl_vendor.d'
 /usr/bin/install -c -m 644 ../../include/KHR/khrplatform.h
'/build/lib32-mesa/src/fakeinstall/usr/include/KHR'
 /usr/bin/install -c -m 644 ../../include/EGL/eglext.h ../../include/EGL/egl.h
../../include/EGL/eglextchromium.h ../../include/EGL/eglmesaext.h
../../include/EGL/eglplatform.h
'/build/lib32-mesa/src/fakeinstall/usr/include/EGL'
 /usr/bin/install -c -m 644 main/50_mesa.json
'/build/lib32-mesa/src/fakeinstall/usr/share/glvnd/egl_vendor.d'
 /usr/bin/install -c -m 644 main/egl.pc
'/build/lib32-mesa/src/fakeinstall/usr/lib32/pkgconfig'
libtool: warning: relinking 'libEGL_mesa.la'
libtool: install: (cd /build/lib32-mesa/src/mesa-17.1.0/src/egl; /bin/sh
"/build/lib32-mesa/src/mesa-17.1.0/libtool"  --silent --tag CC --mode=relink
gcc -m32 -I../../include -I../../src/egl/main -I../../src/gbm/main -I../../src
-D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS
-D_GNU_SOURCE -DUSE_SSE41 -DUSE_GCC_ATOMIC_BUILTINS -DNDEBUG
-DTEXTURE_FLOAT_ENABLED -DUSE_X86_ASM -DUSE_MMX_ASM -DUSE_3DNOW_ASM
-DUSE_SSE_ASM -DHAVE_XLOCALE_H -DHAVE_SYS_SYSCTL_H -DHAVE_STRTOF
-DHAVE_MKOSTEMP -DHAVE_DLOPEN -DHAVE_DL_ITERATE_PHDR -DHAVE_POSIX_MEMALIGN
-DHAVE_GALLIUM_EXTRA_HUD=1 -DHAVE_LIBSENSORS=1 -DUSE_LIBGLVND=1 -DHAVE_LIBDRM
-DGLX_USE_DRM -DGLX_INDIRECT_RENDERING -DGLX_DIRECT_RENDERING -DGLX_USE_TLS
-DHAVE_DRI3 -DENABLE_SHADER_CACHE -DHAVE_MINCORE -DHAVE_ST_VDPAU
-DHAVE_LLVM=0x0400 -DMESA_LLVM_VERSION_PATCH=0 -fvisibility=hidden
-I/usr/include/libdrm -D_EGL_NATIVE_PLATFORM=_EGL_PLATFORM_X11
-DHAVE_X11_PLATFORM -DHAVE_WAYLAND_PLATFORM -DHAVE_DRM_PLATFORM
-I../../src/loader -I../../src/egl/drivers/dri2 -I../../src/gbm/backends/dri
-I../../src/egl/wayland/wayland-egl -I../../src/egl/wayland/wayland-drm
-I../../src/egl/wayland/wayland-drm
-DDEFAULT_DRIVER_DIR=\"/usr/lib32/xorg/modules/dri\"
-D_EGL_BUILT_IN_DRIVER_DRI2 -march=x86-64 -mtune=generic -O2 -pipe
-fstack-protector-strong -Wall -std=c99 -Werror=implicit-function-declaration
-Werror=missing-prototypes -fno-math-errno -fno-trapping-math -no-undefined
-version-number 0 -Wl,-Bsymbolic -Wl,--gc-sections -Wl,--no-undefined
-Wl,-O1,--sort-common,--as-needed,-z,relro -o libEGL_mesa.la -rpath /usr/lib32
main/eglglvnd.lo main/egldispatchstubs.lo g_egldispatchstubs.lo
libEGL_common.la -inst-prefix-dir /build/lib32-mesa/src/fakeinstall)
./.libs/libEGL_common.a(platform_drm.o): In function `get_back_bo':
platform_drm.c:(.text+0x1dd): undefined reference to
`gbm_bo_create_with_modifiers'
collect2: error: ld returned 1 exit status
libtool:   error: error: relink 'libEGL_mesa.la' with the above command before
installing it
make[5]: *** [Makefile:969: install-libLTLIBRARIES] Error 1
make[5]: Leaving directory '/build/lib32-mesa/src/mesa-17.1.0/src/egl'
make[4]: *** [Makefile:1490: install-am] Error 2
make[4]: Leaving directory '/build/lib32-mesa/src/mesa-17.1.0/src/egl'
make[3]: *** [Makefile:1484: install] Error 2
make[3]: Leaving directory '/build/lib32-mesa/src/mesa-17.1.0/src/egl'
make[2]: *** [Makefile:851: install-recursive] Error 1
make[2]: Leaving directory '/build/lib32-mesa/src/mesa-17.1.0/src'
make[1]: *** [Makefile:1008: install] Error 2
make[1]: Leaving directory '/build/lib32-mesa/src/mesa-17.1.0/src'
make: *** [Makefile:642: install-recursive] Error 1

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[Mesa-dev] [Bug 101028] Cannot run OpenGL applications on a remote XServer without +iglx

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101028

Michel Dänzer  changed:

   What|Removed |Added

 Resolution|--- |NOTABUG
 QA Contact|mesa-dev@lists.freedesktop. |xorg-t...@lists.x.org
   |org |
Product|Mesa|xorg
  Component|Drivers/Gallium/swr |Server/Ext/GLX
   Assignee|mesa-dev@lists.freedesktop. |xorg-t...@lists.x.org
   |org |
 Status|NEW |RESOLVED

--- Comment #1 from Michel Dänzer  ---
Current versions of Xorg disable GLX indirect rendering by default. This is
intended behaviour.

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Re: [Mesa-dev] Fix __atomic* builtins detection for Clang

[Jan Beich]

Jonathan Gray  writes:

> On Sat, May 13, 2017 at 02:22:30AM +0200, Jan Beich wrote:
>
>> "int" isn't large enough and lack of builtins only manifests at link time.
>> This was breaking build on FreeBSD 11.0 i386 with Clang 3.8.0.
>> 
>> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
>> `disk_cache_remove':
>> disk_cache.c:(.text+0x763): undefined reference to `__atomic_fetch_add_8'
>> glsl/.libs/libstandalone.a(libmesautil_la-disk_cache.o): In function 
>> `cache_put':
>> disk_cache.c:(.text+0xabc): undefined reference to `__atomic_fetch_add_8'
>> disk_cache.c:(.text+0xec1): undefined reference to `__atomic_fetch_add_8'
>> c++: error: linker command failed with exit code 1 (use -v to see invocation)
>
> You should be building with -march=i586 on i386 for CX8.

-march=i586 doesn't help. Dimitry, could this be a Clang bug?

$ cat a.c
#include 
int main() {
uint64_t n;
return __atomic_load_n(, __ATOMIC_ACQUIRE);
}

$ clang40 -m32 -march=i586 a.c
/tmp/a-d984ec.o: In function `main':
a.c:(.text+0x21): undefined reference to `__atomic_load_8'
clang-4.0: error: linker command failed with exit code 1 (use -v to see 
invocation)

full build log: http://sprunge.us/LJdh

>
> The diff is wrong as it will break other architectures, ie powerpc.

And it's not broken already? -latomic isn't passed anywhere.

>
> commit a6a38a038bd62e6d9558905f00bef81b5e7e6fcc
> Author: Grazvydas Ignotas 
> Date:   Fri Mar 31 01:26:25 2017 +0300
>
> util/u_atomic: provide 64bit atomics where they're missing
>
> attempts to handle powerpc like situations, though not sync
> builtins being missing entirely.
>
>> ---
>>  configure.ac | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>> 
>> diff --git a/configure.ac b/configure.ac
>> index 957d15df8c..5b11941a0c 100644
>> --- a/configure.ac
>> +++ b/configure.ac
>> @@ -403,9 +403,10 @@ AM_CONDITIONAL([SSE41_SUPPORTED], [test 
>> x$SSE41_SUPPORTED = x1])
>>  AC_SUBST([SSE41_CFLAGS], $SSE41_CFLAGS)
>>  
>>  dnl Check for new-style atomic builtins
>> -AC_COMPILE_IFELSE([AC_LANG_SOURCE([[
>> +AC_LINK_IFELSE([AC_LANG_SOURCE([[
>> +#include 
>>  int main() {
>> -int n;
>> +uint64_t n;
>>  return __atomic_load_n(, __ATOMIC_ACQUIRE);
>>  }]])], GCC_ATOMIC_BUILTINS_SUPPORTED=1)
>>  if test "x$GCC_ATOMIC_BUILTINS_SUPPORTED" = x1; then
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Re: [Mesa-dev] [PATCH] mesa: don't crash in KHR_no_error uniform variants when location == -1

[Timothy Arceri]

My commit message seems to have gone missing. By -1 is allowed so that 
inactive uniforms don't cause the app to throw an error.


On 13/05/17 16:31, Timothy Arceri wrote:

---
  src/mesa/main/uniform_query.cpp | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 0e02a76..5f38aa5 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -904,20 +904,23 @@ validate_uniform(GLint location, GLsizei count, const 
GLvoid *values,
  extern "C" void
  _mesa_uniform(GLint location, GLsizei count, const GLvoid *values,
struct gl_context *ctx, struct gl_shader_program *shProg,
enum glsl_base_type basicType, unsigned src_components)
  {
 unsigned offset;
 int size_mul = glsl_base_type_is_64bit(basicType) ? 2 : 1;
  
 struct gl_uniform_storage *uni;

 if (_mesa_is_no_error_enabled(ctx)) {
+  if (location == -1)
+ return;
+
uni = shProg->UniformRemapTable[location];
  
/* The array index specified by the uniform location is just the

 * uniform location minus the base location of of the uniform.
 */
assert(uni->array_elements > 0 || location == (int)uni->remap_location);
offset = location - uni->remap_location;
 } else {
uni = validate_uniform(location, count, values, , ctx, shProg,
   basicType, src_components);


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[Mesa-dev] [Bug 101028] Cannot run OpenGL applications on a remote XServer without +iglx

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101028

Bug ID: 101028
   Summary: Cannot run OpenGL applications on a remote XServer
without +iglx
   Product: Mesa
   Version: unspecified
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/swr
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: suic...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

When I try to run glxgears on a remote Cygwin / X server I get this error 

suici@HP-Pavilion-g7:~$ LIBGL_DEBUG=verbose DISPLAY=:0 glxgears
libGL: OpenDriver: trying /usr/lib/x86_64-linux-gnu/dri/tls/swrast_dri.so
libGL: OpenDriver: trying /usr/lib/x86_64-linux-gnu/dri/swrast_dri.so
libGL: Can't open configuration file /home/suici/.drirc: No such file or
directory.
libGL: Can't open configuration file /home/suici/.drirc: No such file or
directory.
libGL error: No matching fbConfigs or visuals found
libGL error: failed to load driver: swrast
X Error of failed request:  BadValue (integer parameter out of range for
operation)
  Major opcode of failed request:  149 (GLX)
  Minor opcode of failed request:  3 (X_GLXCreateContext)
  Value in failed request:  0x0
  Serial number of failed request:  28
  Current serial number in output stream:  30

I'm using Windows 10 WSL but the same error also occurs if I run it from a
remote Linux machine. If I use +iglx the error goes but it only supports GL
1.4.

GPU : Radeon HD 7640G

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[Mesa-dev] [PATCH] mesa: don't crash in KHR_no_error uniform variants when location == -1

[Timothy Arceri]

---
 src/mesa/main/uniform_query.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 0e02a76..5f38aa5 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -904,20 +904,23 @@ validate_uniform(GLint location, GLsizei count, const 
GLvoid *values,
 extern "C" void
 _mesa_uniform(GLint location, GLsizei count, const GLvoid *values,
   struct gl_context *ctx, struct gl_shader_program *shProg,
   enum glsl_base_type basicType, unsigned src_components)
 {
unsigned offset;
int size_mul = glsl_base_type_is_64bit(basicType) ? 2 : 1;
 
struct gl_uniform_storage *uni;
if (_mesa_is_no_error_enabled(ctx)) {
+  if (location == -1)
+ return;
+
   uni = shProg->UniformRemapTable[location];
 
   /* The array index specified by the uniform location is just the
* uniform location minus the base location of of the uniform.
*/
   assert(uni->array_elements > 0 || location == (int)uni->remap_location);
   offset = location - uni->remap_location;
} else {
   uni = validate_uniform(location, count, values, , ctx, shProg,
  basicType, src_components);
-- 
2.9.3

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