date:20180322

Re: [Mesa-dev] [PATCH] mesa: readpixels add support for GL_HALF_FLOAT

2018-03-22 Thread Lin, Johnson

So the solution will be query if EXT_color_buffer_half_float is supported?

-Original Message-
From: Palli, Tapani 
Sent: Friday, March 23, 2018 1:53 PM
To: Lin, Johnson ; Alejandro Piñeiro 
; mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH] mesa: readpixels add support for GL_HALF_FLOAT


On 03/22/2018 07:53 AM, Tapani Pälli wrote:
> 
> 
> On 03/22/2018 04:43 AM, Lin, Johnson wrote:
>> Hi,  Thanks for the comments.
>>
>> I just noticed it does not check the extension support for 
>> EXT_color_buffer_float neither?
> 
> That is probably because it is enabled as 'dummy_true' (see
> extensions_table.h) so it's always enabled on any driver. I wonder if 
> we can just go and do the same for EXT_color_buffer_half_float? Is 
> there any driver that would not support this?

Took a brief look and no, we can't simply toggle it on. There is also some API 
interaction defined by the spec that would need to be enabled, querying 
component type via glGetFramebufferAttachmentParameteriv and so on.

> 
>> -Original Message-
>> From: Palli, Tapani
>> Sent: Wednesday, March 21, 2018 6:57 PM
>> To: Alejandro Piñeiro ; Lin, Johnson 
>> ; mesa-dev@lists.freedesktop.org
>> Subject: Re: [Mesa-dev] [PATCH] mesa: readpixels add support for 
>> GL_HALF_FLOAT
>>
>>
>>
>> On 21.03.2018 12:45, Tapani Pälli wrote:
>>>
>>>
>>> On 21.03.2018 08:52, Alejandro Piñeiro wrote:
 On 21/03/18 06:57, Lin Johnson wrote:
> Ext_color_buffer_half_float is using type GL_HALF_FLOAT and 
> data_type GL_FLOAT. This fix Android CTS test 
> android.view.cts.PixelCopyTest #TestWindowProducerCopyToRGBA16F
>
> Signed-off-by: Lin Johnson 
> ---
>    src/mesa/main/readpix.c | 2 ++
>    1 file changed, 2 insertions(+)
>
> diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c 
> index 6ce340ddf9bb..51331dd095ab 100644
> --- a/src/mesa/main/readpix.c
> +++ b/src/mesa/main/readpix.c
> @@ -920,6 +920,8 @@ read_pixels_es3_error_check(GLenum format, 
> GLenum type,
>   case GL_RGBA:
>  if (type == GL_FLOAT && data_type == GL_FLOAT)
>     return GL_NO_ERROR; /* EXT_color_buffer_float */
> +  if (type == GL_HALF_FLOAT && data_type == GL_FLOAT)
> + return GL_NO_ERROR; /* EXT_color_buffer_half_float */

 If this combination is allowed thanks to that extension, what would 
 happen if that extension is not supported? shouldn't include a 
 extension check? Or that is checked in a different place?
>>>
>>> I was thinking the same. Having seen the test it does not seem to 
>>> make any kind of checks what is supported (like asking for 
>>> extension, or maybe asking for GL_IMPLEMENTATION_COLOR_READ_TYPE)  
>>> but attempts glReadPixels using GL_HALF_FLOAT type, I think it 
>>> should verify first that such reads are supported. Currently we 
>>> don't seem to support this extension.
>>
>> ... but probably support the functionality (OpenGL ES 3.2), so maybe 
>> some checks needed for ES version (?)
>>
>>
>>>
>>>
>  if (type == GL_UNSIGNED_BYTE && data_type ==
> GL_UNSIGNED_NORMALIZED)
>     return GL_NO_ERROR;
>  if (internalFormat == GL_RGB10_A2 &&


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Re: [Mesa-dev] [PATCH] mesa: readpixels add support for GL_HALF_FLOAT

2018-03-22 Thread Tapani Pälli



On 03/22/2018 07:53 AM, Tapani Pälli wrote:



On 03/22/2018 04:43 AM, Lin, Johnson wrote:

Hi,  Thanks for the comments.

I just noticed it does not check the extension support for 
EXT_color_buffer_float neither?


That is probably because it is enabled as 'dummy_true' (see 
extensions_table.h) so it's always enabled on any driver. I wonder if we 
can just go and do the same for EXT_color_buffer_half_float? Is there 
any driver that would not support this?


Took a brief look and no, we can't simply toggle it on. There is also 
some API interaction defined by the spec that would need to be enabled, 
querying component type via glGetFramebufferAttachmentParameteriv and so on.





-Original Message-
From: Palli, Tapani
Sent: Wednesday, March 21, 2018 6:57 PM
To: Alejandro Piñeiro ; Lin, Johnson 
; mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH] mesa: readpixels add support for 
GL_HALF_FLOAT




On 21.03.2018 12:45, Tapani Pälli wrote:



On 21.03.2018 08:52, Alejandro Piñeiro wrote:

On 21/03/18 06:57, Lin Johnson wrote:

Ext_color_buffer_half_float is using type GL_HALF_FLOAT and
data_type GL_FLOAT. This fix Android CTS test
android.view.cts.PixelCopyTest #TestWindowProducerCopyToRGBA16F

Signed-off-by: Lin Johnson 
---
   src/mesa/main/readpix.c | 2 ++
   1 file changed, 2 insertions(+)

diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c index
6ce340ddf9bb..51331dd095ab 100644
--- a/src/mesa/main/readpix.c
+++ b/src/mesa/main/readpix.c
@@ -920,6 +920,8 @@ read_pixels_es3_error_check(GLenum format,
GLenum type,
  case GL_RGBA:
 if (type == GL_FLOAT && data_type == GL_FLOAT)
    return GL_NO_ERROR; /* EXT_color_buffer_float */
+  if (type == GL_HALF_FLOAT && data_type == GL_FLOAT)
+ return GL_NO_ERROR; /* EXT_color_buffer_half_float */


If this combination is allowed thanks to that extension, what would
happen if that extension is not supported? shouldn't include a
extension check? Or that is checked in a different place?


I was thinking the same. Having seen the test it does not seem to make
any kind of checks what is supported (like asking for extension, or
maybe asking for GL_IMPLEMENTATION_COLOR_READ_TYPE)  but attempts
glReadPixels using GL_HALF_FLOAT type, I think it should verify first
that such reads are supported. Currently we don't seem to support this
extension.


... but probably support the functionality (OpenGL ES 3.2), so maybe 
some checks needed for ES version (?)







 if (type == GL_UNSIGNED_BYTE && data_type ==
GL_UNSIGNED_NORMALIZED)
    return GL_NO_ERROR;
 if (internalFormat == GL_RGB10_A2 &&



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Re: [Mesa-dev] [PATCH v1 0/7] Implement commont gralloc_handle_t in libdrm

2018-03-22 Thread Tomasz Figa

On Fri, Mar 23, 2018 at 11:43 AM, Chih-Wei Huang  wrote:
> 2018-03-22 16:23 GMT+08:00 Tomasz Figa :
>> Hi Chih-Wei,
>>
>> On Thu, Feb 22, 2018 at 2:53 PM, Chih-Wei Huang  wrote:
>>> 2018-02-21 3:03 GMT+08:00 Rob Herring :

 Perhaps worth revisiting. Given we've failed to progress at all since
 then may change opinions some. We already have to handle multiple
 opens share the same pipe_screen, so I don't think reusing the fd buys
 us anything.

 Maybe we're close to the point of removing the flink name support too.
 The android-x86 folks have been working to get dma-bufs working.
 Chih-Wei, any comments on this?
>>>
>>> Ah! Sorry. I didn't catch or understand the details.
>>> Did you mean the attempts to use drm_hwcomposer
>>> in android-x86?
>>> My understanding so far is most x86 GPUs won't work
>>> except some very limited models.
>>> It's due to kernel driver issues which may never be solved.
>>> So we can't drop the flink name support.
>>> Please correct me if I am wrong.
>>
>> Could you elaborate a bit more on those GPUs that won't work and
>> corresponding driver issues? We're running cros_gralloc on Intel and
>> AMD GPUs, with DMA-buf and render-node only setup and we haven't seen
>> any problems.
>
> Hi Tomasz,
> I remember (in our previous discussion) you said
> CrOS uses your own hwcomposer (proprietary?) so
> the story may be different.
>
> What we have tried is gbm_gralloc + drm_hwcomposer
> and I reported the issues here:
> https://lists.freedesktop.org/archives/dri-devel/2017-September/153580.html
>
> Sorry I didn't make more tests recently.
> I CC Mauro to comment. He should have made more tests
> with newer kernel and mesa.

Thanks for clarification.

This sounds like something that could be fixed by making sure DMA-buf
support is properly implemented in gralloc and hwcomposer used by
android-x86. I can help figuring this out, if anyone would be
interested in driving this on your side. FYI, I'm UTC+9 time zone, so
based on .tw domain in your email, it should be possible for us to
communicate easily, for example by IRC.

If i915 DRI driver is also needed, it would need wiring support for
DMA-buf as well, but it shouldn't be too hard as mentioned earlier

Best regards,
Tomasz
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[Mesa-dev] [PATCH 2/2] st/glsl_to_nir: correctly handle arrays packed across multiple vars

2018-03-22 Thread Timothy Arceri

Fixes piglit test:
tests/spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-interleave-range.shader_test
---
 src/mesa/state_tracker/st_glsl_to_nir.cpp | 24 +++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index e0467f205d3..4ded4ec60f5 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -133,6 +133,7 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
const int base = stage == MESA_SHADER_FRAGMENT ?
   (int) FRAG_RESULT_DATA0 : (int) VARYING_SLOT_VAR0;
 
+   int UNUSED last_loc = 0;
nir_foreach_variable(var, var_list) {
 
   const struct glsl_type *type = var->type;
@@ -164,8 +165,29 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
* we may have already have processed this location.
*/
   if (processed) {
- var->data.driver_location = assigned_locations[var->data.location];
+ unsigned driver_location = assigned_locations[var->data.location];
+ var->data.driver_location = driver_location;
  *size += type_size(type);
+
+ /* An array may be packed such that is crosses multiple other arrays
+  * or variables, we need to make sure we have allocated the elements
+  * consecutively if the previously proccessed var was shorter than
+  * the current array we are processing.
+  *
+  * NOTE: The code below assumes the var list is ordered in ascending
+  * location order.
+  */
+ assert(last_loc <= var->data.location);
+ last_loc = var->data.location;
+ unsigned last_slot_location = driver_location + var_size;
+ if (last_slot_location > location) {
+unsigned num_unallocated_slots = last_slot_location - location;
+unsigned first_unallocated_slot = var_size - num_unallocated_slots;
+for (unsigned i = first_unallocated_slot; i < 
num_unallocated_slots; i++) {
+   assigned_locations[var->data.location + i] = location;
+   location++;
+}
+ }
  continue;
   }
 
-- 
2.14.3

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[Mesa-dev] [PATCH 1/2] radeonsi/nir: fix input processing for packed varyings

2018-03-22 Thread Timothy Arceri

The location was only being incremented the first time we processed a
location. This meant we would incorrectly skip some elements of
an array if the first element was packed and proccessed previously
but other elements were not.
---
 src/gallium/drivers/radeonsi/si_shader_nir.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index ed9f90a6a3a..4e15eeae6b9 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -911,7 +911,7 @@ bool si_nir_build_llvm(struct si_shader_context *ctx, 
struct nir_shader *nir)
/* Packed components share the same location so 
skip
 * them if we have already processed the 
location.
 */
-   if (processed_inputs & ((uint64_t)1 << loc)) {
+   if (processed_inputs & ((uint64_t)1 << (loc + 
i))) {
input_idx += 4;
continue;
}
@@ -929,8 +929,7 @@ bool si_nir_build_llvm(struct si_shader_context *ctx, 
struct nir_shader *nir)
bitcast_inputs(ctx, data, input_idx);
}
 
-   processed_inputs |= ((uint64_t)1 << loc);
-   loc++;
+   processed_inputs |= ((uint64_t)1 << (loc + i));
input_idx += 4;
}
}
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 1/2] radv: add support for Vega12

2018-03-22 Thread Bas Nieuwenhuizen

Reviewed-by: Bas Nieuwenhuizen 

for the series.

On Thu, Mar 22, 2018 at 4:41 PM, Samuel Pitoiset
 wrote:
> Based on RadeonSI. Untested.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_device.c   | 5 -
>  src/amd/vulkan/radv_pipeline.c | 1 +
>  src/amd/vulkan/si_cmd_buffer.c | 1 +
>  3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 36ba0c3833..e9122072a8 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -101,6 +101,7 @@ radv_get_device_name(enum radeon_family family, char 
> *name, size_t name_len)
> case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
> case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
> case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
> +   case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
> case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
> default: chip_string = "AMD RADV unknown"; break;
> }
> @@ -290,7 +291,8 @@ radv_physical_device_init(struct radv_physical_device 
> *device,
> if (device->rad_info.family == CHIP_STONEY ||
> device->rad_info.chip_class >= GFX9) {
> device->has_rbplus = true;
> -   device->rbplus_allowed = device->rad_info.family == 
> CHIP_STONEY;
> +   device->rbplus_allowed = device->rad_info.family == 
> CHIP_STONEY ||
> +device->rad_info.family == 
> CHIP_VEGA12;
> }
>
> /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
> @@ -1174,6 +1176,7 @@ radv_device_init_gs_info(struct radv_device *device)
> case CHIP_POLARIS11:
> case CHIP_POLARIS12:
> case CHIP_VEGA10:
> +   case CHIP_VEGA12:
> case CHIP_RAVEN:
> device->gs_table_depth = 32;
> return;
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index dd5baec117..af1ea395d3 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -2155,6 +2155,7 @@ radv_pipeline_generate_binning_state(struct 
> radeon_winsys_cs *cs,
>
> switch (pipeline->device->physical_device->rad_info.family) {
> case CHIP_VEGA10:
> +   case CHIP_VEGA12:
> context_states_per_bin = 1;
> persistent_states_per_bin = 1;
> fpovs_per_batch = 63;
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index 06e8442100..0970eff103 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -509,6 +509,7 @@ si_emit_config(struct radv_physical_device 
> *physical_device,
>
> switch (physical_device->rad_info.family) {
> case CHIP_VEGA10:
> +   case CHIP_VEGA12:
> pc_lines = 4096;
> break;
> case CHIP_RAVEN:
> --
> 2.16.2
>
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[Mesa-dev] [Bug 105699] s3tc fbo-generatemipmap-formats tests fail unless optimized

2018-03-22 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=105699

Roland Scheidegger  changed:

   What|Removed |Added

   Assignee|srol...@vmware.com  |mesa-dev@lists.freedesktop.
   ||org

--- Comment #1 from Roland Scheidegger  ---
Not sure if this is intel specific or not, but either way I don't feel
responsible for this bug.

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[Mesa-dev] [Bug 105699] s3tc fbo-generatemipmap-formats tests fail unless optimized

2018-03-22 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=105699

Bug ID: 105699
   Summary: s3tc fbo-generatemipmap-formats tests fail unless
optimized
   Product: Mesa
   Version: unspecified
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: srol...@vmware.com
  Reporter: mark.a.ja...@intel.com
QA Contact: mesa-dev@lists.freedesktop.org

The following piglit tests fail on all Intel hardware, with -O0:

piglit.spec.ext_texture_compression_s3tc.fbo-generatemipmap-formats
piglit.spec.ext_texture_srgb.fbo-generatemipmap-formats-s3tc

EG:
piglit/bin/fbo-generatemipmap-formats GL_EXT_texture_compression_s3tc -auto
-fbo
Using test set: GL_EXT_texture_compression_s3tc
Testing GL_COMPRESSED_RGB_S3TC_DXT1_EXT
PIGLIT: {"subtest": {"GL_COMPRESSED_RGB_S3TC_DXT1_EXT" : "pass"}}
Testing GL_COMPRESSED_RGBA_S3TC_DXT1_EXT
PIGLIT: {"subtest": {"GL_COMPRESSED_RGBA_S3TC_DXT1_EXT" : "pass"}}
Testing GL_COMPRESSED_RGBA_S3TC_DXT3_EXT
PIGLIT: {"subtest": {"GL_COMPRESSED_RGBA_S3TC_DXT3_EXT" : "pass"}}
Testing GL_COMPRESSED_RGBA_S3TC_DXT5_EXT
PIGLIT: {"subtest": {"GL_COMPRESSED_RGBA_S3TC_DXT5_EXT" : "pass"}}
Testing GL_COMPRESSED_RGB_S3TC_DXT1_EXT (NPOT)
PIGLIT: {"subtest": {"GL_COMPRESSED_RGB_S3TC_DXT1_EXT NPOT" : "pass"}}
Testing GL_COMPRESSED_RGBA_S3TC_DXT1_EXT (NPOT)
PIGLIT: {"subtest": {"GL_COMPRESSED_RGBA_S3TC_DXT1_EXT NPOT" : "pass"}}
Testing GL_COMPRESSED_RGBA_S3TC_DXT3_EXT (NPOT)
PIGLIT: {"subtest": {"GL_COMPRESSED_RGBA_S3TC_DXT3_EXT NPOT" : "pass"}}
Testing GL_COMPRESSED_RGBA_S3TC_DXT5_EXT (NPOT)
Probe color at (439,4)
  Expected: 0 255 0 63
  Observed: 0 255 0 255
PIGLIT: {"subtest": {"GL_COMPRESSED_RGBA_S3TC_DXT5_EXT NPOT" : "fail"}}
PIGLIT: {"result": "fail" }

When Mesa is compiled with -O2, the tests pass.

You would expect optimizations to *break* tests, not fix them.  ¯\_(ツ)_/¯

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Re: [Mesa-dev] [RFC] Mesa 17.3.x release problems and process improvements

2018-03-22 Thread Dylan Baker

Quoting Ilia Mirkin (2018-03-22 15:16:18)
> On Thu, Mar 22, 2018 at 6:00 PM, Dylan Baker  wrote:
> > Quoting Ilia Mirkin (2018-03-21 17:39:14)
> >> Just one bit of feedback, for the rest I either agree or have no opinion:
> >>
> >> On Wed, Mar 21, 2018 at 8:28 PM, Emil Velikov  
> >> wrote:
> >> >  * unfit and late nominations:
> >> > * any rejections that are unfit based on the existing criteria can
> >> >   be merged as long as:
> >> >* subsystem specific patches are approved by the team
> >> >  maintainer(s).
> >> >* patches that cover multiple subsystems are approved by 50%+1
> >> >  of the maintainers of the affected subsystems.
> >>
> >> I don't think 50% + 1 is workable. That would mean for a core mesa
> >> patch, one would have to get like 5+ people to ack it. Seems like a
> >> lot. (And I suspect will lead to debates about how to count "affected"
> >> subsystems.) IMHO 2 is enough, i.e. the maintainer that wants it, and
> >> another maintainer who thinks it's reasonable.
> >
> > What do we do if two maintainers say yes, but it breaks another driver? I'm
> > asking because we've had these sort of problems in the past.
> 
> An explicit NAK from any maintainer kills the whole thing. I believe
> this should apply to all patches, not just these "unfit and late
> nominations" category. At least that's what makes sense to me. Ideally
> the two warring factions will come to some agreement, but it's not the
> release manager's responsibility to resolve these conflicts.
> 
>   -ilia

That makes sense to me.


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Re: [Mesa-dev] [PATCH] radv: disable binning state in some situations

2018-03-22 Thread Bas Nieuwenhuizen

I'd rather we figure out a story of when it is faster. I tried a lot
of stuff with the currently available games, and getting it
consistently faster was difficult.

So if you have a raven ridge, feel free to try something, but I'm not
really a fan of copying it blindly without understanding it.

On Thu, Mar 22, 2018 at 6:40 PM, Samuel Pitoiset
 wrote:
> This is imported from RadeonSI/ADMVLK. That might or might not
> improve performance. Anyway, it's still disabled by default.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_pipeline.c | 56 
> +-
>  1 file changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index dd5baec117..6c0d552c81 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -2134,6 +2134,59 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, 
> const VkGraphicsPipelineCr
> return extent;
>  }
>
> +static bool
> +radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo 
> *pCreateInfo)
> +{
> +   assert(pCreateInfo);
> +   return pCreateInfo->depthTestEnable &&
> +  pCreateInfo->depthWriteEnable &&
> +  pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
> +}
> +
> +static bool
> +radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo 
> *pCreateInfo)
> +{
> +   assert(pCreateInfo);
> +   return pCreateInfo->stencilTestEnable &&
> +  (pCreateInfo->front.failOp != VK_STENCIL_OP_KEEP ||
> +   pCreateInfo->front.passOp != VK_STENCIL_OP_KEEP ||
> +   pCreateInfo->front.depthFailOp != VK_STENCIL_OP_KEEP ||
> +   pCreateInfo->back.failOp != VK_STENCIL_OP_KEEP ||
> +   pCreateInfo->back.passOp != VK_STENCIL_OP_KEEP ||
> +   pCreateInfo->back.depthFailOp != VK_STENCIL_OP_KEEP);
> +}
> +
> +static bool
> +radv_should_enable_pbb(struct radv_pipeline *pipeline,
> +  const VkGraphicsPipelineCreateInfo *pCreateInfo)
> +{
> +   RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
> +   struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
> +   struct radv_shader_variant *ps = 
> pipeline->shaders[MESA_SHADER_FRAGMENT];
> +
> +   if (!pipeline->device->pbb_allowed)
> +   return false;
> +
> +   /* Whether we can disable binning state based on the pixel shader, 
> MSAA
> +* states and depth/stencil writes.
> +*/
> +   bool ps_can_kill = ps->info.fs.can_discard ||
> +  ps->info.info.ps.writes_sample_mask ||
> +  pCreateInfo->pMultisampleState;
> +   bool ps_can_reject_z_trivially = !ps->info.info.ps.writes_z;
> +   bool ds_write_enabled =
> +   pCreateInfo->pDepthStencilState &&
> +   subpass->depth_stencil_attachment.attachment != 
> VK_ATTACHMENT_UNUSED &&
> +   (radv_is_depth_write_enabled(pCreateInfo->pDepthStencilState) 
> ||
> +
> radv_is_stencil_write_enabled(pCreateInfo->pDepthStencilState));
> +
> +   /* Disable binning state if PS can kill trivially with DB writes. */
> +   if (ps_can_kill && ps_can_reject_z_trivially && ds_write_enabled)
> +   return false;
> +
> +   return true;
> +}
> +
>  static void
>  radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
>  struct radv_pipeline *pipeline,
> @@ -2168,7 +2221,8 @@ radv_pipeline_generate_binning_state(struct 
> radeon_winsys_cs *cs,
> unreachable("unhandled family while determining binning 
> state.");
> }
>
> -   if (pipeline->device->pbb_allowed && bin_size.width && 
> bin_size.height) {
> +   if (radv_should_enable_pbb(pipeline, pCreateInfo) &&
> +   bin_size.width && bin_size.height) {
> pa_sc_binner_cntl_0 =
> S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
> S_028C44_BIN_SIZE_X(bin_size.width == 16) |
> --
> 2.16.2
>
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[Mesa-dev] [Bug 105670] [regression][hang] Trine1EE hangs GPU after loading screen on Mesa3D-17.3 and later

2018-03-22 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=105670

--- Comment #6 from Timothy Arceri  ---
(In reply to Gert Wollny from comment #2)
> I can confirm this on Radeon 6870 HD. 
> 
> I was able to track the issue to the series beginning with  
> 
>ab23b759f24 glsl: don't drop instructions from unreachable 
>terminators continue branch
> 
> The first time around I had a few difficulties get the correct patch, it
> seems to be either 646621c66da9 or 7a7fb90af75. In any case, yes it is
> related to loop unrolling.
> 
> The original TGSI goes like 
> 
> BGNLOOP
>   ISGE TEMP[13].x, TEMP[8]., IMM[7].
>   UIF TEMP[13].
>  BRK
>   ENDIF
>   ...
> ENDLOOP
> 
> and with the series in question applied it is 
> 
> BGNLOOP
>   ISLT TEMP[13].x, TEMP[8]., IMM[7].
>   UIF TEMP[13].
>   ...
>   ENDI
> ENDLOOP
> 
> This UIF should have an else path with the BRK to resemble the original
> code. 
> (There are more BRK statements in the LOOP but they are the same in both
> versions.
> 
> Regarding bisecting this, after a failure one usually must reboot the
> system, otherwise the graphics card is in a bad state. But given the nature
> of the bug one should also be able to reproduce the endless loop with
> LIBGL_ALWAYS_SOFTWARE=1 thereby not clobbering the hardware.

Thanks for tracking down the problem. Do you think you would be able to create
a piglit test to reproduce the bug? Or failing that can you copy the full glsl
loop an attach it to the bug so that I can attempt to recreate the issue in
piglit. Thanks.

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Re: [Mesa-dev] [PATCH 2/2] gallium/u_vbuf: Protect against overflow with large instance divisors.

2018-03-22 Thread Brian Paul


Reviewed-by: Brian Paul 

On 03/22/2018 04:18 PM, Eric Anholt wrote:

GTF-GLES3.gtf.GL3Tests.instanced_arrays.instanced_arrays_divisor uses -1
as a divisor, so we would overflow to count=0 and upload no data,
triggering the assert below.  We want to upload 1 element in this case,
fixing the test on VC5.

v2: Use some more obvious logic, and explain why we don't use the normal
 round_up().
---
  src/gallium/auxiliary/util/u_vbuf.c | 11 ++-
  1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_vbuf.c 
b/src/gallium/auxiliary/util/u_vbuf.c
index 95d7990c6ca4..8a680d60a687 100644
--- a/src/gallium/auxiliary/util/u_vbuf.c
+++ b/src/gallium/auxiliary/util/u_vbuf.c
@@ -936,7 +936,16 @@ u_vbuf_upload_buffers(struct u_vbuf *mgr,
   size = mgr->ve->src_format_size[i];
} else if (instance_div) {
   /* Per-instance attrib. */
- unsigned count = (num_instances + instance_div - 1) / instance_div;
+
+ /* Figure out how many instances we'll render given instance_div.  We
+  * can't use the typical div_round_up() pattern because the CTS uses
+  * instance_div = ~0 for a test, which overflows div_round_up()'s
+  * addition.
+  */
+ unsigned count = num_instances / instance_div;
+ if (count * instance_div != num_instances)
+count++;
+
   first += vb->stride * start_instance;
   size = vb->stride * (count - 1) + mgr->ve->src_format_size[i];
} else {



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Re: [Mesa-dev] [PATCH 1/2] st: Allow accelerated CopyTexImage from RGBA to RGB.

2018-03-22 Thread Brian Paul


On 03/22/2018 04:18 PM, Eric Anholt wrote:

There's nothing to worry about here -- the A channel just gets dropped by
the blit.  This avoids a segfault in the fallback path when copying from a
RGBA16_SINT renderbuffer to a RGB16_SINT destination represented by an
RGBA16_SINT texture (the fallback path tries to get/fetch to float
buffers, but the float pack/unpack functions are NULL for SINT/UINT).

Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgba16i on VC5.

v2: Extract the logic to a helper function and explain what's going on
 better.
---
  src/mesa/state_tracker/st_cb_texture.c | 32 ++--
  1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_texture.c 
b/src/mesa/state_tracker/st_cb_texture.c
index 6345ead6396b..5a23c7e8b6cd 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2281,6 +2281,31 @@ fallback_copy_texsubimage(struct gl_context *ctx,
 pipe->transfer_unmap(pipe, src_trans);
  }
  
+static bool

+st_can_copyteximage_using_blit(struct gl_texture_image *texImage,
+   struct gl_renderbuffer *rb)


I think those params could be const-qualified.

Looks great otherwise.  Thanks.

Reviewed-by: Brian Paul 


+{
+   GLenum tex_baseformat = _mesa_get_format_base_format(texImage->TexFormat);
+
+   /* We don't blit to a teximage where the GL base format doesn't match the
+* texture's chosen format, except in the case of a GL_RGB texture
+* represented with GL_RGBA (where the alpha channel is just being
+* dropped).
+*/
+   if (texImage->_BaseFormat != tex_baseformat &&
+   ((texImage->_BaseFormat != GL_RGB || tex_baseformat != GL_RGBA))) {
+  return false;
+   }
+
+   /* We can't blit from a RB where the GL base format doesn't match the RB's
+* chosen format (for example, GL RGB or ALPHA with rb->Format of an RGBA
+* type, because the other channels will be undefined).
+*/
+   if (rb->_BaseFormat != _mesa_get_format_base_format(rb->Format))
+  return false;
+
+   return true;
+}
  
  /**

   * Do a CopyTex[Sub]Image1/2/3D() using a hardware (blit) path if possible.
@@ -2324,12 +2349,7 @@ st_CopyTexSubImage(struct gl_context *ctx, GLuint dims,
goto fallback;
 }
  
-   /* The base internal format must match the mesa format, so make sure

-* e.g. an RGB internal format is really allocated as RGB and not as RGBA.
-*/
-   if (texImage->_BaseFormat !=
-   _mesa_get_format_base_format(texImage->TexFormat) ||
-   rb->_BaseFormat != _mesa_get_format_base_format(rb->Format)) {
+   if (!st_can_copyteximage_using_blit(texImage, rb)) {
goto fallback;
 }
  



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[Mesa-dev] [PATCH 2/2] gallium/u_vbuf: Protect against overflow with large instance divisors.

2018-03-22 Thread Eric Anholt

GTF-GLES3.gtf.GL3Tests.instanced_arrays.instanced_arrays_divisor uses -1
as a divisor, so we would overflow to count=0 and upload no data,
triggering the assert below.  We want to upload 1 element in this case,
fixing the test on VC5.

v2: Use some more obvious logic, and explain why we don't use the normal
round_up().
---
 src/gallium/auxiliary/util/u_vbuf.c | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_vbuf.c 
b/src/gallium/auxiliary/util/u_vbuf.c
index 95d7990c6ca4..8a680d60a687 100644
--- a/src/gallium/auxiliary/util/u_vbuf.c
+++ b/src/gallium/auxiliary/util/u_vbuf.c
@@ -936,7 +936,16 @@ u_vbuf_upload_buffers(struct u_vbuf *mgr,
  size = mgr->ve->src_format_size[i];
   } else if (instance_div) {
  /* Per-instance attrib. */
- unsigned count = (num_instances + instance_div - 1) / instance_div;
+
+ /* Figure out how many instances we'll render given instance_div.  We
+  * can't use the typical div_round_up() pattern because the CTS uses
+  * instance_div = ~0 for a test, which overflows div_round_up()'s
+  * addition.
+  */
+ unsigned count = num_instances / instance_div;
+ if (count * instance_div != num_instances)
+count++;
+
  first += vb->stride * start_instance;
  size = vb->stride * (count - 1) + mgr->ve->src_format_size[i];
   } else {
-- 
2.16.2

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[Mesa-dev] [PATCH 1/2] st: Allow accelerated CopyTexImage from RGBA to RGB.

2018-03-22 Thread Eric Anholt

There's nothing to worry about here -- the A channel just gets dropped by
the blit.  This avoids a segfault in the fallback path when copying from a
RGBA16_SINT renderbuffer to a RGB16_SINT destination represented by an
RGBA16_SINT texture (the fallback path tries to get/fetch to float
buffers, but the float pack/unpack functions are NULL for SINT/UINT).

Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgba16i on VC5.

v2: Extract the logic to a helper function and explain what's going on
better.
---
 src/mesa/state_tracker/st_cb_texture.c | 32 ++--
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_texture.c 
b/src/mesa/state_tracker/st_cb_texture.c
index 6345ead6396b..5a23c7e8b6cd 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2281,6 +2281,31 @@ fallback_copy_texsubimage(struct gl_context *ctx,
pipe->transfer_unmap(pipe, src_trans);
 }
 
+static bool
+st_can_copyteximage_using_blit(struct gl_texture_image *texImage,
+   struct gl_renderbuffer *rb)
+{
+   GLenum tex_baseformat = _mesa_get_format_base_format(texImage->TexFormat);
+
+   /* We don't blit to a teximage where the GL base format doesn't match the
+* texture's chosen format, except in the case of a GL_RGB texture
+* represented with GL_RGBA (where the alpha channel is just being
+* dropped).
+*/
+   if (texImage->_BaseFormat != tex_baseformat &&
+   ((texImage->_BaseFormat != GL_RGB || tex_baseformat != GL_RGBA))) {
+  return false;
+   }
+
+   /* We can't blit from a RB where the GL base format doesn't match the RB's
+* chosen format (for example, GL RGB or ALPHA with rb->Format of an RGBA
+* type, because the other channels will be undefined).
+*/
+   if (rb->_BaseFormat != _mesa_get_format_base_format(rb->Format))
+  return false;
+
+   return true;
+}
 
 /**
  * Do a CopyTex[Sub]Image1/2/3D() using a hardware (blit) path if possible.
@@ -2324,12 +2349,7 @@ st_CopyTexSubImage(struct gl_context *ctx, GLuint dims,
   goto fallback;
}
 
-   /* The base internal format must match the mesa format, so make sure
-* e.g. an RGB internal format is really allocated as RGB and not as RGBA.
-*/
-   if (texImage->_BaseFormat !=
-   _mesa_get_format_base_format(texImage->TexFormat) ||
-   rb->_BaseFormat != _mesa_get_format_base_format(rb->Format)) {
+   if (!st_can_copyteximage_using_blit(texImage, rb)) {
   goto fallback;
}
 
-- 
2.16.2

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Re: [Mesa-dev] [RFC] Mesa 17.3.x release problems and process improvements

2018-03-22 Thread Ilia Mirkin

On Thu, Mar 22, 2018 at 6:00 PM, Dylan Baker  wrote:
> Quoting Ilia Mirkin (2018-03-21 17:39:14)
>> Just one bit of feedback, for the rest I either agree or have no opinion:
>>
>> On Wed, Mar 21, 2018 at 8:28 PM, Emil Velikov  
>> wrote:
>> >  * unfit and late nominations:
>> > * any rejections that are unfit based on the existing criteria can
>> >   be merged as long as:
>> >* subsystem specific patches are approved by the team
>> >  maintainer(s).
>> >* patches that cover multiple subsystems are approved by 50%+1
>> >  of the maintainers of the affected subsystems.
>>
>> I don't think 50% + 1 is workable. That would mean for a core mesa
>> patch, one would have to get like 5+ people to ack it. Seems like a
>> lot. (And I suspect will lead to debates about how to count "affected"
>> subsystems.) IMHO 2 is enough, i.e. the maintainer that wants it, and
>> another maintainer who thinks it's reasonable.
>
> What do we do if two maintainers say yes, but it breaks another driver? I'm
> asking because we've had these sort of problems in the past.

An explicit NAK from any maintainer kills the whole thing. I believe
this should apply to all patches, not just these "unfit and late
nominations" category. At least that's what makes sense to me. Ideally
the two warring factions will come to some agreement, but it's not the
release manager's responsibility to resolve these conflicts.

  -ilia
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Re: [Mesa-dev] [RFC] Mesa 17.3.x release problems and process improvements

2018-03-22 Thread Dylan Baker

Quoting Ilia Mirkin (2018-03-21 17:39:14)
> Just one bit of feedback, for the rest I either agree or have no opinion:
> 
> On Wed, Mar 21, 2018 at 8:28 PM, Emil Velikov  
> wrote:
> >  * unfit and late nominations:
> > * any rejections that are unfit based on the existing criteria can
> >   be merged as long as:
> >* subsystem specific patches are approved by the team
> >  maintainer(s).
> >* patches that cover multiple subsystems are approved by 50%+1
> >  of the maintainers of the affected subsystems.
> 
> I don't think 50% + 1 is workable. That would mean for a core mesa
> patch, one would have to get like 5+ people to ack it. Seems like a
> lot. (And I suspect will lead to debates about how to count "affected"
> subsystems.) IMHO 2 is enough, i.e. the maintainer that wants it, and
> another maintainer who thinks it's reasonable.

What do we do if two maintainers say yes, but it breaks another driver? I'm
asking because we've had these sort of problems in the past.

Dylan


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Re: [Mesa-dev] [PATCH 1/4] intel/genxml: Add SC_INSTDONE register.

2018-03-22 Thread Lionel Landwerlin


I didn't check the xml definition bit by bit, but I'm sure it's fine.
This series is :

Reviewed-by: Lionel Landwerlin 

On 21/03/18 18:42, Rafael Antognolli wrote:

---
  src/intel/genxml/gen10.xml | 27 +++
  src/intel/genxml/gen11.xml | 27 +++
  src/intel/genxml/gen7.xml  | 19 +++
  src/intel/genxml/gen75.xml | 17 +
  src/intel/genxml/gen8.xml  | 24 
  src/intel/genxml/gen9.xml  | 26 ++
  6 files changed, 140 insertions(+)

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index cc696e800d1..e0bf0e91590 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3459,6 +3459,33 @@
  

  
+  

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+

  
  
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 417fac13654..3278f35b824 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3455,6 +3455,33 @@
  

  
+  

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+

  
  
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 87e05c94ef5..bc9fa5b65de 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2397,6 +2397,25 @@
  

  
+  

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+

  
  
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 68aff857f35..9e2b789006f 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2869,6 +2869,23 @@
  

  
+  

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+

  
  
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 8a4bf34cf7d..0a6be596988 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -3123,6 +3123,30 @@
  

  
+  

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+

  
  
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index cfae4a8b658..834f5773ff2 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -3406,6 +3406,32 @@
  

  
+  

+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+  
+

  
  



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Re: [Mesa-dev] [PATCH] anv: Add gen11 to anv_genX_call

2018-03-22 Thread Lionel Landwerlin


There is another macro anv_genX_call() in anv_cmd_buffer.c & anv_blorp.c
Also a switch in anv_device.c in anv_device_init_dispatch.

If you just knock those off in the same patch, that would be great.

Thanks!

-
Lionel

On 22/03/18 20:58, Jordan Justen wrote:

Signed-off-by: Jordan Justen 
---
  src/intel/vulkan/anv_cmd_buffer.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 8f4bf3f0bb9..33687920a38 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -332,6 +332,9 @@ VkResult anv_ResetCommandBuffer(
 case 10:\
gen10_##func(__VA_ARGS__);   \
break;   \
+   case 11:\
+  gen11_##func(__VA_ARGS__);   \
+  break;   \
 default:\
assert(!"Unknown hardware generation");  \
 }



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[Mesa-dev] [PATCH] anv: Add gen11 to anv_genX_call

2018-03-22 Thread Jordan Justen

Signed-off-by: Jordan Justen 
---
 src/intel/vulkan/anv_cmd_buffer.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 8f4bf3f0bb9..33687920a38 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -332,6 +332,9 @@ VkResult anv_ResetCommandBuffer(
case 10:\
   gen10_##func(__VA_ARGS__);   \
   break;   \
+   case 11:\
+  gen11_##func(__VA_ARGS__);   \
+  break;   \
default:\
   assert(!"Unknown hardware generation");  \
}
-- 
2.16.2

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[Mesa-dev] [Bug 105670] [regression][hang] Trine1EE hangs GPU after loading screen on Mesa3D-17.3 and later

2018-03-22 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=105670

--- Comment #5 from Roland Scheidegger  ---
(In reply to almos from comment #4)
> The problem is not loop unrolling. The problem is that userspace code can
> hang the GPU unrecoverably, and thus bringing down the entire system.
> 
> BTW I can confirm this on Pitcairn with radeon drm in linux 4.15.

There isn't much you can do about shaders not terminating (loop limiting in
llvmpipe is quite a hack, you could legitimately have a loop which has more
iterations).

But yes, gpu reset actually working reliably would be nice. I haven't really
seen it succeed lately neither (but it can happen...).

I disagree that loop unrolling isn't a problem. Clearly there's two problems:
- loop unrolling shouldn't turn perfectly fine loops into loops which don't
terminate, this is what this bug is about.
- gpu reset should work reliably

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[Mesa-dev] [Bug 105670] [regression][hang] Trine1EE hangs GPU after loading screen on Mesa3D-17.3 and later

2018-03-22 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=105670

--- Comment #4 from almos  ---
The problem is not loop unrolling. The problem is that userspace code can hang
the GPU unrecoverably, and thus bringing down the entire system.

BTW I can confirm this on Pitcairn with radeon drm in linux 4.15.

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Re: [Mesa-dev] [PATCH 2/2] svga: simplify uses_flat_interp expression in emit_input_declarations()

2018-03-22 Thread Neha Bhende

For the series,


Reviewed-by: Neha Bhende



Regards,

Neha


From: Brian Paul 
Sent: Thursday, March 22, 2018 8:28:52 AM
To: mesa-dev@lists.freedesktop.org
Cc: Neha Bhende; Charmaine Lee
Subject: [PATCH 2/2] svga: simplify uses_flat_interp expression in 
emit_input_declarations()

---
 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index 04d8303..4292894 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -2396,7 +2396,7 @@ emit_input_declarations(struct svga_shader_emitter_v10 
*emit)
emit->info.input_interpolate_loc[i]);

 /* keeps track if flat interpolation mode is being used */
-emit->uses_flat_interp = emit->uses_flat_interp ||
+emit->uses_flat_interp |=
(interpolationMode == VGPU10_INTERPOLATION_CONSTANT);

 name = VGPU10_NAME_UNDEFINED;
--
2.7.4

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Re: [Mesa-dev] [PATCH 3/3] st/mesa: s/unsigned/enum pipe_shader_type/ for st_bind_ubos()

2018-03-22 Thread Neha Bhende

For the series,


Reviewed-by: Neha Bhende


Regards,

Neha


From: Brian Paul 
Sent: Thursday, March 22, 2018 8:29:16 AM
To: mesa-dev@lists.freedesktop.org
Cc: Neha Bhende; Charmaine Lee
Subject: [PATCH 3/3] st/mesa: s/unsigned/enum pipe_shader_type/ for 
st_bind_ubos()

---
 src/mesa/state_tracker/st_atom_constbuf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_atom_constbuf.c 
b/src/mesa/state_tracker/st_atom_constbuf.c
index 0c094dc..6455e61 100644
--- a/src/mesa/state_tracker/st_atom_constbuf.c
+++ b/src/mesa/state_tracker/st_atom_constbuf.c
@@ -196,7 +196,7 @@ st_update_cs_constants(struct st_context *st)

 static void
 st_bind_ubos(struct st_context *st, struct gl_program *prog,
- unsigned shader_type)
+ enum pipe_shader_type shader_type)
 {
unsigned i;
struct pipe_constant_buffer cb = { 0 };
--
2.7.4

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Re: [Mesa-dev] [PATCH v3] wayland-drm: do not distribute generated sources

2018-03-22 Thread Emil Velikov

On 22 March 2018 at 18:46, Juan A. Suarez Romero  wrote:
> Instead we will re-generate them again on building.
>
> v2: get rid of BUILT_SOURCES (Daniel, Emil)
> ---
>  src/egl/Makefile.am | 15 ++-
>  src/egl/wayland/wayland-drm/Makefile.am | 22 --
>  src/vulkan/Makefile.am  | 15 ++-
>  3 files changed, 36 insertions(+), 16 deletions(-)
>
> diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
> index 285d3caa9ef..5d25eb46a39 100644
> --- a/src/egl/Makefile.am
> +++ b/src/egl/Makefile.am
> @@ -23,8 +23,6 @@ include Makefile.sources
>
>  MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D)
>
> -BUILT_SOURCES =
> -

> -BUILT_SOURCES += g_egldispatchstubs.c g_egldispatchstubs.h
There should stay in the list  -> with that
Reviewed-by: Emil Velikov 

-Emil
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[Mesa-dev] [PATCH v3] wayland-drm: do not distribute generated sources

2018-03-22 Thread Juan A. Suarez Romero

Instead we will re-generate them again on building.

v2: get rid of BUILT_SOURCES (Daniel, Emil)
---
 src/egl/Makefile.am | 15 ++-
 src/egl/wayland/wayland-drm/Makefile.am | 22 --
 src/vulkan/Makefile.am  | 15 ++-
 3 files changed, 36 insertions(+), 16 deletions(-)

diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 285d3caa9ef..5d25eb46a39 100644
--- a/src/egl/Makefile.am
+++ b/src/egl/Makefile.am
@@ -23,8 +23,6 @@ include Makefile.sources
 
 MKDIR_GEN = $(AM_V_at)$(MKDIR_P) $(@D)
 
-BUILT_SOURCES =
-
 AM_CFLAGS = \
-I$(top_srcdir)/include \
-I$(top_srcdir)/src/mapi \
@@ -50,6 +48,7 @@ libEGL_common_la_LIBADD = \
$(EGL_LIB_DEPS)
 
 dri2_backend_FILES =
+dri2_backend_GENERATED_FILES =
 dri3_backend_FILES =
 
 if HAVE_PLATFORM_X11
@@ -87,7 +86,8 @@ AM_CFLAGS += $(WAYLAND_SERVER_CFLAGS)
 libEGL_common_la_LIBADD += 
$(top_builddir)/src/egl/wayland/wayland-drm/libwayland-drm.la
 libEGL_common_la_LIBADD += $(WAYLAND_SERVER_LIBS)
 dri2_backend_FILES += \
-   drivers/dri2/platform_wayland.c \
+   drivers/dri2/platform_wayland.c
+dri2_backend_GENERATED_FILES += \
drivers/dri2/linux-dmabuf-unstable-v1-protocol.c \
drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.h
 endif
@@ -118,6 +118,9 @@ AM_CFLAGS += \
-DDEFAULT_DRIVER_DIR=\"$(DRI_DRIVER_SEARCH_DIR)\" \
-D_EGL_BUILT_IN_DRIVER_DRI2
 
+nodist_libEGL_common_la_SOURCES = \
+   $(dri2_backend_GENERATED_FILES)
+
 libEGL_common_la_SOURCES += \
$(dri2_backend_core_FILES) \
$(dri2_backend_FILES) \
@@ -147,8 +150,10 @@ g_egldispatchstubs.h: $(GLVND_GEN_DEPS)
$(top_srcdir)/src/egl/generate/egl.xml \
$(top_srcdir)/src/egl/generate/egl_other.xml > $@
 
-BUILT_SOURCES += g_egldispatchstubs.c g_egldispatchstubs.h
-CLEANFILES = $(BUILT_SOURCES)
+CLEANFILES = \
+   g_egldispatchstubs.c \
+   g_egldispatchstubs.h \
+   $(dri2_backend_GENERATED_FILES)
 
 if USE_LIBGLVND
 AM_CFLAGS += \
diff --git a/src/egl/wayland/wayland-drm/Makefile.am 
b/src/egl/wayland/wayland-drm/Makefile.am
index c10c4349d48..0404c79e7fa 100644
--- a/src/egl/wayland/wayland-drm/Makefile.am
+++ b/src/egl/wayland/wayland-drm/Makefile.am
@@ -3,19 +3,29 @@ AM_CFLAGS = -I$(top_srcdir)/include \
$(VISIBILITY_CFLAGS) \
$(WAYLAND_SERVER_CFLAGS)
 
+if HAVE_PLATFORM_WAYLAND
+wayland-drm.lo: wayland-drm-client-protocol.h wayland-drm-server-protocol.h
+endif
+
 noinst_LTLIBRARIES = libwayland-drm.la
+
+nodist_libwayland_drm_la_SOURCES = \
+   wayland-drm-protocol.c \
+   wayland-drm-client-protocol.h \
+   wayland-drm-server-protocol.h
+
 libwayland_drm_la_SOURCES = \
wayland-drm.c \
-   wayland-drm.h \
-   wayland-drm-protocol.c
+   wayland-drm.h
+
 noinst_HEADERS = wayland-drm.h
 
 EXTRA_DIST = wayland-drm.xml meson.build
 
-BUILT_SOURCES = wayland-drm-protocol.c \
-   wayland-drm-client-protocol.h \
-   wayland-drm-server-protocol.h
-CLEANFILES = $(BUILT_SOURCES)
+CLEANFILES = \
+   wayland-drm-protocol.c \
+   wayland-drm-client-protocol.h \
+   wayland-drm-server-protocol.h
 
 %-protocol.c : %.xml
$(AM_V_GEN)$(WAYLAND_SCANNER) code $< $@
diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am
index e6d4277f92f..bbcf7d0cc64 100644
--- a/src/vulkan/Makefile.am
+++ b/src/vulkan/Makefile.am
@@ -20,9 +20,6 @@ VULKAN_UTIL_SOURCES = \
$(VULKAN_UTIL_FILES) \
$(VULKAN_UTIL_GENERATED_FILES)
 
-BUILT_SOURCES = \
-   $(VULKAN_UTIL_GENERATED_FILES)
-
 util/vk_enum_to_str.c util/vk_enum_to_str.h: util/gen_enum_to_str.py \
$(vulkan_api_xml) $(vk_android_native_buffer_xml)
$(MKDIR_GEN)
@@ -46,6 +43,8 @@ AM_CFLAGS = \
$(LIBDRM_CFLAGS) \
$(VISIBILITY_CFLAGS)
 
+VULKAN_WSI_GENERATED_SOURCES =
+
 VULKAN_WSI_SOURCES = \
$(VULKAN_WSI_FILES)
 
@@ -58,7 +57,9 @@ AM_CPPFLAGS += \
 VULKAN_WSI_SOURCES += $(VULKAN_WSI_X11_FILES)
 endif
 
-CLEANFILES = $(BUILT_SOURCES)
+CLEANFILES = \
+   $(VULKAN_UTIL_GENERATED_FILES) \
+   $(VULKAN_WSI_WAYLAND_GENERATED_FILES)
 
 WL_DRM_XML = $(top_srcdir)/src/egl/wayland/wayland-drm/wayland-drm.xml
 
@@ -91,9 +92,13 @@ AM_CPPFLAGS += \
-DVK_USE_PLATFORM_WAYLAND_KHR
 
 VULKAN_WSI_SOURCES += \
-   $(VULKAN_WSI_WAYLAND_FILES) \
+   $(VULKAN_WSI_WAYLAND_FILES)
+
+VULKAN_WSI_GENERATED_SOURCES += \
$(VULKAN_WSI_WAYLAND_GENERATED_FILES)
 
 endif
 
+nodist_libvulkan_wsi_la_SOURCES = $(VULKAN_WSI_GENERATED_SOURCES)
+
 libvulkan_wsi_la_SOURCES = $(VULKAN_WSI_SOURCES)
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 1/3] st/mesa: s/unsigned/enum pipe_shader_type/

2018-03-22 Thread Eric Anholt

Brian Paul  writes:

> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 --
>  src/mesa/state_tracker/st_glsl_to_tgsi.h   | 2 +-
>  2 files changed, 5 insertions(+), 3 deletions(-)

This series is:

Reviewed-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH] i965: Drop PIPE_CONTROL_NO_WRITE from various calls.

2018-03-22 Thread Lionel Landwerlin


Reviewed-by: Lionel Landwerlin 

On 22/03/18 18:22, Kenneth Graunke wrote:

This is just zero - passing nothing already gives us a post-sync
operation of "nothing".
---
  src/mesa/drivers/dri/i965/brw_misc_state.c   | 4 +---
  src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
  src/mesa/drivers/dri/i965/brw_program.c  | 4 +---
  src/mesa/drivers/dri/i965/gen7_l3_state.c| 5 +
  4 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 29d74876c27..05517ebf587 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -462,15 +462,13 @@ brw_emit_select_pipeline(struct brw_context *brw, enum 
brw_pipeline pipeline)
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
dc_flush |
-  PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
  
brw_emit_pipe_control_flush(brw,

PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_STATE_CACHE_INVALIDATE |
-  PIPE_CONTROL_INSTRUCTION_INVALIDATE |
-  PIPE_CONTROL_NO_WRITE);
+  PIPE_CONTROL_INSTRUCTION_INVALIDATE);
  
 } else {

/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 2350a6148f3..71f79b18474 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -547,7 +547,7 @@ brw_emit_mi_flush(struct brw_context *brw)
   OUT_BATCH(0);
ADVANCE_BATCH();
 } else {
-  int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
+  int flags = PIPE_CONTROL_RENDER_TARGET_FLUSH;
if (devinfo->gen >= 6) {
   flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 4ba46a3c826..23743639dc8 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -277,9 +277,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield 
barriers)
  {
 struct brw_context *brw = brw_context(ctx);
 const struct gen_device_info *devinfo = >screen->devinfo;
-   unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
-PIPE_CONTROL_NO_WRITE |
-PIPE_CONTROL_CS_STALL);
+   unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL;
 assert(devinfo->gen >= 7 && devinfo->gen <= 11);
  
 if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |

diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c 
b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index 8c8f4169e7e..8c6c4c47481 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -86,7 +86,6 @@ setup_l3_config(struct brw_context *brw, const struct 
gen_l3_config *cfg)
  */
 brw_emit_pipe_control_flush(brw,
 PIPE_CONTROL_DATA_CACHE_FLUSH |
-   PIPE_CONTROL_NO_WRITE |
 PIPE_CONTROL_CS_STALL);
  
 /* ...followed by a second pipelined PIPE_CONTROL that initiates

@@ -107,15 +106,13 @@ setup_l3_config(struct brw_context *brw, const struct 
gen_l3_config *cfg)
 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 PIPE_CONTROL_CONST_CACHE_INVALIDATE |
 PIPE_CONTROL_INSTRUCTION_INVALIDATE |
-   PIPE_CONTROL_STATE_CACHE_INVALIDATE |
-   PIPE_CONTROL_NO_WRITE);
+   PIPE_CONTROL_STATE_CACHE_INVALIDATE);
  
 /* Now send a third stalling flush to make sure that invalidation is

  * complete when the L3 configuration registers are modified.
  */
 brw_emit_pipe_control_flush(brw,
 PIPE_CONTROL_DATA_CACHE_FLUSH |
-   PIPE_CONTROL_NO_WRITE |
 PIPE_CONTROL_CS_STALL);
  
 if (devinfo->gen >= 8) {



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Re: [Mesa-dev] [PATCH v2 7/7] broadcom/vc4: add path to nir_builder.h

2018-03-22 Thread Eric Anholt

"Juan A. Suarez Romero"  writes:

> As the other VC4 files do. Otherwise, it won't find nir_builder.h
>
> v2: add path in source code rather changing autotools (Emil)
>
> Reviewed-by: Emil Velikov 

Reviewed-by: Eric Anholt 


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Re: [Mesa-dev] [PATCH mesa] meson: merge C and C++ compiler arguments check

2018-03-22 Thread Eric Engestrom

On Thursday, 2018-03-22 11:17:55 -0700, Dylan Baker wrote:
> Quoting Eric Engestrom (2018-03-22 05:08:55)
> > On Monday, 2018-03-12 10:16:33 -0700, Dylan Baker wrote:
> > > Quoting Emil Velikov (2018-03-12 09:09:50)
> > > > On 12 March 2018 at 15:01, Eric Engestrom  
> > > > wrote:
> > > > > Signed-off-by: Eric Engestrom 
> > > > > ---
> > > > > Dylan, was there any reason to have -Werror=missing-prototypes and
> > > > > -Werror=implicit-function-declaration in C but not C++?
> > > > > Both sound to me like something we always want.
> > > > 
> > > > Seems to be copied from the autotools setup.
> > > > Reason being, both are not valid for C++.
> > > > Although since we probe for them, everything should be fine. The C++
> > > > test will bail out and the flags won't be set during the actual build.
> > > 
> > > Which is why I left them separate, since it avoids having to compile for
> > > arguments we know that C++ doesn't support.
> > 
> > Pushed now (cb2ddcefa5196fdfeff7), but to explain, my point was: we want
> > those warnings when possible, so we might as well test for them and use
> > them if/when support is added in the compilers.
> > 
> > The configure-time cost is very low, and the build-time cost is
> > non-existent :)
> > 
> > > It probably doesn't matter either way,
> > > 
> > > Reviewed-by: Dylan Baker 
> 
> I didn't notice before, but this breaks compiling basically all of our C++ 
> code
> with clang since it adds -Werror=missing-prototypes, and clang gets very angry
> at us.

Ah crap :(
Are you pushing a revert, or should I?

Question though, why is the code full of missing prototypes? Is that
a compiler mistake (false-positives), or is the code really missing
a bunch of includes?

> 
> Dylan
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Re: [Mesa-dev] [PATCH 1/7] tgsi: convert opcode macros to enums

2018-03-22 Thread Eric Anholt

Brian Paul  writes:

> Enums are nicer in gdb.

This series is:

Reviewed-by: Eric Anholt 


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[Mesa-dev] [PATCH] i965: Drop PIPE_CONTROL_NO_WRITE from various calls.

2018-03-22 Thread Kenneth Graunke

This is just zero - passing nothing already gives us a post-sync
operation of "nothing".
---
 src/mesa/drivers/dri/i965/brw_misc_state.c   | 4 +---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
 src/mesa/drivers/dri/i965/brw_program.c  | 4 +---
 src/mesa/drivers/dri/i965/gen7_l3_state.c| 5 +
 4 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 29d74876c27..05517ebf587 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -462,15 +462,13 @@ brw_emit_select_pipeline(struct brw_context *brw, enum 
brw_pipeline pipeline)
   PIPE_CONTROL_RENDER_TARGET_FLUSH |
   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
   dc_flush |
-  PIPE_CONTROL_NO_WRITE |
   PIPE_CONTROL_CS_STALL);
 
   brw_emit_pipe_control_flush(brw,
   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
   PIPE_CONTROL_CONST_CACHE_INVALIDATE |
   PIPE_CONTROL_STATE_CACHE_INVALIDATE |
-  PIPE_CONTROL_INSTRUCTION_INVALIDATE |
-  PIPE_CONTROL_NO_WRITE);
+  PIPE_CONTROL_INSTRUCTION_INVALIDATE);
 
} else {
   /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 2350a6148f3..71f79b18474 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -547,7 +547,7 @@ brw_emit_mi_flush(struct brw_context *brw)
  OUT_BATCH(0);
   ADVANCE_BATCH();
} else {
-  int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
+  int flags = PIPE_CONTROL_RENDER_TARGET_FLUSH;
   if (devinfo->gen >= 6) {
  flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
   PIPE_CONTROL_CONST_CACHE_INVALIDATE |
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 4ba46a3c826..23743639dc8 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -277,9 +277,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield 
barriers)
 {
struct brw_context *brw = brw_context(ctx);
const struct gen_device_info *devinfo = >screen->devinfo;
-   unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
-PIPE_CONTROL_NO_WRITE |
-PIPE_CONTROL_CS_STALL);
+   unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL;
assert(devinfo->gen >= 7 && devinfo->gen <= 11);
 
if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c 
b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index 8c8f4169e7e..8c6c4c47481 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -86,7 +86,6 @@ setup_l3_config(struct brw_context *brw, const struct 
gen_l3_config *cfg)
 */
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DATA_CACHE_FLUSH |
-   PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
 
/* ...followed by a second pipelined PIPE_CONTROL that initiates
@@ -107,15 +106,13 @@ setup_l3_config(struct brw_context *brw, const struct 
gen_l3_config *cfg)
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_INSTRUCTION_INVALIDATE |
-   PIPE_CONTROL_STATE_CACHE_INVALIDATE |
-   PIPE_CONTROL_NO_WRITE);
+   PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 
/* Now send a third stalling flush to make sure that invalidation is
 * complete when the L3 configuration registers are modified.
 */
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DATA_CACHE_FLUSH |
-   PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
 
if (devinfo->gen >= 8) {
-- 
2.16.2

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Re: [Mesa-dev] [PATCH v6 1/2] gallium/winsys/kms: Fix possible leak in map/unmap.

2018-03-22 Thread Emil Velikov

On 21 March 2018 at 18:00, Lepton Wu  wrote:

> Thanks all for review. Is there anything else missing for getting this
> committed?

Some of us tend to give extra 24h or so for other devs to send final
comments/R-B.
Everything seems silent so the series is in master now. Thanks!

Tomasz can apply for commit access and with a bit more work so can you
- see [1].

-Emil
[1] https://www.mesa3d.org/repository.html#developer
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Re: [Mesa-dev] [PATCH mesa] meson: merge C and C++ compiler arguments check

2018-03-22 Thread Dylan Baker

Quoting Eric Engestrom (2018-03-22 05:08:55)
> On Monday, 2018-03-12 10:16:33 -0700, Dylan Baker wrote:
> > Quoting Emil Velikov (2018-03-12 09:09:50)
> > > On 12 March 2018 at 15:01, Eric Engestrom  
> > > wrote:
> > > > Signed-off-by: Eric Engestrom 
> > > > ---
> > > > Dylan, was there any reason to have -Werror=missing-prototypes and
> > > > -Werror=implicit-function-declaration in C but not C++?
> > > > Both sound to me like something we always want.
> > > 
> > > Seems to be copied from the autotools setup.
> > > Reason being, both are not valid for C++.
> > > Although since we probe for them, everything should be fine. The C++
> > > test will bail out and the flags won't be set during the actual build.
> > 
> > Which is why I left them separate, since it avoids having to compile for
> > arguments we know that C++ doesn't support.
> 
> Pushed now (cb2ddcefa5196fdfeff7), but to explain, my point was: we want
> those warnings when possible, so we might as well test for them and use
> them if/when support is added in the compilers.
> 
> The configure-time cost is very low, and the build-time cost is
> non-existent :)
> 
> > It probably doesn't matter either way,
> > 
> > Reviewed-by: Dylan Baker 

I didn't notice before, but this breaks compiling basically all of our C++ code
with clang since it adds -Werror=missing-prototypes, and clang gets very angry
at us.

Dylan


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Re: [Mesa-dev] [PATCH 1/6] i965: Add negative_equals methods

2018-03-22 Thread Ian Romanick

On 03/22/2018 01:12 AM, Alejandro Piñeiro wrote:
> Looks good in general, just a comment below.
> 
> 
> On 22/03/18 01:58, Ian Romanick wrote:
>> From: Ian Romanick 
>>
>> This method is similar to the existing ::equals methods.  Instead of
>> testing that two src_regs are equal to each other, it tests that one is
>> the negation of the other.
>>
>> v2: Simplify various checks based on suggestions from Matt.  Use
>> src_reg::type instead of fixed_hw_reg.type in a check.  Also suggested
>> by Matt.
>>
>> v3: Rebase on 3 years.  Fix some problems with negative_equals with VF
>> constants.  Add fs_reg::negative_equals.
>>
>> Signed-off-by: Ian Romanick 
>> ---
>>  src/intel/compiler/brw_fs.cpp |  7 ++
>>  src/intel/compiler/brw_ir_fs.h|  1 +
>>  src/intel/compiler/brw_ir_vec4.h  |  1 +
>>  src/intel/compiler/brw_reg.h  | 46 
>> +++
>>  src/intel/compiler/brw_shader.cpp |  6 +
>>  src/intel/compiler/brw_shader.h   |  1 +
>>  src/intel/compiler/brw_vec4.cpp   |  7 ++
>>  7 files changed, 69 insertions(+)
>>
>> diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
>> index 6eea532..3d454c3 100644
>> --- a/src/intel/compiler/brw_fs.cpp
>> +++ b/src/intel/compiler/brw_fs.cpp
>> @@ -454,6 +454,13 @@ fs_reg::equals(const fs_reg ) const
>>  }
>>  
>>  bool
>> +fs_reg::negative_equals(const fs_reg ) const
>> +{
>> +   return (this->backend_reg::negative_equals(r) &&
>> +   stride == r.stride);
>> +}
>> +
>> +bool
>>  fs_reg::is_contiguous() const
>>  {
>> return stride == 1;
>> diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
>> index 54797ff..f06a33c 100644
>> --- a/src/intel/compiler/brw_ir_fs.h
>> +++ b/src/intel/compiler/brw_ir_fs.h
>> @@ -41,6 +41,7 @@ public:
>> fs_reg(enum brw_reg_file file, int nr, enum brw_reg_type type);
>>  
>> bool equals(const fs_reg ) const;
>> +   bool negative_equals(const fs_reg ) const;
>> bool is_contiguous() const;
>>  
>> /**
>> diff --git a/src/intel/compiler/brw_ir_vec4.h 
>> b/src/intel/compiler/brw_ir_vec4.h
>> index cbaff2f..95c5119 100644
>> --- a/src/intel/compiler/brw_ir_vec4.h
>> +++ b/src/intel/compiler/brw_ir_vec4.h
>> @@ -43,6 +43,7 @@ public:
>> src_reg(struct ::brw_reg reg);
>>  
>> bool equals(const src_reg ) const;
>> +   bool negative_equals(const src_reg ) const;
>>  
>> src_reg(class vec4_visitor *v, const struct glsl_type *type);
>> src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
>> diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
>> index 7ad144b..732bddf 100644
>> --- a/src/intel/compiler/brw_reg.h
>> +++ b/src/intel/compiler/brw_reg.h
>> @@ -255,6 +255,52 @@ brw_regs_equal(const struct brw_reg *a, const struct 
>> brw_reg *b)
>> return a->bits == b->bits && (df ? a->u64 == b->u64 : a->ud == b->ud);
>>  }
>>  
>> +static inline bool
>> +brw_regs_negative_equal(const struct brw_reg *a, const struct brw_reg *b)
>> +{
>> +   if (a->file == IMM) {
>> +  if (a->bits != b->bits)
>> + return false;
>> +
>> +  switch (a->type) {
>> +  case BRW_REGISTER_TYPE_UQ:
>> +  case BRW_REGISTER_TYPE_Q:
>> + return a->d64 == -b->d64;
>> +  case BRW_REGISTER_TYPE_DF:
>> + return a->df == -b->df;
>> +  case BRW_REGISTER_TYPE_UD:
>> +  case BRW_REGISTER_TYPE_D:
>> + return a->d == -b->d;
>> +  case BRW_REGISTER_TYPE_F:
>> + return a->f == -b->f;
>> +  case BRW_REGISTER_TYPE_VF:
>> + /* It is tempting to treat 0 as a negation of 0 (and -0 as a 
>> negation
>> +  * of -0).  There are occasions where 0 or -0 is used and the exact
>> +  * bit pattern is desired.  At the very least, changing this to 
>> allow
>> +  * 0 as a negation of 0 causes some fp64 tests to fail on IVB.
>> +  */
>> + return a->ud == (b->ud ^ 0x80808080);
>> +  case BRW_REGISTER_TYPE_UW:
>> +  case BRW_REGISTER_TYPE_W:
>> +  case BRW_REGISTER_TYPE_UV:
>> +  case BRW_REGISTER_TYPE_V:
>> +  case BRW_REGISTER_TYPE_HF:
>> +  case BRW_REGISTER_TYPE_UB:
>> +  case BRW_REGISTER_TYPE_B:
>> + /* FINISHME: Implement support for these types. */
> 
> Is this missing functionality on purpose or the patch is still a wip? If
> it is the former, perhaps it would be good to explain why it is ok to
> leave that functionality hole.

Basically this means that any optimizations that depend on
negative_equals won't happen.  I didn't implement these paths because,
as far as I can tell, we never generate any code that uses these types.
I was a bit reluctant to implement something that I couldn't test.

>> + return false;
>> +  default:
>> + unreachable("not reached");
>> +  }
>> +   } else {
>> +  struct brw_reg tmp = *a;
>> +
>> +  tmp.negate = !tmp.negate;
>> +
>> +  return brw_regs_equal(,

Re: [Mesa-dev] [PATCH 5/6] i965/vec4: Propagate conditional modifiers from compares to adds

2018-03-22 Thread Ian Romanick

On 03/22/2018 01:12 AM, Alejandro Piñeiro wrote:
> Any reason to not add tests on test_vec4_cmod_propagation as the fs
> equivalent did?

Laziness. :)

> Also, two small comments below.
> 
> On 22/03/18 01:58, Ian Romanick wrote:
>> From: Ian Romanick 
>>
>> No changes on Broadwell and later becuase those plaforms do not use the
>> vec4 backend at all.
> 
> typo: becuase -> because

And plaforms -> platforms.  I'll fix those.

>> Ivy Bridge and Haswell had similar results. (Ivy Bridge shown)
>> total instructions in shared programs: 11682119 -> 11681056 (<.01%)
>> instructions in affected programs: 150403 -> 149340 (-0.71%)
>> helped: 950
>> HURT: 0
>> helped stats (abs) min: 1 max: 16 x̄: 1.12 x̃: 1
>> helped stats (rel) min: 0.23% max: 2.78% x̄: 0.82% x̃: 0.71%
>> 95% mean confidence interval for instructions value: -1.19 -1.04
>> 95% mean confidence interval for instructions %-change: -0.84% -0.79%
>> Instructions are helped.
>>
>> total cycles in shared programs: 257495842 -> 257495238 (<.01%)
>> cycles in affected programs: 270302 -> 269698 (-0.22%)
>> helped: 271
>> HURT: 13
>> helped stats (abs) min: 2 max: 14 x̄: 2.42 x̃: 2
>> helped stats (rel) min: 0.06% max: 1.13% x̄: 0.32% x̃: 0.28%
>> HURT stats (abs)   min: 2 max: 12 x̄: 4.00 x̃: 4
>> HURT stats (rel)   min: 0.15% max: 1.18% x̄: 0.30% x̃: 0.26%
>> 95% mean confidence interval for cycles value: -2.41 -1.84
>> 95% mean confidence interval for cycles %-change: -0.31% -0.26%
>> Cycles are helped.
>>
>> Sandy Bridge
>> total instructions in shared programs: 10430493 -> 10429727 (<.01%)
>> instructions in affected programs: 120860 -> 120094 (-0.63%)
>> helped: 766
>> HURT: 0
>> helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
>> helped stats (rel) min: 0.30% max: 2.70% x̄: 0.78% x̃: 0.73%
>> 95% mean confidence interval for instructions value: -1.00 -1.00
>> 95% mean confidence interval for instructions %-change: -0.80% -0.75%
>> Instructions are helped.
>>
>> total cycles in shared programs: 146138718 -> 146138446 (<.01%)
>> cycles in affected programs: 244114 -> 243842 (-0.11%)
>> helped: 132
>> HURT: 0
>> helped stats (abs) min: 2 max: 4 x̄: 2.06 x̃: 2
>> helped stats (rel) min: 0.03% max: 0.43% x̄: 0.16% x̃: 0.19%
>> 95% mean confidence interval for cycles value: -2.12 -2.00
>> 95% mean confidence interval for cycles %-change: -0.18% -0.15%
>> Cycles are helped.
>>
>> GM45 and Iron Lake had identical results. (Iron Lake shown)
>> total instructions in shared programs: 7780251 -> 7780248 (<.01%)
>> instructions in affected programs: 175 -> 172 (-1.71%)
>> helped: 3
>> HURT: 0
>> helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
>> helped stats (rel) min: 1.49% max: 2.44% x̄: 1.81% x̃: 1.49%
>>
>> total cycles in shared programs: 177851584 -> 177851578 (<.01%)
>> cycles in affected programs: 9796 -> 9790 (-0.06%)
>> helped: 3
>> HURT: 0
>> helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
>> helped stats (rel) min: 0.05% max: 0.08% x̄: 0.06% x̃: 0.05%
>>
>> Signed-off-by: Ian Romanick 
>> ---
>>  src/intel/compiler/brw_vec4_cmod_propagation.cpp | 70 
>> ++--
>>  1 file changed, 65 insertions(+), 5 deletions(-)
>>
>> diff --git a/src/intel/compiler/brw_vec4_cmod_propagation.cpp 
>> b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
>> index 7f1001b..5205da4 100644
>> --- a/src/intel/compiler/brw_vec4_cmod_propagation.cpp
>> +++ b/src/intel/compiler/brw_vec4_cmod_propagation.cpp
>> @@ -50,8 +50,14 @@ opt_cmod_propagation_local(bblock_t *block)
>>inst->predicate != BRW_PREDICATE_NONE ||
>>!inst->dst.is_null() ||
>>(inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
>> -   inst->src[0].file != UNIFORM) ||
>> -  inst->src[0].abs)
>> +   inst->src[0].file != UNIFORM))
>> + continue;
>> +
>> +  /* An ABS source modifier can only be handled when processing a 
>> compare
>> +   * with a value other than zero.
>> +   */
>> +  if (inst->src[0].abs &&
>> +  (inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero()))
>>   continue;
>>  
>>if (inst->opcode == BRW_OPCODE_AND &&
>> @@ -60,15 +66,68 @@ opt_cmod_propagation_local(bblock_t *block)
>>  !inst->src[0].negate))
>>   continue;
>>  
>> -  if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero())
>> - continue;
>> -
>>if (inst->opcode == BRW_OPCODE_MOV &&
>>inst->conditional_mod != BRW_CONDITIONAL_NZ)
>>   continue;
>>  
>>bool read_flag = false;
>>foreach_inst_in_block_reverse_starting_from(vec4_instruction, 
>> scan_inst, inst) {
>> + /* A CMP with a second source of zero can match with anything.  A 
>> CMP
>> +  * with a second source that is not zero can only match with an ADD
>> +  * instruction.
>> +  */
>> + if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) {
>> +bool negate;

Re: [Mesa-dev] Removing GRALLOC_MODULE_PERFORM_GET_DRM_FD

2018-03-22 Thread Robert Foss


Hey Tomasz,

On 03/22/2018 09:27 AM, Tomasz Figa wrote:

Hi Stefan,

On Thu, Mar 22, 2018 at 8:42 AM, Stefan Schake  wrote:

Hey Robert,

On Wed, Mar 21, 2018 at 4:16 PM, Robert Foss  wrote:

Hey,

I've started looking into removing the gralloc method
GRALLOC_MODULE_PERFORM_GET_DRM_FD.

The issues around this seems to be two parts:
1) Finding the right device to open
2) Sharing the device between components

Sharing the device between components
-

Currently the device is used by drm_hwc, gbm_gralloc and mesa.

drm_hwc opens the *primary* node in DrmResources::Init() and creates an
internal model of what properties/components the device has.

gbm_gralloc uses the *render* node during in gbm_dev_create().

Mesa uses uses the *render* node during dri_screen creation in
dri2_create_screen() and for loading the driver in
dri2_initialize_android().

However, problematically, drm_hwc uses OpenGL composition as a fallback
method, and when doing so mesa has to be able to import buffers, which means
mesa has to use a *primary* node.

The way this is currently worked around in production systems seems to be to
disable drm master authentication. This is at least what ChromeOS & Intel
are doing as far as I understand it.



Thanks for kicking this off.

I've done a few tests on 2) with VC4 and 8.1.0_r18. With drm_hwc the primary
or master on card0 and gbm_gralloc & Mesa each getting their own fd from
render128, I didn't need any of the DRM authentication hacks in the kernel
anymore. That's with full overlay composition, everything forced to hwui GL
composition or everything done through my hacked up ES2 version of glworker
in drm_hwc (well it made it to launcher until succumbing to a resource leak).
So I don't think mesa would need a master node and could make do with render.


Thanks for checking this. It seems to match my assumptions, which I
described in my reply to Rob's email.


Alright, so some kind of probing seems to be the way forward then.
What I'm wondering is what kind of properties of a render node would be the best
to match against.

For a quick reference of what information is available through drmGetDevices2, 
ran drmdevice[1], which gave this output:


Opening device 0 node /dev/dri/renderD129
device[0]
available_nodes 0005
nodes
nodes[0] /dev/dri/card1
nodes[2] /dev/dri/renderD129
bustype 
businfo
pci
domain  
bus 00
dev 02
func0
deviceinfo
pci
vendor_id   8086
device_id   191b
subvendor_id1028
subdevice_id06e4
revision_id 06


[1] https://github.com/grate-driver/libdrm/blob/master/tests/drmdevice.c





The one thing that mesa on a render node definitely breaks is flink/GEM names
which drm_gralloc uses (the Android-x86 version anyway). No flink anything
with render nodes; drm_gralloc would have to move to dmabuf fds.


I really wonder why those are still in use...



That said, it would finally get rid of the strict coupling between Mesa and
gralloc. Ripping out the PERFORM and drm_gralloc facsimile in gbm_gralloc
saves a big bunch of code:

https://github.com/stschake/gbm_gralloc/tree/libdrm_handle_def

With more in mesa/platform_android from the flink stuff.


Nice diffstat. ;)

Best regards,
Tomasz


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[Mesa-dev] [PATCH] radv: disable binning state in some situations

2018-03-22 Thread Samuel Pitoiset

This is imported from RadeonSI/ADMVLK. That might or might not
improve performance. Anyway, it's still disabled by default.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_pipeline.c | 56 +-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index dd5baec117..6c0d552c81 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2134,6 +2134,59 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, 
const VkGraphicsPipelineCr
return extent;
 }
 
+static bool
+radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo 
*pCreateInfo)
+{
+   assert(pCreateInfo);
+   return pCreateInfo->depthTestEnable &&
+  pCreateInfo->depthWriteEnable &&
+  pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
+}
+
+static bool
+radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo 
*pCreateInfo)
+{
+   assert(pCreateInfo);
+   return pCreateInfo->stencilTestEnable &&
+  (pCreateInfo->front.failOp != VK_STENCIL_OP_KEEP ||
+   pCreateInfo->front.passOp != VK_STENCIL_OP_KEEP ||
+   pCreateInfo->front.depthFailOp != VK_STENCIL_OP_KEEP ||
+   pCreateInfo->back.failOp != VK_STENCIL_OP_KEEP ||
+   pCreateInfo->back.passOp != VK_STENCIL_OP_KEEP ||
+   pCreateInfo->back.depthFailOp != VK_STENCIL_OP_KEEP);
+}
+
+static bool
+radv_should_enable_pbb(struct radv_pipeline *pipeline,
+  const VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+   RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
+   struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
+   struct radv_shader_variant *ps = 
pipeline->shaders[MESA_SHADER_FRAGMENT];
+
+   if (!pipeline->device->pbb_allowed)
+   return false;
+
+   /* Whether we can disable binning state based on the pixel shader, MSAA
+* states and depth/stencil writes.
+*/
+   bool ps_can_kill = ps->info.fs.can_discard ||
+  ps->info.info.ps.writes_sample_mask ||
+  pCreateInfo->pMultisampleState;
+   bool ps_can_reject_z_trivially = !ps->info.info.ps.writes_z;
+   bool ds_write_enabled =
+   pCreateInfo->pDepthStencilState &&
+   subpass->depth_stencil_attachment.attachment != 
VK_ATTACHMENT_UNUSED &&
+   (radv_is_depth_write_enabled(pCreateInfo->pDepthStencilState) ||
+
radv_is_stencil_write_enabled(pCreateInfo->pDepthStencilState));
+
+   /* Disable binning state if PS can kill trivially with DB writes. */
+   if (ps_can_kill && ps_can_reject_z_trivially && ds_write_enabled)
+   return false;
+
+   return true;
+}
+
 static void
 radv_pipeline_generate_binning_state(struct radeon_winsys_cs *cs,
 struct radv_pipeline *pipeline,
@@ -2168,7 +2221,8 @@ radv_pipeline_generate_binning_state(struct 
radeon_winsys_cs *cs,
unreachable("unhandled family while determining binning 
state.");
}
 
-   if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) 
{
+   if (radv_should_enable_pbb(pipeline, pCreateInfo) &&
+   bin_size.width && bin_size.height) {
pa_sc_binner_cntl_0 =
S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
S_028C44_BIN_SIZE_X(bin_size.width == 16) |
-- 
2.16.2

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[Mesa-dev] [PATCH v3] radv: fix scanning output_usage_mask with structs

2018-03-22 Thread Samuel Pitoiset

To fix a regression in:
dEQP-VK.spirv_assembly.instruction.graphics.variable_init.output.struct

And the following regressions (Polaris only):
dEQP-VK.glsl.indexing.varying_array.*

v3: account for slots (Dave)
v2: handle indirect array accesses (Dave)

Fixes: f3275ca01c ("ac/nir: only enable used channels when exporting 
parameters")
Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_shader_info.c | 56 ---
 1 file changed, 52 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_shader_info.c 
b/src/amd/vulkan/radv_shader_info.c
index 9c18791524..c8853f 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -47,6 +47,46 @@ static void mark_tess_output(struct radv_shader_info *info,
info->tcs.outputs_written |= (mask << param);
 }
 
+static void get_deref_offset(nir_deref_var *deref, unsigned *const_out)
+{
+   nir_deref *tail = >deref;
+   unsigned const_offset = 0;
+
+   if (deref->var->data.compact) {
+   assert(tail->child->deref_type == nir_deref_type_array);
+   
assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
+
+   nir_deref_array *deref_array = nir_deref_as_array(tail->child);
+   /* We always lower indirect dereferences for "compact" array 
vars. */
+   assert(deref_array->deref_array_type == 
nir_deref_array_type_direct);
+
+   *const_out = deref_array->base_offset;
+   return;
+   }
+
+   while (tail->child != NULL) {
+   const struct glsl_type *parent_type = tail->type;
+   tail = tail->child;
+
+   if (tail->deref_type == nir_deref_type_array) {
+   nir_deref_array *deref_array = nir_deref_as_array(tail);
+   unsigned size = glsl_count_attribute_slots(tail->type, 
false);
+
+   const_offset += size * deref_array->base_offset;
+   } else if (tail->deref_type == nir_deref_type_struct) {
+   nir_deref_struct *deref_struct = 
nir_deref_as_struct(tail);
+
+   for (unsigned i = 0; i < deref_struct->index; i++) {
+   const struct glsl_type *ft = 
glsl_get_struct_field(parent_type, i);
+   const_offset += glsl_count_attribute_slots(ft, 
false);
+   }
+   } else
+   unreachable("unsupported deref type");
+   }
+
+   *const_out = const_offset;
+}
+
 static void
 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
  struct radv_shader_info *info)
@@ -174,15 +214,23 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
nir_variable *var = dvar->var;
 
if (var->data.mode == nir_var_shader_out) {
+   unsigned attrib_count = 
glsl_count_attribute_slots(var->type, false);
unsigned idx = var->data.location;
unsigned comp = var->data.location_frac;
+   unsigned const_offset = 0;
+
+   get_deref_offset(dvar, _offset);
 
if (nir->info.stage == MESA_SHADER_VERTEX) {
-   info->vs.output_usage_mask[idx] |=
-   instr->const_index[0] << comp;
+   for (unsigned i = 0; i < attrib_count; i++) {
+   info->vs.output_usage_mask[idx + i + 
const_offset] |=
+   instr->const_index[0] << comp;
+   }
} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
-   info->tes.output_usage_mask[idx] |=
-   instr->const_index[0] << comp;
+   for (unsigned i = 0; i < attrib_count; i++) {
+   info->tes.output_usage_mask[idx + i + 
const_offset] |=
+   instr->const_index[0] << comp;
+   }
} else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
unsigned param = 
shader_io_get_unique_index(idx);
const struct glsl_type *type = var->type;
-- 
2.16.2

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[Mesa-dev] [Bug 105670] [regression][hang] Trine1EE hangs GPU after loading screen on Mesa3D-17.3 and later

2018-03-22 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=105670

--- Comment #3 from Roland Scheidegger  ---
(In reply to Gert Wollny from comment #2)
> Regarding bisecting this, after a failure one usually must reboot the
> system, otherwise the graphics card is in a bad state. But given the nature
> of the bug one should also be able to reproduce the endless loop with
> LIBGL_ALWAYS_SOFTWARE=1 thereby not clobbering the hardware.

Just to avoid any confusion, llvmpipe won't show an infinite loop, since it
uses a loop limiter on all loops (might still take quite some time, though).
But of course you can still see the bogus tgsi.

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Re: [Mesa-dev] [PATCH] i965/perf: fix config registration when uploading to kernel

2018-03-22 Thread Kenneth Graunke

On Thursday, March 22, 2018 9:02:11 AM PDT Lionel Landwerlin wrote:
> When registring configuration to the kernel for the first time, we run
> into an issue where the id number is not properly set. As a result
> when trying to use that id later on, we get an error.
> 
> This issue manifest itself the first time you use frameretrace after
> reboot, subsequent runs are fine.
> 
> Fixes: 27ee83eaf7e9 ("i965: perf: add support for userspace configurations")
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
> b/src/mesa/drivers/dri/i965/brw_performance_query.c
> index 8b3f38966ca..4144aa3c9b8 100644
> --- a/src/mesa/drivers/dri/i965/brw_performance_query.c
> +++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
> @@ -1905,7 +1905,7 @@ init_oa_configs(struct brw_context *brw)
>   continue;
>}
>  
> -  register_oa_config(brw, query, config_id);
> +  register_oa_config(brw, query, ret);
>DBG("metric set: %s (added)\n", query->guid);
> }
>  }
> 

Reviewed-by: Kenneth Graunke 


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Re: [Mesa-dev] [PATCH v3 5/8] intel: devinfo: add helper functions to fill fusing masks values

2018-03-22 Thread Kenneth Graunke

On Wednesday, March 21, 2018 7:12:50 AM PDT Lionel Landwerlin wrote:
> There are a couple of ways we can get the fusing information from the
> kernel :
> 
>   - Through DRM_I915_GETPARAM with the SLICE_MASK/SUBSLICE_MASK
> parameters
> 
>   - Through the new DRM_IOCTL_I915_QUERY by requesting the
> DRM_I915_QUERY_TOPOLOGY_INFO
> 
> The second method is more accurate and also gives us the EUs fusing
> masks. It's also a requirement for CNL as this platform has asymetric
> subslices and the first method SUBSLICE_MASK value is assumed uniform
> across slices.
> 
> v2: Change gen_device_info_update_from_masks() to generate topology
> and call into gen_device_info_update_from_topology (Lionel/Ken)
> 
> Signed-off-by: Lionel Landwerlin 

With the num_eus_per_subslice asserts gone and division turned to
DIV_ROUND_UP, this is:

Reviewed-by: Kenneth Graunke 

(Lionel and I discovered that there are 23 EU and 47 EU parts, where
one subslice has 1 fewer EU...so they're not uniformly distributed like
the code here assumed...)


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Re: [Mesa-dev] [PATCH v2 1/7] waylan-drm: do not distribute generated sources

2018-03-22 Thread Emil Velikov

On 22 March 2018 at 17:01, Daniel Stone  wrote:
> Hi Juan,
>
> On 22 March 2018 at 16:49, Juan A. Suarez Romero  wrote:
>> Instead we will re-generate them again on building.
>
> Thanks for sending the v2 - that looks good to me. There was some kind
> of problem with having the sources in BUILT_SOURCES though, which Emil
> might be able to remember. Is it necessary to have it there,
> especially if we have hardcoded Makefile deps already?
>
BUILT_SOURCES is effectively "as you come in this folder, first
build/generate those files. regardless if you need them or not."
Which will effectively fail if wayland-scanner is missing.

When you remove them from the list, they will be generated only as
needed. Building with wayland will list those files as deps, hence
they'll be generated.

With that addressed the patch is
Reviewed-by: Emil Velikov 

Please push the non-controversial patches.

Thanks
Emil
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Re: [Mesa-dev] [PATCH v2 1/7] waylan-drm: do not distribute generated sources

2018-03-22 Thread Juan A. Suarez Romero

On Thu, 2018-03-22 at 17:01 +, Daniel Stone wrote:
> Hi Juan,
> 
> On 22 March 2018 at 16:49, Juan A. Suarez Romero  wrote:
> > Instead we will re-generate them again on building.
> 
> Thanks for sending the v2 - that looks good to me. There was some kind
> of problem with having the sources in BUILT_SOURCES though, which Emil
> might be able to remember. Is it necessary to have it there,
> especially if we have hardcoded Makefile deps already?
> 

Hmm... probably Emil knows better. AFAIK it only keeps the list of generated
files, so we can later clean them up. 

J.A.

> Cheers,
> Daniel
> 
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Re: [Mesa-dev] [PATCH v3 3/8] drm-uapi: bump headers

2018-03-22 Thread Kenneth Graunke

On Wednesday, March 21, 2018 7:12:48 AM PDT Lionel Landwerlin wrote:
> Required updates from drm-next for changes in i965.
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  include/drm-uapi/README  |   8 +--
>  include/drm-uapi/drm_mode.h  |  43 +---
>  include/drm-uapi/i915_drm.h  | 152 
> +--
>  include/drm-uapi/tegra_drm.h |  22 +--
>  4 files changed, 189 insertions(+), 36 deletions(-)

Acked-by: Kenneth Graunke 

Though, I honestly don't think acks or reviews should be required for
simply updating headers generated by the kernel.  Assuming you pull them
from drm-next, I say just go for it.

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Re: [Mesa-dev] [PATCH v2 1/7] waylan-drm: do not distribute generated sources

2018-03-22 Thread Daniel Stone

Hi Juan,

On 22 March 2018 at 16:49, Juan A. Suarez Romero  wrote:
> Instead we will re-generate them again on building.

Thanks for sending the v2 - that looks good to me. There was some kind
of problem with having the sources in BUILT_SOURCES though, which Emil
might be able to remember. Is it necessary to have it there,
especially if we have hardcoded Makefile deps already?

Cheers,
Daniel
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[Mesa-dev] [Bug 105670] [regression][hang] Trine1EE hangs GPU after loading screen on Mesa3D-17.3 and later

2018-03-22 Thread bugzilla-daemon

https://bugs.freedesktop.org/show_bug.cgi?id=105670

--- Comment #2 from Gert Wollny  ---
I can confirm this on Radeon 6870 HD. 

I was able to track the issue to the series beginning with  

   ab23b759f24 glsl: don't drop instructions from unreachable 
   terminators continue branch

The first time around I had a few difficulties get the correct patch, it seems
to be either 646621c66da9 or 7a7fb90af75. In any case, yes it is related to
loop unrolling.

The original TGSI goes like 

BGNLOOP
  ISGE TEMP[13].x, TEMP[8]., IMM[7].
  UIF TEMP[13].
 BRK
  ENDIF
  ...
ENDLOOP

and with the series in question applied it is 

BGNLOOP
  ISLT TEMP[13].x, TEMP[8]., IMM[7].
  UIF TEMP[13].
  ...
  ENDI
ENDLOOP

This UIF should have an else path with the BRK to resemble the original code. 
(There are more BRK statements in the LOOP but they are the same in both
versions.

Regarding bisecting this, after a failure one usually must reboot the system,
otherwise the graphics card is in a bad state. But given the nature of the bug
one should also be able to reproduce the endless loop with
LIBGL_ALWAYS_SOFTWARE=1 thereby not clobbering the hardware.

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[Mesa-dev] [PATCH v2 5/7] swr/rast: autotools: add events_private.proto in dist tarball.

2018-03-22 Thread Juan A. Suarez Romero

Reviewed-by: Emil Velikov 
---
 src/gallium/drivers/swr/Makefile.am | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/swr/Makefile.am 
b/src/gallium/drivers/swr/Makefile.am
index 13c7f8b7345..5ec9213c349 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -368,6 +368,7 @@ EXTRA_DIST = \
rasterizer/codegen/meson.build \
rasterizer/core/backends/meson.build \
rasterizer/archrast/events.proto \
+   rasterizer/archrast/events_private.proto \
rasterizer/codegen/gen_llvm_ir_macros.py \
rasterizer/codegen/gen_llvm_types.py \
rasterizer/codegen/gen_archrast.py \
-- 
2.14.3

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[Mesa-dev] [PATCH v2 7/7] broadcom/vc4: add path to nir_builder.h

2018-03-22 Thread Juan A. Suarez Romero

As the other VC4 files do. Otherwise, it won't find nir_builder.h

v2: add path in source code rather changing autotools (Emil)

Reviewed-by: Emil Velikov 
---
 src/gallium/drivers/vc4/vc4_blit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/vc4/vc4_blit.c 
b/src/gallium/drivers/vc4/vc4_blit.c
index 7543e9d4aa0..d3cc5152a2d 100644
--- a/src/gallium/drivers/vc4/vc4_blit.c
+++ b/src/gallium/drivers/vc4/vc4_blit.c
@@ -24,7 +24,7 @@
 #include "util/u_format.h"
 #include "util/u_surface.h"
 #include "util/u_blitter.h"
-#include "nir_builder.h"
+#include "compiler/nir/nir_builder.h"
 #include "vc4_context.h"
 
 static struct pipe_surface *
-- 
2.14.3

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[Mesa-dev] [PATCH v2 6/7] autotools: add tegra header files

2018-03-22 Thread Juan A. Suarez Romero

Reviewed-by: Emil Velikov 
---
 Makefile.am   | 1 +
 src/gallium/winsys/tegra/drm/Makefile.sources | 1 +
 2 files changed, 2 insertions(+)

diff --git a/Makefile.am b/Makefile.am
index de6921bf1fc..804b1d85353 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -75,6 +75,7 @@ noinst_HEADERS = \
include/drm-uapi/drm_fourcc.h \
include/drm-uapi/drm_mode.h \
include/drm-uapi/i915_drm.h \
+   include/drm-uapi/tegra_drm.h \
include/drm-uapi/vc4_drm.h \
include/D3D9 \
include/GL/wglext.h \
diff --git a/src/gallium/winsys/tegra/drm/Makefile.sources 
b/src/gallium/winsys/tegra/drm/Makefile.sources
index fe0d5c42e72..29a0edc9c43 100644
--- a/src/gallium/winsys/tegra/drm/Makefile.sources
+++ b/src/gallium/winsys/tegra/drm/Makefile.sources
@@ -1,2 +1,3 @@
 C_SOURCES := \
+   tegra_drm_public.h \
tegra_drm_winsys.c
-- 
2.14.3

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[Mesa-dev] [PATCH v2 3/7] anv/radv: autotools: include vulkan_*.h headers

2018-03-22 Thread Juan A. Suarez Romero

Reviewed-by: Emil Velikov 
---
 src/amd/vulkan/Makefile.am   | 4 
 src/intel/Makefile.vulkan.am | 4 
 2 files changed, 8 insertions(+)

diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index cc1b53980fd..00b808229fa 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -23,6 +23,10 @@ include Makefile.sources
 
 noinst_HEADERS = \
$(top_srcdir)/include/vulkan/vk_platform.h \
+   $(top_srcdir)/include/vulkan/vulkan_core.h \
+   $(top_srcdir)/include/vulkan/vulkan_wayland.h \
+   $(top_srcdir)/include/vulkan/vulkan_xcb.h \
+   $(top_srcdir)/include/vulkan/vulkan_xlib.h \
$(top_srcdir)/include/vulkan/vulkan.h
 
 lib_LTLIBRARIES = libvulkan_radeon.la
diff --git a/src/intel/Makefile.vulkan.am b/src/intel/Makefile.vulkan.am
index 6b71df6319a..3d5e8e5cfdd 100644
--- a/src/intel/Makefile.vulkan.am
+++ b/src/intel/Makefile.vulkan.am
@@ -84,6 +84,10 @@ vulkan_includedir = $(includedir)/vulkan
 
 noinst_HEADERS += \
$(top_srcdir)/include/vulkan/vk_platform.h \
+   $(top_srcdir)/include/vulkan/vulkan_core.h \
+   $(top_srcdir)/include/vulkan/vulkan_wayland.h \
+   $(top_srcdir)/include/vulkan/vulkan_xcb.h \
+   $(top_srcdir)/include/vulkan/vulkan_xlib.h \
$(top_srcdir)/include/vulkan/vulkan.h
 
 vulkan_include_HEADERS = \
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 0/8] Fix several issues/missings in make dist/distcheck

2018-03-22 Thread Juan A. Suarez Romero

On Thu, 2018-03-22 at 14:16 +, Emil Velikov wrote:
> Can we merge the series as-is, until we untangle the dist bits?

Just sent a V2 following Daniel proposal.


J.A.

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[Mesa-dev] [PATCH v2 2/7] nir: autotools, meson: add GLSL.ext.AMD.h in the files list

2018-03-22 Thread Juan A. Suarez Romero

Reviewed-by: Emil Velikov 
---
 src/compiler/Makefile.sources | 1 +
 src/compiler/nir/meson.build  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index b231f2fa972..2dc48365507 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -295,6 +295,7 @@ SPIRV_GENERATED_FILES = \
spirv/vtn_gather_types.c
 
 SPIRV_FILES = \
+   spirv/GLSL.ext.AMD.h \
spirv/GLSL.std.450.h \
spirv/nir_spirv.h \
spirv/spirv.h \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index e97ce0d1e2d..887035d7595 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -183,6 +183,7 @@ files_libnir = files(
   'nir_vla.h',
   'nir_worklist.c',
   'nir_worklist.h',
+  '../spirv/GLSL.ext.AMD.h',
   '../spirv/GLSL.std.450.h',
   '../spirv/nir_spirv.h',
   '../spirv/spirv.h',
-- 
2.14.3

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[Mesa-dev] [PATCH v2 4/7] radv: autotools: add radv_extensions.h in the generated VULKAN list

2018-03-22 Thread Juan A. Suarez Romero

Reviewed-by: Emil Velikov 
---
 src/amd/vulkan/Makefile.sources | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/Makefile.sources b/src/amd/vulkan/Makefile.sources
index b0a8f8b97d8..ccb956a2396 100644
--- a/src/amd/vulkan/Makefile.sources
+++ b/src/amd/vulkan/Makefile.sources
@@ -83,5 +83,6 @@ VULKAN_WSI_X11_FILES := \
 VULKAN_GENERATED_FILES := \
radv_entrypoints.c \
radv_entrypoints.h \
-   radv_extensions.c
+   radv_extensions.c \
+   radv_extensions.h
 
-- 
2.14.3

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[Mesa-dev] [PATCH v2 1/7] waylan-drm: do not distribute generated sources

2018-03-22 Thread Juan A. Suarez Romero

Instead we will re-generate them again on building.
---
 src/egl/Makefile.am | 10 +-
 src/egl/wayland/wayland-drm/Makefile.am |  8 ++--
 src/vulkan/Makefile.am  | 11 +--
 3 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 285d3caa9ef..3bfce3313db 100644
--- a/src/egl/Makefile.am
+++ b/src/egl/Makefile.am
@@ -50,6 +50,7 @@ libEGL_common_la_LIBADD = \
$(EGL_LIB_DEPS)
 
 dri2_backend_FILES =
+dri2_backend_GENERATED_FILES =
 dri3_backend_FILES =
 
 if HAVE_PLATFORM_X11
@@ -87,7 +88,8 @@ AM_CFLAGS += $(WAYLAND_SERVER_CFLAGS)
 libEGL_common_la_LIBADD += 
$(top_builddir)/src/egl/wayland/wayland-drm/libwayland-drm.la
 libEGL_common_la_LIBADD += $(WAYLAND_SERVER_LIBS)
 dri2_backend_FILES += \
-   drivers/dri2/platform_wayland.c \
+   drivers/dri2/platform_wayland.c
+dri2_backend_GENERATED_FILES += \
drivers/dri2/linux-dmabuf-unstable-v1-protocol.c \
drivers/dri2/linux-dmabuf-unstable-v1-client-protocol.h
 endif
@@ -118,6 +120,12 @@ AM_CFLAGS += \
-DDEFAULT_DRIVER_DIR=\"$(DRI_DRIVER_SEARCH_DIR)\" \
-D_EGL_BUILT_IN_DRIVER_DRI2
 
+BUILT_SOURCES += \
+   $(dri2_backend_GENERATED_FILES)
+
+nodist_libEGL_common_la_SOURCES = \
+   $(dri2_backend_GENERATED_FILES)
+
 libEGL_common_la_SOURCES += \
$(dri2_backend_core_FILES) \
$(dri2_backend_FILES) \
diff --git a/src/egl/wayland/wayland-drm/Makefile.am 
b/src/egl/wayland/wayland-drm/Makefile.am
index c10c4349d48..684b389a025 100644
--- a/src/egl/wayland/wayland-drm/Makefile.am
+++ b/src/egl/wayland/wayland-drm/Makefile.am
@@ -4,10 +4,14 @@ AM_CFLAGS = -I$(top_srcdir)/include \
$(WAYLAND_SERVER_CFLAGS)
 
 noinst_LTLIBRARIES = libwayland-drm.la
+
+nodist_libwayland_drm_la_SOURCES =\
+   wayland-drm-protocol.c
+
 libwayland_drm_la_SOURCES = \
wayland-drm.c \
-   wayland-drm.h \
-   wayland-drm-protocol.c
+   wayland-drm.h
+
 noinst_HEADERS = wayland-drm.h
 
 EXTRA_DIST = wayland-drm.xml meson.build
diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am
index e6d4277f92f..fdfd8a5d42a 100644
--- a/src/vulkan/Makefile.am
+++ b/src/vulkan/Makefile.am
@@ -21,7 +21,8 @@ VULKAN_UTIL_SOURCES = \
$(VULKAN_UTIL_GENERATED_FILES)
 
 BUILT_SOURCES = \
-   $(VULKAN_UTIL_GENERATED_FILES)
+   $(VULKAN_UTIL_GENERATED_FILES) \
+   $(VULKAN_WSI_WAYLAND_GENERATED_FILES)
 
 util/vk_enum_to_str.c util/vk_enum_to_str.h: util/gen_enum_to_str.py \
$(vulkan_api_xml) $(vk_android_native_buffer_xml)
@@ -46,6 +47,8 @@ AM_CFLAGS = \
$(LIBDRM_CFLAGS) \
$(VISIBILITY_CFLAGS)
 
+VULKAN_WSI_GENERATED_SOURCES =
+
 VULKAN_WSI_SOURCES = \
$(VULKAN_WSI_FILES)
 
@@ -91,9 +94,13 @@ AM_CPPFLAGS += \
-DVK_USE_PLATFORM_WAYLAND_KHR
 
 VULKAN_WSI_SOURCES += \
-   $(VULKAN_WSI_WAYLAND_FILES) \
+   $(VULKAN_WSI_WAYLAND_FILES)
+
+VULKAN_WSI_GENERATED_SOURCES += \
$(VULKAN_WSI_WAYLAND_GENERATED_FILES)
 
 endif
 
+nodist_libvulkan_wsi_la_SOURCES = $(VULKAN_WSI_GENERATED_SOURCES)
+
 libvulkan_wsi_la_SOURCES = $(VULKAN_WSI_SOURCES)
-- 
2.14.3

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[Mesa-dev] [PATCH v2 0/7] Fix several issues/missings in make dist/distcheck

2018-03-22 Thread Juan A. Suarez Romero

This series fix several issues that happen when running "./autogen.sh && make
{dist, distcheck}".

This V2 is similar to V1, except for the first patch: we now exclude from dist 
the generated wayland-scanner files.

Juan A. Suarez Romero (7):
  waylan-drm: do not distribute generated sources
  nir: autotools, meson: add GLSL.ext.AMD.h in the files list
  anv/radv: autotools: include vulkan_*.h headers
  radv: autotools: add radv_extensions.h in the generated VULKAN list
  swr/rast: autotools: add events_private.proto in dist tarball.
  autotools: add tegra header files
  broadcom/vc4: add path to nir_builder.h

 Makefile.am   |  1 +
 src/amd/vulkan/Makefile.am|  4 
 src/amd/vulkan/Makefile.sources   |  3 ++-
 src/compiler/Makefile.sources |  1 +
 src/compiler/nir/meson.build  |  1 +
 src/egl/Makefile.am   | 10 +-
 src/egl/wayland/wayland-drm/Makefile.am   |  8 ++--
 src/gallium/drivers/swr/Makefile.am   |  1 +
 src/gallium/drivers/vc4/vc4_blit.c|  2 +-
 src/gallium/winsys/tegra/drm/Makefile.sources |  1 +
 src/intel/Makefile.vulkan.am  |  4 
 src/vulkan/Makefile.am| 11 +--
 12 files changed, 40 insertions(+), 7 deletions(-)

-- 
2.14.3

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Re: [Mesa-dev] [PATCH] gallium/u_vbuf: Protect against overflow with large instance divisors.

2018-03-22 Thread Brian Paul


On 03/21/2018 11:06 AM, Eric Anholt wrote:

GTF-GLES3.gtf.GL3Tests.instanced_arrays.instanced_arrays_divisor uses -1
as a divisor,


Since GL's vertex attrib instance divisor is a GLuint, we can 
alternately say the divisor is ~0, right?




so we would overflow to count=0 and upload no data,
triggering the assert below.  We want to upload 1 element in this case,
fixing the test on VC5.
---
  src/gallium/auxiliary/util/u_vbuf.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_vbuf.c 
b/src/gallium/auxiliary/util/u_vbuf.c
index 95d7990c6ca4..9073f3feed98 100644
--- a/src/gallium/auxiliary/util/u_vbuf.c
+++ b/src/gallium/auxiliary/util/u_vbuf.c
@@ -936,7 +936,12 @@ u_vbuf_upload_buffers(struct u_vbuf *mgr,
   size = mgr->ve->src_format_size[i];
} else if (instance_div) {
   /* Per-instance attrib. */
- unsigned count = (num_instances + instance_div - 1) / instance_div;
+ unsigned count = (num_instances + instance_div - 1);
+
+ if (count < num_instances)
+count = 0x;
+ count /= instance_div;


I've been staring at this for a while but I'm still not sure I 
understand what's happening.  Can you add a comment at least?




+
   first += vb->stride * start_instance;
   size = vb->stride * (count - 1) + mgr->ve->src_format_size[i];
} else {



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Re: [Mesa-dev] [PATCH] egl/wayland: Make swrast display_sync the correct queue

2018-03-22 Thread Eric Engestrom

On Thursday, 2018-03-22 15:28:49 +, Daniel Stone wrote:
> On 22 March 2018 at 15:20, Derek Foreman  wrote:
> > commit 03dd9a88b0be17ff0ce91e92f6902a9a85ba584a introduced per surface
> > queues, but the display_sync for swrast_commit_backbuffer remained on
> > the old queue.  This is likely to break when dispatching the correct
> > queue at the top of function (which can't dispatch the sync callback
> > we're waiting for).
> >
> > The easiest known reproduction case is running weston-subsurfaces under
> > weston --use-pixman
> 
> Oh dear. Pushed now with review. For future though, can you please use
> the 'Fixes:' annotation, which in this case would've been for
> 03dd9a88b0be? Don't feel too bad though, because I also forgot to add
> it when pushing.

We want this in stable, right?
Would've been done automatically with the Fixes: tag, but I cc'ed
mesa-stable@ now, so it's nominated :)

> 
> Cheers,
> Daniel
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Re: [Mesa-dev] [PATCH] st: Allow accelerated CopyTexImage from RGBA to RGB.

2018-03-22 Thread Brian Paul


On 03/21/2018 02:54 PM, Eric Anholt wrote:

There's nothing to worry about here -- the A channel just gets dropped by
the blit.  This avoids a segfault in the fallback path when copying from a
RGBA16_SINT renderbuffer to a RGB16_SINT destination represented by an
RGBA16_SINT texture (the fallback path tries to get/fetch to float
buffers, but the float pack/unpack functions are NULL for SINT/UINT).

Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgba16i on VC5.
---
  src/mesa/state_tracker/st_cb_texture.c | 6 --
  1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_texture.c 
b/src/mesa/state_tracker/st_cb_texture.c
index 6345ead6396b..469a82a75390 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2327,8 +2327,10 @@ st_CopyTexSubImage(struct gl_context *ctx, GLuint dims,
 /* The base internal format must match the mesa format, so make sure
  * e.g. an RGB internal format is really allocated as RGB and not as RGBA.
  */
-   if (texImage->_BaseFormat !=
-   _mesa_get_format_base_format(texImage->TexFormat) ||
+   if ((texImage->_BaseFormat !=
+_mesa_get_format_base_format(texImage->TexFormat) &&
+(texImage->_BaseFormat != GL_RGB ||
+ _mesa_get_format_base_format(texImage->TexFormat) != GL_RGBA)) ||
 rb->_BaseFormat != _mesa_get_format_base_format(rb->Format)) {
goto fallback;
 }


When a conditional starts to get complicated like this, I consider 
putting it into helper/predicate function.  In this case, maybe 
st_texture_renderbuffer_formats_compatible().


In any case, the comment should probably be updated to say "But copying 
from RGBA to RGB is allowed" so there's no confusion between the comment 
and the conditional.


-Brian
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Re: [Mesa-dev] [PATCH 05/11] intel/compiler: Use null destination register for memory fence messages

2018-03-22 Thread Matt Turner

On Wed, Mar 21, 2018 at 3:08 PM, Francisco Jerez  wrote:
> Matt Turner  writes:
>
>> On Wed, Mar 21, 2018 at 2:56 PM, Francisco Jerez  
>> wrote:
>>> Matt Turner  writes:
>>>
 From Message Descriptor section in gfxspecs:

   "Memory fence messages without Commit Enable set do not return
anything to the thread (response length is 0 and destination
register is null)."

 This fixes a GPU hang in simulation in the piglit test
 arb_shader_image_load_store-shader-mem-barrier

>>>
>>> On what platform?
>>
>> I'm pretty sure Anuj found this in ICL. I'll revert this patch from my
>> branch and try to confirm.
>
> That sounds pretty bogus, this patch cannot possibly have any effect on
> ICL because brw_memory_fence() is already setting commit_enable
> unconditionally on Gen10+, so the destination register won't ever be
> null regardless.

I just ran the associated piglit test through simulation without this
patch, and everything passed. I'll drop the patch.
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Re: [Mesa-dev] [PATCH v2 0/8] freedreno: a2xx improvements

2018-03-22 Thread Wladimir J. van der Laan

On Thu, Mar 22, 2018 at 11:46:57AM -0400, Ilia Mirkin wrote:
> With the minor whitespace issue I pointed out (which might also apply
> to 8/8, couldn't tell), this is

Looks like there is also a case in 5/8, will go over them and resubmit the ones
with wacky spacing.
(I think the issue here is that I had set my editor for spaces due to the other
parts of mesa)

> Reviewed-by: Ilia Mirkin 

Thanks.

Wladimir
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[Mesa-dev] [PATCH] i965/perf: fix config registration when uploading to kernel

2018-03-22 Thread Lionel Landwerlin

When registring configuration to the kernel for the first time, we run
into an issue where the id number is not properly set. As a result
when trying to use that id later on, we get an error.

This issue manifest itself the first time you use frameretrace after
reboot, subsequent runs are fine.

Fixes: 27ee83eaf7e9 ("i965: perf: add support for userspace configurations")
Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 8b3f38966ca..4144aa3c9b8 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1905,7 +1905,7 @@ init_oa_configs(struct brw_context *brw)
  continue;
   }
 
-  register_oa_config(brw, query, config_id);
+  register_oa_config(brw, query, ret);
   DBG("metric set: %s (added)\n", query->guid);
}
 }
-- 
2.16.2

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Re: [Mesa-dev] [PATCH v2 0/8] freedreno: a2xx improvements

2018-03-22 Thread Ilia Mirkin

With the minor whitespace issue I pointed out (which might also apply
to 8/8, couldn't tell), this is

Reviewed-by: Ilia Mirkin 

On Thu, Mar 22, 2018 at 11:26 AM, Wladimir J. van der Laan
 wrote:
> While working on a205 support for i.MX51/53, I've also written some patches
> that are not specific to a20x but should apply to the whole a2xx range.
>
> As I'm figuring out how to handle backward compatibility to other a2xx, I
> think it makes sense to send these upstream already to reduce the patch stack.
>
> Changes since first post:
>
> - Split up rnndb patch into a patch that changes formate numeration
>   and one that changed BLEND->BLEND2.
> - fd2_emit emit_texture const correctness.
>
> I checked that there is no Gallium capability to be set for TEXTURE_RECT.
>
> Wladimir J. van der Laan (8):
>   freedreno: a2xx: Update rnndb header for formats enumeration
>   freedreno: a2xx: Change use of BLEND_ to BLEND2_
>   freedreno: a2xx: Fix fd2_tex_swiz
>   freedreno: a2xx: Prevent crash in emit_texture if view is not set
>   freedreno: a2xx: Support TEXTURE_RECT
>   freedreno: a2xx: Compressed textures support
>   freedreno: a2xx: implement SEQ/SNE instructions
>   freedreno: a2xx: Implement DP2 instruction
>
>  src/gallium/drivers/freedreno/a2xx/a2xx.xml.h | 33 +++-
>  src/gallium/drivers/freedreno/a2xx/fd2_compiler.c | 47 
> +--
>  src/gallium/drivers/freedreno/a2xx/fd2_emit.c | 13 +--
>  src/gallium/drivers/freedreno/a2xx/fd2_gmem.c |  4 +-
>  src/gallium/drivers/freedreno/a2xx/fd2_util.c | 29 +-
>  src/gallium/drivers/freedreno/a2xx/ir-a2xx.c  |  1 +
>  src/gallium/drivers/freedreno/a2xx/ir-a2xx.h  |  1 +
>  7 files changed, 90 insertions(+), 38 deletions(-)
>
> --
> 2.7.4
>
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Re: [Mesa-dev] [Freedreno] [PATCH v2 7/8] freedreno: a2xx: implement SEQ/SNE instructions

2018-03-22 Thread Ilia Mirkin

On Thu, Mar 22, 2018 at 11:26 AM, Wladimir J. van der Laan
 wrote:
> Extend translate_sge_slt to emit these, in analogous fashion
> but using CNDEv.
>
> Signed-off-by: Wladimir J. van der Laan 
> ---
>  src/gallium/drivers/freedreno/a2xx/fd2_compiler.c | 23 
> ---
>  1 file changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c 
> b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
> index 9f2fc61..52f0aba 100644
> --- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
> +++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
> @@ -829,8 +829,10 @@ translate_tex(struct fd2_compile_context *ctx,
>
>  /* SGE(a,b) = GTE((b - a), 1.0, 0.0) */
>  /* SLT(a,b) = GTE((b - a), 0.0, 1.0) */
> +/* SEQ(a,b) = EQU((b - a), 1.0, 0.0) */
> +/* SNE(a,b) = EQU((b - a), 0.0, 1.0) */
>  static void
> -translate_sge_slt(struct fd2_compile_context *ctx,
> +translate_sge_slt_seq_sne(struct fd2_compile_context *ctx,
> struct tgsi_full_instruction *inst, unsigned opc)
>  {
> struct ir2_instruction *instr;
> @@ -838,6 +840,7 @@ translate_sge_slt(struct fd2_compile_context *ctx,
> struct tgsi_src_register tmp_src;
> struct tgsi_src_register tmp_const;
> float c0, c1;
> +instr_vector_opc_t vopc;

tabs vs spaces, here and elsewhere in this commit.

>
> switch (opc) {
> default:
> @@ -845,10 +848,22 @@ translate_sge_slt(struct fd2_compile_context *ctx,
> case TGSI_OPCODE_SGE:
> c0 = 1.0;
> c1 = 0.0;
> +vopc = CNDGTEv;
> break;
> case TGSI_OPCODE_SLT:
> c0 = 0.0;
> c1 = 1.0;
> +vopc = CNDGTEv;
> +   break;
> +   case TGSI_OPCODE_SEQ:
> +   c0 = 0.0;
> +   c1 = 1.0;
> +vopc = CNDEv;
> +   break;
> +   case TGSI_OPCODE_SNE:
> +   c0 = 1.0;
> +   c1 = 0.0;
> +vopc = CNDEv;
> break;
> }
>
> @@ -859,7 +874,7 @@ translate_sge_slt(struct fd2_compile_context *ctx,
> add_src_reg(ctx, instr, >Src[0].Register)->flags |= 
> IR2_REG_NEGATE;
> add_src_reg(ctx, instr, >Src[1].Register);
>
> -   instr = ir2_instr_create_alu(next_exec_cf(ctx), CNDGTEv, ~0);
> +   instr = ir2_instr_create_alu(next_exec_cf(ctx), vopc, ~0);
> add_dst_reg(ctx, instr, >Dst[0].Register);
> /* maybe should re-arrange the syntax some day, but
>  * in assembler/disassembler and what ir.c expects
> @@ -1057,7 +1072,9 @@ translate_instruction(struct fd2_compile_context *ctx,
> break;
> case TGSI_OPCODE_SLT:
> case TGSI_OPCODE_SGE:
> -   translate_sge_slt(ctx, inst, opc);
> +case TGSI_OPCODE_SEQ:
> +case TGSI_OPCODE_SNE:
> +   translate_sge_slt_seq_sne(ctx, inst, opc);
> break;
> case TGSI_OPCODE_MAD:
> instr = ir2_instr_create_alu(cf, MULADDv, ~0);
> --
> 2.7.4
>
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[Mesa-dev] [PATCH 2/2] radv: rename VEGA10 device name

2018-03-22 Thread Samuel Pitoiset

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_device.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index e9122072a8..8c406a572c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -100,7 +100,7 @@ radv_get_device_name(enum radeon_family family, char *name, 
size_t name_len)
case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
-   case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
+   case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
default: chip_string = "AMD RADV unknown"; break;
-- 
2.16.2

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[Mesa-dev] [PATCH 1/2] radv: add support for Vega12

2018-03-22 Thread Samuel Pitoiset

Based on RadeonSI. Untested.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_device.c   | 5 -
 src/amd/vulkan/radv_pipeline.c | 1 +
 src/amd/vulkan/si_cmd_buffer.c | 1 +
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 36ba0c3833..e9122072a8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -101,6 +101,7 @@ radv_get_device_name(enum radeon_family family, char *name, 
size_t name_len)
case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
+   case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
default: chip_string = "AMD RADV unknown"; break;
}
@@ -290,7 +291,8 @@ radv_physical_device_init(struct radv_physical_device 
*device,
if (device->rad_info.family == CHIP_STONEY ||
device->rad_info.chip_class >= GFX9) {
device->has_rbplus = true;
-   device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
+   device->rbplus_allowed = device->rad_info.family == CHIP_STONEY 
||
+device->rad_info.family == CHIP_VEGA12;
}
 
/* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
@@ -1174,6 +1176,7 @@ radv_device_init_gs_info(struct radv_device *device)
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGA10:
+   case CHIP_VEGA12:
case CHIP_RAVEN:
device->gs_table_depth = 32;
return;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index dd5baec117..af1ea395d3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2155,6 +2155,7 @@ radv_pipeline_generate_binning_state(struct 
radeon_winsys_cs *cs,
 
switch (pipeline->device->physical_device->rad_info.family) {
case CHIP_VEGA10:
+   case CHIP_VEGA12:
context_states_per_bin = 1;
persistent_states_per_bin = 1;
fpovs_per_batch = 63;
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 06e8442100..0970eff103 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -509,6 +509,7 @@ si_emit_config(struct radv_physical_device *physical_device,
 
switch (physical_device->rad_info.family) {
case CHIP_VEGA10:
+   case CHIP_VEGA12:
pc_lines = 4096;
break;
case CHIP_RAVEN:
-- 
2.16.2

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Re: [Mesa-dev] [PATCH 1/5] winsys/amdgpu: always allow GTT placements on APUs

2018-03-22 Thread Christian König


Reviewed-by: Christian König 

Am 22.03.2018 um 16:03 schrieb Marek Olšák:

From: Marek Olšák 

---
  src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 12 +---
  1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 7740b46b7b9..22b5a73143d 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -402,28 +402,26 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
heap);
 }
 request.alloc_size = size;
 request.phys_alignment = alignment;
  
 if (initial_domain & RADEON_DOMAIN_VRAM)

request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
 if (initial_domain & RADEON_DOMAIN_GTT)
request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
  
-   /* If VRAM is just stolen system memory, allow both VRAM and

-* GTT, whichever has free space. If a buffer is evicted from
-* VRAM to GTT, it will stay there.
-*
-* DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
-* placements even with a low amount of stolen VRAM.
+   /* Since VRAM and GTT have almost the same performance on APUs, we could
+* just set GTT. However, in order to decrease GTT(RAM) usage, which is
+* shared with the OS, allow VRAM placements too. The idea is not to use
+* VRAM usefully, but to use it so that it's not unused and wasted.
  */
-   if (!ws->info.has_dedicated_vram && ws->info.drm_minor < 6)
+   if (!ws->info.has_dedicated_vram)
request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
  
 if (flags & RADEON_FLAG_NO_CPU_ACCESS)

request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 if (flags & RADEON_FLAG_GTT_WC)
request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
 ws->info.has_local_buffers)
request.flags |= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID;
  


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[Mesa-dev] [PATCH 1/3] st/mesa: s/unsigned/enum pipe_shader_type/

2018-03-22 Thread Brian Paul

---
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 --
 src/mesa/state_tracker/st_glsl_to_tgsi.h   | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index fc53811..5f7a0dc 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -5450,7 +5450,7 @@ struct st_translate {
const ubyte *inputMapping;
const ubyte *outputMapping;
 
-   unsigned procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
+   enum pipe_shader_type procType;  /**< PIPE_SHADER_VERTEX/FRAGMENT */
bool need_uarl;
 };
 
@@ -6290,7 +6290,7 @@ st_translate_interp(enum glsl_interp_mode glsl_qual, 
GLuint varying)
 extern "C" enum pipe_error
 st_translate_program(
struct gl_context *ctx,
-   uint procType,
+   enum pipe_shader_type procType,
struct ureg_program *ureg,
glsl_to_tgsi_visitor *program,
const struct gl_program *proginfo,
@@ -6723,6 +6723,8 @@ st_translate_program(
  }
   }
   break;
+   default:
+  ; /* nothing - silence compiler warning */
}
 
 out:
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.h 
b/src/mesa/state_tracker/st_glsl_to_tgsi.h
index f38d41d..8ccfff9 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.h
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.h
@@ -38,7 +38,7 @@ struct ureg_program;
 
 enum pipe_error st_translate_program(
struct gl_context *ctx,
-   uint procType,
+   enum pipe_shader_type procType,
struct ureg_program *ureg,
struct glsl_to_tgsi_visitor *program,
const struct gl_program *proginfo,
-- 
2.7.4

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[Mesa-dev] [PATCH 2/3] st/mesa: whitespace/formatting fixes in st_atom_constbuf.c

2018-03-22 Thread Brian Paul

---
 src/mesa/state_tracker/st_atom_constbuf.c | 57 +++
 1 file changed, 36 insertions(+), 21 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_constbuf.c 
b/src/mesa/state_tracker/st_atom_constbuf.c
index 87a72b2..0c094dc 100644
--- a/src/mesa/state_tracker/st_atom_constbuf.c
+++ b/src/mesa/state_tracker/st_atom_constbuf.c
@@ -1,8 +1,8 @@
 /**
- * 
+ *
  * Copyright 2007 VMware, Inc.
  * All Rights Reserved.
- * 
+ *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the
  * "Software"), to deal in the Software without restriction, including
@@ -10,11 +10,11 @@
  * distribute, sub license, and/or sell copies of the Software, and to
  * permit persons to whom the Software is furnished to do so, subject to
  * the following conditions:
- * 
+ *
  * The above copyright notice and this permission notice (including the
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
- * 
+ *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
@@ -22,7 +22,7 @@
  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- * 
+ *
  **/
 
 /*
@@ -52,7 +52,8 @@
  * Pass the given program parameters to the graphics pipe as a
  * constant buffer.
  */
-void st_upload_constants(struct st_context *st, struct gl_program *prog)
+void
+st_upload_constants(struct st_context *st, struct gl_program *prog)
 {
gl_shader_stage stage = prog->info.stage;
struct gl_program_parameter_list *params = prog->Parameters;
@@ -77,7 +78,8 @@ void st_upload_constants(struct st_context *st, struct 
gl_program *prog)
ati_fs->Constants[c], sizeof(GLfloat) * 4);
  else
 memcpy(params->ParameterValues + offset,
-   st->ctx->ATIFragmentShader.GlobalConstants[c], 
sizeof(GLfloat) * 4);
+   st->ctx->ATIFragmentShader.GlobalConstants[c],
+   sizeof(GLfloat) * 4);
   }
}
 
@@ -132,7 +134,8 @@ void st_upload_constants(struct st_context *st, struct 
gl_program *prog)
 /**
  * Vertex shader:
  */
-void st_update_vs_constants(struct st_context *st )
+void
+st_update_vs_constants(struct st_context *st)
 {
st_upload_constants(st, >vp->Base);
 }
@@ -140,7 +143,8 @@ void st_update_vs_constants(struct st_context *st )
 /**
  * Fragment shader:
  */
-void st_update_fs_constants(struct st_context *st )
+void
+st_update_fs_constants(struct st_context *st)
 {
st_upload_constants(st, >fp->Base);
 }
@@ -148,7 +152,8 @@ void st_update_fs_constants(struct st_context *st )
 
 /* Geometry shader:
  */
-void st_update_gs_constants(struct st_context *st )
+void
+st_update_gs_constants(struct st_context *st)
 {
struct st_common_program *gp = st->gp;
 
@@ -158,7 +163,8 @@ void st_update_gs_constants(struct st_context *st )
 
 /* Tessellation control shader:
  */
-void st_update_tcs_constants(struct st_context *st )
+void
+st_update_tcs_constants(struct st_context *st)
 {
struct st_common_program *tcp = st->tcp;
 
@@ -168,7 +174,8 @@ void st_update_tcs_constants(struct st_context *st )
 
 /* Tessellation evaluation shader:
  */
-void st_update_tes_constants(struct st_context *st )
+void
+st_update_tes_constants(struct st_context *st)
 {
struct st_common_program *tep = st->tep;
 
@@ -178,7 +185,8 @@ void st_update_tes_constants(struct st_context *st )
 
 /* Compute shader:
  */
-void st_update_cs_constants(struct st_context *st )
+void
+st_update_cs_constants(struct st_context *st)
 {
struct st_compute_program *cp = st->cp;
 
@@ -186,8 +194,9 @@ void st_update_cs_constants(struct st_context *st )
   st_upload_constants(st, >Base);
 }
 
-static void st_bind_ubos(struct st_context *st, struct gl_program *prog,
- unsigned shader_type)
+static void
+st_bind_ubos(struct st_context *st, struct gl_program *prog,
+ unsigned shader_type)
 {
unsigned i;
struct pipe_constant_buffer cb = { 0 };
@@ -224,7 +233,8 @@ static void st_bind_ubos(struct st_context *st, struct 
gl_program *prog,
}
 }
 
-void st_bind_vs_ubos(struct st_context *st)
+void
+st_bind_vs_ubos(struct st_context *st)
 {
struct gl_program *prog =
   st->ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX];
@@ -232,7 +242,8 @@ void st_bind_vs_ubos(struct st_context *st)
st_bind_ubos(st, prog, PIPE_SHADER_VERTEX);
 }
 
-void st_bind_fs_ubos(struct st_context *st)
+void
+st_bind_fs_ubos(struct st_context *st)
 {
struct gl_program *prog =

[Mesa-dev] [PATCH 3/3] st/mesa: s/unsigned/enum pipe_shader_type/ for st_bind_ubos()

2018-03-22 Thread Brian Paul

---
 src/mesa/state_tracker/st_atom_constbuf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_atom_constbuf.c 
b/src/mesa/state_tracker/st_atom_constbuf.c
index 0c094dc..6455e61 100644
--- a/src/mesa/state_tracker/st_atom_constbuf.c
+++ b/src/mesa/state_tracker/st_atom_constbuf.c
@@ -196,7 +196,7 @@ st_update_cs_constants(struct st_context *st)
 
 static void
 st_bind_ubos(struct st_context *st, struct gl_program *prog,
- unsigned shader_type)
+ enum pipe_shader_type shader_type)
 {
unsigned i;
struct pipe_constant_buffer cb = { 0 };
-- 
2.7.4

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[Mesa-dev] [PATCH 1/2] svga: replace unsigned with proper enum names

2018-03-22 Thread Brian Paul

---
 src/gallium/drivers/svga/svga_tgsi_emit.h | 12 ++--
 src/gallium/drivers/svga/svga_tgsi_insn.c | 19 ++-
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_emit.h 
b/src/gallium/drivers/svga/svga_tgsi_emit.h
index 114c956..357d772 100644
--- a/src/gallium/drivers/svga/svga_tgsi_emit.h
+++ b/src/gallium/drivers/svga/svga_tgsi_emit.h
@@ -189,7 +189,7 @@ emit_instruction(struct svga_shader_emitter *emit,
 
 /** Generate a SVGA3dShaderInstToken for the given SVGA3D shader opcode */
 static inline SVGA3dShaderInstToken
-inst_token(unsigned opcode)
+inst_token(SVGA3dShaderOpCodeType opcode)
 {
SVGA3dShaderInstToken inst;
 
@@ -205,7 +205,7 @@ inst_token(unsigned opcode)
  * with the predication flag set.
  */
 static inline SVGA3dShaderInstToken
-inst_token_predicated(unsigned opcode)
+inst_token_predicated(SVGA3dShaderOpCodeType opcode)
 {
SVGA3dShaderInstToken inst;
 
@@ -222,7 +222,7 @@ inst_token_predicated(unsigned opcode)
  * using the given comparison operator (one of SVGA3DOPCOMP_xx).
  */
 static inline SVGA3dShaderInstToken
-inst_token_setp(unsigned operator)
+inst_token_setp(SVGA3dShaderOpCodeCompFnType operator)
 {
SVGA3dShaderInstToken inst;
 
@@ -240,7 +240,7 @@ inst_token_setp(unsigned operator)
  * temp registers AND constants (see emit_def_const()).
  */
 static inline SVGA3dShaderDestToken
-dst_register(unsigned file, int number)
+dst_register(SVGA3dShaderRegType file, int number)
 {
SVGA3dShaderDestToken dest;
 
@@ -278,7 +278,7 @@ writemask(SVGA3dShaderDestToken dest, unsigned mask)
 
 /** Create a SVGA3dShaderSrcToken given a register file and number */
 static inline SVGA3dShaderSrcToken
-src_token(unsigned file, int number)
+src_token(SVGA3dShaderRegType file, int number)
 {
SVGA3dShaderSrcToken src;
 
@@ -302,7 +302,7 @@ src_token(unsigned file, int number)
 
 /** Create a src_register given a register file and register number */
 static inline struct src_register
-src_register(unsigned file, int number)
+src_register(SVGA3dShaderRegType file, int number)
 {
struct src_register src;
 
diff --git a/src/gallium/drivers/svga/svga_tgsi_insn.c 
b/src/gallium/drivers/svga/svga_tgsi_insn.c
index c08809c..c7804b2 100644
--- a/src/gallium/drivers/svga/svga_tgsi_insn.c
+++ b/src/gallium/drivers/svga/svga_tgsi_insn.c
@@ -39,7 +39,7 @@ static boolean emit_vs_postamble( struct svga_shader_emitter 
*emit );
 static boolean emit_ps_postamble( struct svga_shader_emitter *emit );
 
 
-static unsigned
+static SVGA3dShaderOpCodeType
 translate_opcode(enum tgsi_opcode opcode)
 {
switch (opcode) {
@@ -60,8 +60,8 @@ translate_opcode(enum tgsi_opcode opcode)
 }
 
 
-static unsigned
-translate_file(unsigned file)
+static SVGA3dShaderRegType
+translate_file(enum tgsi_file_type file)
 {
switch (file) {
case TGSI_FILE_TEMPORARY: return SVGA3DREG_TEMP;
@@ -1435,7 +1435,7 @@ same_register(struct src_register r1, struct src_register 
r2)
  */
 static boolean
 emit_conditional(struct svga_shader_emitter *emit,
- unsigned compare_func,
+ enum pipe_compare_func compare_func,
  SVGA3dShaderDestToken dst,
  struct src_register src0,
  struct src_register src1,
@@ -1516,7 +1516,7 @@ emit_conditional(struct svga_shader_emitter *emit,
  */
 static boolean
 emit_select(struct svga_shader_emitter *emit,
-unsigned compare_func,
+enum pipe_compare_func compare_func,
 SVGA3dShaderDestToken dst,
 struct src_register src0,
 struct src_register src1 )
@@ -1968,7 +1968,7 @@ emit_brk(struct svga_shader_emitter *emit,
  */
 static boolean
 emit_scalar_op1(struct svga_shader_emitter *emit,
-unsigned opcode,
+SVGA3dShaderOpCodeType opcode,
 const struct tgsi_full_instruction *insn)
 {
SVGA3dShaderInstToken inst;
@@ -1990,7 +1990,7 @@ emit_scalar_op1(struct svga_shader_emitter *emit,
  */
 static boolean
 emit_simple_instruction(struct svga_shader_emitter *emit,
-unsigned opcode,
+SVGA3dShaderOpCodeType opcode,
 const struct tgsi_full_instruction *insn)
 {
const struct tgsi_full_src_register *src = insn->Src;
@@ -2070,7 +2070,7 @@ emit_deriv(struct svga_shader_emitter *emit,
   return TRUE;
}
else {
-  unsigned opcode;
+  SVGA3dShaderOpCodeType opcode;
   const struct tgsi_full_src_register *reg = >Src[0];
   SVGA3dShaderInstToken inst;
   SVGA3dShaderDestToken dst;
@@ -2923,7 +2923,8 @@ svga_emit_instruction(struct svga_shader_emitter *emit,
 
default:
   {
- unsigned opcode = translate_opcode(insn->Instruction.Opcode);
+ SVGA3dShaderOpCodeType opcode =
+translate_opcode(insn->Instruction.Opcode);
 
  if (opcode == SVGA3DOP_LAST_INST)
 return FALSE;
-- 
2.7.4

[Mesa-dev] [PATCH 2/2] svga: simplify uses_flat_interp expression in emit_input_declarations()

2018-03-22 Thread Brian Paul

---
 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index 04d8303..4292894 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -2396,7 +2396,7 @@ emit_input_declarations(struct svga_shader_emitter_v10 
*emit)
emit->info.input_interpolate_loc[i]);
 
 /* keeps track if flat interpolation mode is being used */
-emit->uses_flat_interp = emit->uses_flat_interp ||
+emit->uses_flat_interp |=
(interpolationMode == VGPU10_INTERPOLATION_CONSTANT);
 
 name = VGPU10_NAME_UNDEFINED;
-- 
2.7.4

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[Mesa-dev] [PATCH 5/7] tgsi/nir: use enum tgsi_opcode

2018-03-22 Thread Brian Paul

---
 src/gallium/auxiliary/nir/tgsi_to_nir.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c 
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index bbbf101..b5b4869 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -773,8 +773,8 @@ ttn_get_src(struct ttn_compile *c, struct 
tgsi_full_src_register *tgsi_fsrc,
 {
nir_builder *b = >build;
struct tgsi_src_register *tgsi_src = _fsrc->Register;
-   unsigned tgsi_opcode = c->token->FullInstruction.Instruction.Opcode;
-   unsigned tgsi_src_type = tgsi_opcode_infer_src_type(tgsi_opcode, src_idx);
+   enum tgsi_opcode opcode = c->token->FullInstruction.Instruction.Opcode;
+   unsigned tgsi_src_type = tgsi_opcode_infer_src_type(opcode, src_idx);
bool src_is_float = !(tgsi_src_type == TGSI_TYPE_SIGNED ||
  tgsi_src_type == TGSI_TYPE_UNSIGNED);
nir_alu_src src;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] egl/wayland: Make swrast display_sync the correct queue

2018-03-22 Thread Daniel Stone

On 22 March 2018 at 15:20, Derek Foreman  wrote:
> commit 03dd9a88b0be17ff0ce91e92f6902a9a85ba584a introduced per surface
> queues, but the display_sync for swrast_commit_backbuffer remained on
> the old queue.  This is likely to break when dispatching the correct
> queue at the top of function (which can't dispatch the sync callback
> we're waiting for).
>
> The easiest known reproduction case is running weston-subsurfaces under
> weston --use-pixman

Oh dear. Pushed now with review. For future though, can you please use
the 'Fixes:' annotation, which in this case would've been for
03dd9a88b0be? Don't feel too bad though, because I also forgot to add
it when pushing.

Cheers,
Daniel
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[Mesa-dev] [PATCH 3/7] gallivm: use enum tgis_opcode

2018-03-22 Thread Brian Paul

---
 src/gallium/auxiliary/gallivm/lp_bld_tgsi.c |  8 
 src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 12 
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
index 079a6ee..64d2cd7 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
@@ -198,7 +198,7 @@ void lp_build_fetch_args(
  *- map dst x,z to src xy;
  *- map dst y,w to src zw;
  */
-static int get_src_chan_idx(unsigned opcode,
+static int get_src_chan_idx(enum tgsi_opcode opcode,
 int dst_chan_index)
 {
enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(opcode, 0);
@@ -232,10 +232,10 @@ lp_build_tgsi_inst_llvm(
struct lp_build_tgsi_context * bld_base,
const struct tgsi_full_instruction * inst)
 {
-   unsigned tgsi_opcode = inst->Instruction.Opcode;
-   const struct tgsi_opcode_info * info = tgsi_get_opcode_info(tgsi_opcode);
+   enum tgsi_opcode opcode = inst->Instruction.Opcode;
+   const struct tgsi_opcode_info * info = tgsi_get_opcode_info(opcode);
const struct lp_build_tgsi_action * action =
- _base->op_actions[tgsi_opcode];
+ _base->op_actions[opcode];
struct lp_build_emit_data emit_data;
unsigned chan_index;
LLVMValueRef val;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index fad74c6..e411f90 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -368,7 +368,8 @@ static void lp_exec_break(struct lp_exec_mask *mask,
   exec_mask, "break_full");
}
else {
-  unsigned opcode = bld_base->instructions[bld_base->pc + 
1].Instruction.Opcode;
+  enum tgsi_opcode opcode =
+ bld_base->instructions[bld_base->pc + 1].Instruction.Opcode;
   boolean break_always = (opcode == TGSI_OPCODE_ENDSWITCH ||
   opcode == TGSI_OPCODE_CASE);
 
@@ -630,7 +631,7 @@ static boolean default_analyse_is_last(struct lp_exec_mask 
*mask,
}
 
while (pc != ~0u && pc < bld_base->num_instructions) {
-  unsigned opcode = bld_base->instructions[pc].Instruction.Opcode;
+  enum tgsi_opcode opcode = bld_base->instructions[pc].Instruction.Opcode;
   switch (opcode) {
   case TGSI_OPCODE_CASE:
  if (curr_switch_stack == ctx->switch_stack_size) {
@@ -648,6 +649,8 @@ static boolean default_analyse_is_last(struct lp_exec_mask 
*mask,
  }
  curr_switch_stack--;
  break;
+  default:
+ ; /* nothing */
   }
   pc++;
}
@@ -700,7 +703,8 @@ static void lp_exec_default(struct lp_exec_mask *mask,
* which just gets rid of all case statements appearing together with
* default (or could do switch analysis at switch start time instead).
*/
-  unsigned opcode = bld_base->instructions[bld_base->pc - 
1].Instruction.Opcode;
+  enum tgsi_opcode opcode =
+ bld_base->instructions[bld_base->pc - 1].Instruction.Opcode;
   boolean ft_into = (opcode != TGSI_OPCODE_BRK &&
  opcode != TGSI_OPCODE_SWITCH);
   /*
@@ -2610,7 +2614,7 @@ near_end_of_shader(struct lp_build_tgsi_soa_context *bld,
unsigned i;
 
for (i = 0; i < 5; i++) {
-  unsigned opcode;
+  enum tgsi_opcode opcode;
 
   if (pc + i >= bld->bld_base.info->num_instructions)
  return TRUE;
-- 
2.7.4

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[Mesa-dev] [PATCH 2/7] svga: use enum tgsi_opcode

2018-03-22 Thread Brian Paul

---
 src/gallium/drivers/svga/svga_tgsi_insn.c   | 2 +-
 src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_tgsi_insn.c 
b/src/gallium/drivers/svga/svga_tgsi_insn.c
index be99ad5..c08809c 100644
--- a/src/gallium/drivers/svga/svga_tgsi_insn.c
+++ b/src/gallium/drivers/svga/svga_tgsi_insn.c
@@ -40,7 +40,7 @@ static boolean emit_ps_postamble( struct svga_shader_emitter 
*emit );
 
 
 static unsigned
-translate_opcode(uint opcode)
+translate_opcode(enum tgsi_opcode opcode)
 {
switch (opcode) {
case TGSI_OPCODE_ADD:return SVGA3DOP_ADD;
diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c 
b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
index b9b3d4f..04d8303 100644
--- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
+++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c
@@ -501,7 +501,7 @@ translate_shader_type(unsigned type)
  * as seen below.  All other opcodes are handled/translated specially.
  */
 static VGPU10_OPCODE_TYPE
-translate_opcode(unsigned opcode)
+translate_opcode(enum tgsi_opcode opcode)
 {
switch (opcode) {
case TGSI_OPCODE_MOV:
@@ -5364,7 +5364,7 @@ static boolean
 emit_simple(struct svga_shader_emitter_v10 *emit,
 const struct tgsi_full_instruction *inst)
 {
-   const unsigned opcode = inst->Instruction.Opcode;
+   const enum tgsi_opcode opcode = inst->Instruction.Opcode;
const struct tgsi_opcode_info *op = tgsi_get_opcode_info(opcode);
unsigned i;
 
@@ -5415,7 +5415,7 @@ emit_simple_1dst(struct svga_shader_emitter_v10 *emit,
  unsigned dst_count,
  unsigned dst_index)
 {
-   const unsigned opcode = inst->Instruction.Opcode;
+   const enum tgsi_opcode opcode = inst->Instruction.Opcode;
const struct tgsi_opcode_info *op = tgsi_get_opcode_info(opcode);
unsigned i;
 
@@ -5447,7 +5447,7 @@ emit_vgpu10_instruction(struct svga_shader_emitter_v10 
*emit,
 unsigned inst_number,
 const struct tgsi_full_instruction *inst)
 {
-   const unsigned opcode = inst->Instruction.Opcode;
+   const enum tgsi_opcode opcode = inst->Instruction.Opcode;
 
switch (opcode) {
case TGSI_OPCODE_ADD:
-- 
2.7.4

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[Mesa-dev] [PATCH 6/7] st/mesa,tgsi: use enum tgsi_opcode

2018-03-22 Thread Brian Paul

Need to update the tgsi code and st_glsl_to_tgsi code at the same time
to prevent compile break since C++ is much pickier about implicit
enum/unsigned casting.

Bump size of glsl_to_tgsi_instruction::op to 10 bits to be sure to
avoid MSVC signed enum overflow issue.  No change in class size.
---
 src/gallium/auxiliary/tgsi/tgsi_info.c   | 10 ++---
 src/gallium/auxiliary/tgsi/tgsi_info.h   | 10 ++---
 src/gallium/auxiliary/tgsi/tgsi_ureg.c   | 10 ++---
 src/gallium/auxiliary/tgsi/tgsi_ureg.h   | 28 ++--
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp   | 55 
 src/mesa/state_tracker/st_glsl_to_tgsi_private.h |  2 +-
 6 files changed, 58 insertions(+), 57 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c 
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index a204682..4aa6587 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -51,7 +51,7 @@ static const struct tgsi_opcode_info 
opcode_info[TGSI_OPCODE_LAST] =
 #undef OPCODE_GAP
 
 const struct tgsi_opcode_info *
-tgsi_get_opcode_info( uint opcode )
+tgsi_get_opcode_info(enum tgsi_opcode opcode)
 {
static boolean firsttime = 1;
 
@@ -85,7 +85,7 @@ static const char * const opcode_names[TGSI_OPCODE_LAST] =
 #undef OPCODE_GAP
 
 const char *
-tgsi_get_opcode_name( uint opcode )
+tgsi_get_opcode_name(enum tgsi_opcode opcode)
 {
if (opcode >= ARRAY_SIZE(opcode_names))
   return "UNK_OOB";
@@ -120,7 +120,7 @@ tgsi_get_processor_name(enum pipe_shader_type processor)
  * MOV and UCMP is special so return VOID
  */
 static inline enum tgsi_opcode_type
-tgsi_opcode_infer_type( uint opcode )
+tgsi_opcode_infer_type(enum tgsi_opcode opcode)
 {
switch (opcode) {
case TGSI_OPCODE_MOV:
@@ -246,7 +246,7 @@ tgsi_opcode_infer_type( uint opcode )
  * infer the source type of a TGSI opcode.
  */
 enum tgsi_opcode_type
-tgsi_opcode_infer_src_type(uint opcode, uint src_idx)
+tgsi_opcode_infer_src_type(enum tgsi_opcode opcode, uint src_idx)
 {
if (src_idx == 1 &&
(opcode == TGSI_OPCODE_DLDEXP || opcode == TGSI_OPCODE_LDEXP))
@@ -317,7 +317,7 @@ tgsi_opcode_infer_src_type(uint opcode, uint src_idx)
  * infer the destination type of a TGSI opcode.
  */
 enum tgsi_opcode_type
-tgsi_opcode_infer_dst_type( uint opcode, uint dst_idx )
+tgsi_opcode_infer_dst_type(enum tgsi_opcode opcode, uint dst_idx)
 {
if (dst_idx == 1 && opcode == TGSI_OPCODE_DFRACEXP)
   return TGSI_TYPE_SIGNED;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.h 
b/src/gallium/auxiliary/tgsi/tgsi_info.h
index 2c97bb6..f0bf27e 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.h
@@ -79,14 +79,14 @@ struct tgsi_opcode_info
unsigned pre_dedent:1;
unsigned post_indent:1;
enum tgsi_output_mode output_mode:4;
-   unsigned opcode:8;
+   enum tgsi_opcode opcode:10;
 };
 
 const struct tgsi_opcode_info *
-tgsi_get_opcode_info( uint opcode );
+tgsi_get_opcode_info(enum tgsi_opcode opcode);
 
 const char *
-tgsi_get_opcode_name( uint opcode );
+tgsi_get_opcode_name(enum tgsi_opcode opcode);
 
 const char *
 tgsi_get_processor_name(enum pipe_shader_type processor);
@@ -111,10 +111,10 @@ static inline bool tgsi_type_is_64bit(enum 
tgsi_opcode_type type)
 }
 
 enum tgsi_opcode_type
-tgsi_opcode_infer_src_type( uint opcode, uint src_idx );
+tgsi_opcode_infer_src_type(enum tgsi_opcode opcode, uint src_idx);
 
 enum tgsi_opcode_type
-tgsi_opcode_infer_dst_type( uint opcode, uint dst_idx );
+tgsi_opcode_infer_dst_type(enum tgsi_opcode opcode, uint dst_idx);
 
 #if defined __cplusplus
 }
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.c 
b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
index 41281da..393e015 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.c
@@ -1234,7 +1234,7 @@ ureg_emit_dst( struct ureg_program *ureg,
 }
 
 
-static void validate( unsigned opcode,
+static void validate( enum tgsi_opcode opcode,
   unsigned nr_dst,
   unsigned nr_src )
 {
@@ -1250,7 +1250,7 @@ static void validate( unsigned opcode,
 
 struct ureg_emit_insn_result
 ureg_emit_insn(struct ureg_program *ureg,
-   unsigned opcode,
+   enum tgsi_opcode opcode,
boolean saturate,
unsigned precise,
unsigned num_dst,
@@ -1392,7 +1392,7 @@ ureg_fixup_insn_size(struct ureg_program *ureg,
 
 void
 ureg_insn(struct ureg_program *ureg,
-  unsigned opcode,
+  enum tgsi_opcode opcode,
   const struct ureg_dst *dst,
   unsigned nr_dst,
   const struct ureg_src *src,
@@ -1427,7 +1427,7 @@ ureg_insn(struct ureg_program *ureg,
 
 void
 ureg_tex_insn(struct ureg_program *ureg,
-  unsigned opcode,
+  enum tgsi_opcode opcode,
   const struct ureg_dst *dst,
   unsigned nr_dst,
   enum tgsi_texture_type target,
@@

[Mesa-dev] [PATCH 7/7] tgsi,softpipe: use enum tgsi_opcode

2018-03-22 Thread Brian Paul

---
 src/gallium/auxiliary/tgsi/tgsi_exec.h   | 4 ++--
 src/gallium/drivers/softpipe/sp_buffer.c | 4 ++--
 src/gallium/drivers/softpipe/sp_image.c  | 8 
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h 
b/src/gallium/auxiliary/tgsi/tgsi_exec.h
index ad920dc..0fac7ea 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h
@@ -134,7 +134,7 @@ struct tgsi_image {
 
void (*op)(const struct tgsi_image *image,
   const struct tgsi_image_params *params,
-  unsigned opcode,
+  enum tgsi_opcode opcode,
   const int s[TGSI_QUAD_SIZE],
   const int t[TGSI_QUAD_SIZE],
   const int r[TGSI_QUAD_SIZE],
@@ -167,7 +167,7 @@ struct tgsi_buffer {
 
void (*op)(const struct tgsi_buffer *buffer,
   const struct tgsi_buffer_params *params,
-  unsigned opcode,
+  enum tgsi_opcode opcode,
   const int s[TGSI_QUAD_SIZE],
   float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE],
   float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE]);
diff --git a/src/gallium/drivers/softpipe/sp_buffer.c 
b/src/gallium/drivers/softpipe/sp_buffer.c
index 69a6bd1..e91d2af 100644
--- a/src/gallium/drivers/softpipe/sp_buffer.c
+++ b/src/gallium/drivers/softpipe/sp_buffer.c
@@ -159,7 +159,7 @@ handle_op_uint(const struct pipe_shader_buffer *bview,
bool just_read,
unsigned char *data_ptr,
uint qi,
-   unsigned opcode,
+   enum tgsi_opcode opcode,
unsigned writemask,
float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE],
float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE])
@@ -281,7 +281,7 @@ handle_op_uint(const struct pipe_shader_buffer *bview,
 static void
 sp_tgsi_op(const struct tgsi_buffer *buffer,
const struct tgsi_buffer_params *params,
-   unsigned opcode,
+   enum tgsi_opcode opcode,
const int s[TGSI_QUAD_SIZE],
float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE],
float rgba2[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE])
diff --git a/src/gallium/drivers/softpipe/sp_image.c 
b/src/gallium/drivers/softpipe/sp_image.c
index d5547e2..49b775c 100644
--- a/src/gallium/drivers/softpipe/sp_image.c
+++ b/src/gallium/drivers/softpipe/sp_image.c
@@ -384,7 +384,7 @@ handle_op_uint(const struct pipe_image_view *iview,
char *data_ptr,
uint qi,
unsigned stride,
-   unsigned opcode,
+   enum tgsi_opcode opcode,
int s,
int t,
float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE],
@@ -501,7 +501,7 @@ handle_op_int(const struct pipe_image_view *iview,
   char *data_ptr,
   uint qi,
   unsigned stride,
-  unsigned opcode,
+  enum tgsi_opcode opcode,
   int s,
   int t,
   float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE],
@@ -615,7 +615,7 @@ handle_op_r32f_xchg(const struct pipe_image_view *iview,
 char *data_ptr,
 uint qi,
 unsigned stride,
-unsigned opcode,
+enum tgsi_opcode opcode,
 int s,
 int t,
 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE])
@@ -649,7 +649,7 @@ handle_op_r32f_xchg(const struct pipe_image_view *iview,
 static void
 sp_tgsi_op(const struct tgsi_image *image,
const struct tgsi_image_params *params,
-   unsigned opcode,
+   enum tgsi_opcode opcode,
const int s[TGSI_QUAD_SIZE],
const int t[TGSI_QUAD_SIZE],
const int r[TGSI_QUAD_SIZE],
-- 
2.7.4

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[Mesa-dev] [PATCH 4/7] tgsi: use enum tgsi_opcode

2018-03-22 Thread Brian Paul

---
 src/gallium/auxiliary/tgsi/tgsi_build.c |  2 +-
 src/gallium/auxiliary/tgsi/tgsi_lowering.c  |  6 +++---
 src/gallium/auxiliary/tgsi/tgsi_scan.c  |  6 +++---
 src/gallium/auxiliary/tgsi/tgsi_transform.c |  2 +-
 src/gallium/auxiliary/tgsi/tgsi_transform.h | 12 ++--
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c 
b/src/gallium/auxiliary/tgsi/tgsi_build.c
index 0c4ec8d..36c36d9 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.c
@@ -660,7 +660,7 @@ tgsi_default_instruction( void )
 }
 
 static struct tgsi_instruction
-tgsi_build_instruction(unsigned opcode,
+tgsi_build_instruction(enum tgsi_opcode opcode,
unsigned saturate,
unsigned precise,
unsigned num_dst_regs,
diff --git a/src/gallium/auxiliary/tgsi/tgsi_lowering.c 
b/src/gallium/auxiliary/tgsi/tgsi_lowering.c
index bfc3a6b..47aa3df 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_lowering.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_lowering.c
@@ -823,7 +823,7 @@ transform_dotp(struct tgsi_transform_context *tctx,
struct tgsi_full_src_register *src0 = >Src[0];
struct tgsi_full_src_register *src1 = >Src[1];
struct tgsi_full_instruction new_inst;
-   unsigned opcode = inst->Instruction.Opcode;
+   enum tgsi_opcode opcode = inst->Instruction.Opcode;
 
/* NOTE: any potential last instruction must replicate src on all
 * components (since it could be re-written to write to final dst)
@@ -908,7 +908,7 @@ transform_flr_ceil(struct tgsi_transform_context *tctx,
struct tgsi_full_dst_register *dst  = >Dst[0];
struct tgsi_full_src_register *src0 = >Src[0];
struct tgsi_full_instruction new_inst;
-   unsigned opcode = inst->Instruction.Opcode;
+   enum tgsi_opcode opcode = inst->Instruction.Opcode;
 
if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
   /* FLR: FRC tmpA, src  CEIL: FRC tmpA, -src */
@@ -1038,7 +1038,7 @@ transform_samp(struct tgsi_transform_context *tctx,
/* mask is clamped coords, pmask is all coords (for projection): */
unsigned mask = 0, pmask = 0, smask;
unsigned tex = inst->Texture.Texture;
-   unsigned opcode = inst->Instruction.Opcode;
+   enum tgsi_opcode opcode = inst->Instruction.Opcode;
bool lower_txp = (opcode == TGSI_OPCODE_TXP) &&
   (ctx->config->lower_TXP & (1 << tex));
 
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 4a2b354..18488d7 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -55,7 +55,7 @@ is_memory_file(unsigned file)
 
 
 static bool
-is_mem_query_inst(unsigned opcode)
+is_mem_query_inst(enum tgsi_opcode opcode)
 {
return opcode == TGSI_OPCODE_RESQ ||
   opcode == TGSI_OPCODE_TXQ ||
@@ -68,7 +68,7 @@ is_mem_query_inst(unsigned opcode)
  * texture map?
  */
 static bool
-is_texture_inst(unsigned opcode)
+is_texture_inst(enum tgsi_opcode opcode)
 {
return (!is_mem_query_inst(opcode) &&
tgsi_get_opcode_info(opcode)->is_tex);
@@ -80,7 +80,7 @@ is_texture_inst(unsigned opcode)
  * implicitly?
  */
 static bool
-computes_derivative(unsigned opcode)
+computes_derivative(enum tgsi_opcode opcode)
 {
if (tgsi_get_opcode_info(opcode)->is_tex) {
   return opcode != TGSI_OPCODE_TG4 &&
diff --git a/src/gallium/auxiliary/tgsi/tgsi_transform.c 
b/src/gallium/auxiliary/tgsi/tgsi_transform.c
index a13cf90..cd076c9 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_transform.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_transform.c
@@ -169,7 +169,7 @@ tgsi_transform_shader(const struct tgsi_token *tokens_in,
  {
 struct tgsi_full_instruction *fullinst
= 
-unsigned opcode = fullinst->Instruction.Opcode;
+enum tgsi_opcode opcode = fullinst->Instruction.Opcode;
 
 if (first_instruction && ctx->prolog) {
ctx->prolog(ctx);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_transform.h 
b/src/gallium/auxiliary/tgsi/tgsi_transform.h
index e4da0f5..018e4a0 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_transform.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_transform.h
@@ -267,7 +267,7 @@ tgsi_transform_src_reg(struct tgsi_full_src_register *reg,
  */
 static inline void
 tgsi_transform_op1_inst(struct tgsi_transform_context *ctx,
-unsigned opcode,
+enum tgsi_opcode opcode,
 unsigned dst_file,
 unsigned dst_index,
 unsigned dst_writemask,
@@ -291,7 +291,7 @@ tgsi_transform_op1_inst(struct tgsi_transform_context *ctx,
 
 static inline void
 tgsi_transform_op2_inst(struct tgsi_transform_context *ctx,
-unsigned opcode,
+enum tgsi_opcode opcode,
 unsigned dst_file,
 unsigned

[Mesa-dev] [PATCH 1/7] tgsi: convert opcode macros to enums

2018-03-22 Thread Brian Paul

Enums are nicer in gdb.
---
 src/gallium/include/pipe/p_shader_tokens.h | 548 +++--
 1 file changed, 275 insertions(+), 273 deletions(-)

diff --git a/src/gallium/include/pipe/p_shader_tokens.h 
b/src/gallium/include/pipe/p_shader_tokens.h
index 4e95789..f4e45c2 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -333,284 +333,286 @@ struct tgsi_property_data {
unsigned Data;
 };
 
-/* TGSI opcodes.  
- * 
+/* TGSI opcodes.
+ *
  * For more information on semantics of opcodes and
  * which APIs are known to use which opcodes, see
  * gallium/docs/source/tgsi.rst
  */
-#define TGSI_OPCODE_ARL 0
-#define TGSI_OPCODE_MOV 1
-#define TGSI_OPCODE_LIT 2
-#define TGSI_OPCODE_RCP 3
-#define TGSI_OPCODE_RSQ 4
-#define TGSI_OPCODE_EXP 5
-#define TGSI_OPCODE_LOG 6
-#define TGSI_OPCODE_MUL 7
-#define TGSI_OPCODE_ADD 8
-#define TGSI_OPCODE_DP3 9
-#define TGSI_OPCODE_DP4 10
-#define TGSI_OPCODE_DST 11
-#define TGSI_OPCODE_MIN 12
-#define TGSI_OPCODE_MAX 13
-#define TGSI_OPCODE_SLT 14
-#define TGSI_OPCODE_SGE 15
-#define TGSI_OPCODE_MAD 16
-#define TGSI_OPCODE_TEX_LZ  17
-#define TGSI_OPCODE_LRP 18
-#define TGSI_OPCODE_FMA 19
-#define TGSI_OPCODE_SQRT20
-#define TGSI_OPCODE_LDEXP   21
-#define TGSI_OPCODE_F2U64   22
-#define TGSI_OPCODE_F2I64   23
-#define TGSI_OPCODE_FRC 24
-#define TGSI_OPCODE_TXF_LZ  25
-#define TGSI_OPCODE_FLR 26
-#define TGSI_OPCODE_ROUND   27
-#define TGSI_OPCODE_EX2 28
-#define TGSI_OPCODE_LG2 29
-#define TGSI_OPCODE_POW 30
-/* gap */
-#define TGSI_OPCODE_U2I64   32
-#define TGSI_OPCODE_CLOCK   33
-#define TGSI_OPCODE_I2I64   34
-/* gap */
-#define TGSI_OPCODE_COS 36
-#define TGSI_OPCODE_DDX 37
-#define TGSI_OPCODE_DDY 38
-#define TGSI_OPCODE_KILL39 /* unconditional */
-#define TGSI_OPCODE_PK2H40
-#define TGSI_OPCODE_PK2US   41
-#define TGSI_OPCODE_PK4B42
-#define TGSI_OPCODE_PK4UB   43
-#define TGSI_OPCODE_D2U64   44
-#define TGSI_OPCODE_SEQ 45
-#define TGSI_OPCODE_D2I64   46
-#define TGSI_OPCODE_SGT 47
-#define TGSI_OPCODE_SIN 48
-#define TGSI_OPCODE_SLE 49
-#define TGSI_OPCODE_SNE 50
-#define TGSI_OPCODE_U642D   51
-#define TGSI_OPCODE_TEX 52
-#define TGSI_OPCODE_TXD 53
-#define TGSI_OPCODE_TXP 54
-#define TGSI_OPCODE_UP2H55
-#define TGSI_OPCODE_UP2US   56
-#define TGSI_OPCODE_UP4B57
-#define TGSI_OPCODE_UP4UB   58
-#define TGSI_OPCODE_U642F   59
-#define TGSI_OPCODE_I642F   60
-#define TGSI_OPCODE_ARR 61
-#define TGSI_OPCODE_I642D   62
-#define TGSI_OPCODE_CAL 63
-#define TGSI_OPCODE_RET 64
-#define TGSI_OPCODE_SSG 65 /* SGN */
-#define TGSI_OPCODE_CMP 66
-/* gap */
-#define TGSI_OPCODE_TXB 68
-#define TGSI_OPCODE_FBFETCH 69
-#define TGSI_OPCODE_DIV 70
-#define TGSI_OPCODE_DP2 71
-#define TGSI_OPCODE_TXL 72
-#define TGSI_OPCODE_BRK 73
-#define TGSI_OPCODE_IF  74
-#define TGSI_OPCODE_UIF 75
-#define TGSI_OPCODE_READ_INVOC  76
-#define TGSI_OPCODE_ELSE77
-#define TGSI_OPCODE_ENDIF   78
-
-#define TGSI_OPCODE_DDX_FINE79
-#define TGSI_OPCODE_DDY_FINE80
-/* gap */
-#define TGSI_OPCODE_CEIL83
-#define TGSI_OPCODE_I2F 84
-#define TGSI_OPCODE_NOT 85
-#define TGSI_OPCODE_TRUNC   86
-#define TGSI_OPCODE_SHL 87
-#define TGSI_OPCODE_BALLOT  88
-#define TGSI_OPCODE_AND 89
-#define TGSI_OPCODE_OR  90
-#define TGSI_OPCODE_MOD 91
-#define TGSI_OPCODE_XOR 92
-/* gap */
-#define TGSI_OPCODE_TXF 94
-#define TGSI_OPCODE_TXQ 95
-#define TGSI_OPCODE_CONT96
-#define TGSI_OPCODE_EMIT97
-#define TGSI_OPCODE_ENDPRIM 98
-#define TGSI_OPCODE_BGNLOOP 99
-#define TGSI_OPCODE_BGNSUB  100
-#define TGSI_OPCODE_ENDLOOP 101
-#define TGSI_OPCODE_ENDSUB

[Mesa-dev] [PATCH] x11: Only report supported DRI3/Present versions

2018-03-22 Thread Daniel Stone

The version passed to QueryVersion requests is the version that the
client supports. We were just passing in whatever version of XCB was
present on the system, which may not be a version that Mesa actually
explicitly supports, e.g. it might bring unwanted semantics.

Set specific protocol versions which we support, and only pass those.

Signed-off-by: Daniel Stone 
---
 src/egl/drivers/dri2/platform_x11_dri3.c | 19 +++
 src/glx/dri3_glx.c   | 21 +++--
 2 files changed, 30 insertions(+), 10 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_x11_dri3.c 
b/src/egl/drivers/dri2/platform_x11_dri3.c
index 5e531e21cb0..254c4441ef5 100644
--- a/src/egl/drivers/dri2/platform_x11_dri3.c
+++ b/src/egl/drivers/dri2/platform_x11_dri3.c
@@ -520,6 +520,17 @@ struct dri2_egl_display_vtbl dri3_x11_display_vtbl = {
.close_screen_notify = dri3_close_screen_notify,
 };
 
+/* Only advertise versions of these protocols which we actually support. */
+#define DRI3_SUPPORTED_MAJOR 1
+#define PRESENT_SUPPORTED_MAJOR 1
+#ifdef HAVE_DRI3_MODIFIERS
+#define DRI3_SUPPORTED_MINOR 2
+#define PRESENT_SUPPORTED_MINOR 2
+#else
+#define PRESENT_SUPPORTED_MINOR 0
+#define DRI3_SUPPORTED_MINOR 0
+#endif
+
 EGLBoolean
 dri3_x11_connect(struct dri2_egl_display *dri2_dpy)
 {
@@ -542,12 +553,12 @@ dri3_x11_connect(struct dri2_egl_display *dri2_dpy)
   return EGL_FALSE;
 
dri3_query_cookie = xcb_dri3_query_version(dri2_dpy->conn,
-  XCB_DRI3_MAJOR_VERSION,
-  XCB_DRI3_MINOR_VERSION);
+  DRI3_SUPPORTED_MAJOR,
+  DRI3_SUPPORTED_MINOR);
 
present_query_cookie = xcb_present_query_version(dri2_dpy->conn,
-XCB_PRESENT_MAJOR_VERSION,
-XCB_PRESENT_MINOR_VERSION);
+PRESENT_SUPPORTED_MAJOR,
+PRESENT_SUPPORTED_MINOR);
 
dri3_query =
   xcb_dri3_query_version_reply(dri2_dpy->conn, dri3_query_cookie, );
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index c48a8ba5327..97abbfd9973 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -1026,6 +1026,17 @@ dri3_destroy_display(__GLXDRIdisplay * dpy)
free(dpy);
 }
 
+/* Only advertise versions of these protocols which we actually support. */
+#define DRI3_SUPPORTED_MAJOR 1
+#define PRESENT_SUPPORTED_MAJOR 1
+#ifdef HAVE_DRI3_MODIFIERS
+#define DRI3_SUPPORTED_MINOR 2
+#define PRESENT_SUPPORTED_MINOR 2
+#else
+#define PRESENT_SUPPORTED_MINOR 0
+#define DRI3_SUPPORTED_MINOR 0
+#endif
+
 /** dri3_create_display
  *
  * Allocate, initialize and return a __DRIdisplayPrivate object.
@@ -1057,13 +1068,11 @@ dri3_create_display(Display * dpy)
   return NULL;
 
dri3_cookie = xcb_dri3_query_version(c,
-XCB_DRI3_MAJOR_VERSION,
-XCB_DRI3_MINOR_VERSION);
-
-
+DRI3_SUPPORTED_MAJOR,
+DRI3_SUPPORTED_MINOR);
present_cookie = xcb_present_query_version(c,
-   XCB_PRESENT_MAJOR_VERSION,
-   XCB_PRESENT_MINOR_VERSION);
+  PRESENT_SUPPORTED_MAJOR,
+  PRESENT_SUPPORTED_MINOR);
 
pdp = malloc(sizeof *pdp);
if (pdp == NULL)
-- 
2.16.2

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[Mesa-dev] [PATCH v2 8/8] freedreno: a2xx: Implement DP2 instruction

2018-03-22 Thread Wladimir J. van der Laan

Use DOT2ADDv instruction with 0.0f constant add.

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/freedreno/a2xx/fd2_compiler.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c 
b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
index 52f0aba..ce0b33a 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
@@ -987,6 +987,24 @@ translate_trig(struct fd2_compile_context *ctx,
add_src_reg(ctx, instr, _src);
 }
 
+static void
+translate_dp2(struct fd2_compile_context *ctx,
+   struct tgsi_full_instruction *inst,
+   unsigned opc)
+{
+struct tgsi_src_register tmp_const;
+struct ir2_instruction *instr;
+/* DP2ADD c,a,b -> dot2(a,b) + c */
+/* for c we use the constant 0.0 */
+instr = ir2_instr_create_alu(next_exec_cf(ctx), DOT2ADDv, ~0);
+get_immediate(ctx, _const, fui(0.0f));
+add_dst_reg(ctx, instr, >Dst[0].Register);
+add_src_reg(ctx, instr, _const);
+add_src_reg(ctx, instr, >Src[0].Register);
+add_src_reg(ctx, instr, >Src[1].Register);
+add_vector_clamp(inst, instr);
+}
+
 /*
  * Main part of compiler/translator:
  */
@@ -1054,6 +1072,9 @@ translate_instruction(struct fd2_compile_context *ctx,
instr = ir2_instr_create_alu(cf, ADDv, ~0);
add_regs_vector_2(ctx, inst, instr);
break;
+   case TGSI_OPCODE_DP2:
+   translate_dp2(ctx, inst, opc);
+   break;
case TGSI_OPCODE_DP3:
instr = ir2_instr_create_alu(cf, DOT3v, ~0);
add_regs_vector_2(ctx, inst, instr);
-- 
2.7.4

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[Mesa-dev] [PATCH v2 6/8] freedreno: a2xx: Compressed textures support

2018-03-22 Thread Wladimir J. van der Laan

Add support for:

- PIPE_FORMAT_ETC1_RGB8
- PIPE_FORMAT_DXT1_RGB
- PIPE_FORMAT_DXT1_RGBA
- PIPE_FORMAT_DXT3_RGBA
- PIPE_FORMAT_DXT5_RGBA

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/freedreno/a2xx/fd2_util.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_util.c 
b/src/gallium/drivers/freedreno/a2xx/fd2_util.c
index 25f2bf4..60e5c39 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_util.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_util.c
@@ -183,6 +183,17 @@ fd2_pipe2surface(enum pipe_format format)
case PIPE_FORMAT_R32G32B32A32_FLOAT:
return FMT_32_32_32_32_FLOAT;
 
+/* Compressed textures. */
+case PIPE_FORMAT_ETC1_RGB8:
+return FMT_ETC1_RGB;
+case PIPE_FORMAT_DXT1_RGB:
+case PIPE_FORMAT_DXT1_RGBA:
+return FMT_DXT1;
+case PIPE_FORMAT_DXT3_RGBA:
+return FMT_DXT2_3;
+case PIPE_FORMAT_DXT5_RGBA:
+return FMT_DXT4_5;
+
/* YUV buffers. */
case PIPE_FORMAT_UYVY:
return FMT_Cr_Y1_Cb_Y0;
-- 
2.7.4

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[Mesa-dev] [PATCH v2 2/8] freedreno: a2xx: Change use of BLEND_ to BLEND2_

2018-03-22 Thread Wladimir J. van der Laan

Change use of BLEND_ to BLEND2_,

BLEND_* a3xx_rb_blend_opcode
BLEND2_* is a2xx_rb_blend_opcode

This makes no effective difference as the used enumerant has the same
value (0), but the other enumerants do not match 1-to-1 so this will
avoid future problems.

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/freedreno/a2xx/fd2_gmem.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c 
b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
index 0905ab6..46a7d18 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
@@ -293,10 +293,10 @@ fd2_emit_tile_mem2gmem(struct fd_batch *batch, struct 
fd_tile *tile)
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) |
-   
A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND_DST_PLUS_SRC) |
+   
A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND2_DST_PLUS_SRC) |
A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) |
A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) |
-   
A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND_DST_PLUS_SRC) |
+   
A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND2_DST_PLUS_SRC) |
A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO));
 
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
-- 
2.7.4

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[Mesa-dev] [PATCH v2 5/8] freedreno: a2xx: Support TEXTURE_RECT

2018-03-22 Thread Wladimir J. van der Laan

Denormalized texture coordinates are required for text rendering in
GALLIUM_HUD.

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/freedreno/a2xx/fd2_compiler.c | 3 ++-
 src/gallium/drivers/freedreno/a2xx/ir-a2xx.c  | 1 +
 src/gallium/drivers/freedreno/a2xx/ir-a2xx.h  | 1 +
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c 
b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
index 2ffd8cd..9f2fc61 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
@@ -791,6 +791,7 @@ translate_tex(struct fd2_compile_context *ctx,
instr = ir2_instr_create(next_exec_cf(ctx), IR2_FETCH);
instr->fetch.opc = TEX_FETCH;
instr->fetch.is_cube = (inst->Texture.Texture == TGSI_TEXTURE_3D);
+   instr->fetch.is_rect = (inst->Texture.Texture == TGSI_TEXTURE_RECT);
assert(inst->Texture.NumOffsets <= 1); // TODO what to do in other 
cases?
 
/* save off the tex fetch to be patched later with correct const_idx: */
@@ -802,7 +803,7 @@ translate_tex(struct fd2_compile_context *ctx,
reg = add_src_reg(ctx, instr, coord);
 
/* blob compiler always sets 3rd component to same as 1st for 2d: */
-   if (inst->Texture.Texture == TGSI_TEXTURE_2D)
+   if (inst->Texture.Texture == TGSI_TEXTURE_2D || inst->Texture.Texture 
== TGSI_TEXTURE_RECT)
reg->swizzle[2] = reg->swizzle[0];
 
/* dst register needs to be marked for sync: */
diff --git a/src/gallium/drivers/freedreno/a2xx/ir-a2xx.c 
b/src/gallium/drivers/freedreno/a2xx/ir-a2xx.c
index 163c282..42a9ab4 100644
--- a/src/gallium/drivers/freedreno/a2xx/ir-a2xx.c
+++ b/src/gallium/drivers/freedreno/a2xx/ir-a2xx.c
@@ -341,6 +341,7 @@ static int instr_emit_fetch(struct ir2_instruction *instr,
tex->use_comp_lod = 1;
tex->use_reg_lod = !instr->fetch.is_cube;
tex->sample_location = SAMPLE_CENTER;
+   tex->tx_coord_denorm = instr->fetch.is_rect;
 
if (instr->pred != IR2_PRED_NONE) {
tex->pred_select = 1;
diff --git a/src/gallium/drivers/freedreno/a2xx/ir-a2xx.h 
b/src/gallium/drivers/freedreno/a2xx/ir-a2xx.h
index 36ed204..c4b6c18 100644
--- a/src/gallium/drivers/freedreno/a2xx/ir-a2xx.h
+++ b/src/gallium/drivers/freedreno/a2xx/ir-a2xx.h
@@ -74,6 +74,7 @@ struct ir2_instruction {
unsigned const_idx;
/* texture fetch specific: */
bool is_cube : 1;
+   bool is_rect : 1;
/* vertex fetch specific: */
unsigned const_idx_sel;
enum a2xx_sq_surfaceformat fmt;
-- 
2.7.4

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[Mesa-dev] [PATCH v2 7/8] freedreno: a2xx: implement SEQ/SNE instructions

2018-03-22 Thread Wladimir J. van der Laan

Extend translate_sge_slt to emit these, in analogous fashion
but using CNDEv.

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/freedreno/a2xx/fd2_compiler.c | 23 ---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c 
b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
index 9f2fc61..52f0aba 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
@@ -829,8 +829,10 @@ translate_tex(struct fd2_compile_context *ctx,
 
 /* SGE(a,b) = GTE((b - a), 1.0, 0.0) */
 /* SLT(a,b) = GTE((b - a), 0.0, 1.0) */
+/* SEQ(a,b) = EQU((b - a), 1.0, 0.0) */
+/* SNE(a,b) = EQU((b - a), 0.0, 1.0) */
 static void
-translate_sge_slt(struct fd2_compile_context *ctx,
+translate_sge_slt_seq_sne(struct fd2_compile_context *ctx,
struct tgsi_full_instruction *inst, unsigned opc)
 {
struct ir2_instruction *instr;
@@ -838,6 +840,7 @@ translate_sge_slt(struct fd2_compile_context *ctx,
struct tgsi_src_register tmp_src;
struct tgsi_src_register tmp_const;
float c0, c1;
+instr_vector_opc_t vopc;
 
switch (opc) {
default:
@@ -845,10 +848,22 @@ translate_sge_slt(struct fd2_compile_context *ctx,
case TGSI_OPCODE_SGE:
c0 = 1.0;
c1 = 0.0;
+vopc = CNDGTEv;
break;
case TGSI_OPCODE_SLT:
c0 = 0.0;
c1 = 1.0;
+vopc = CNDGTEv;
+   break;
+   case TGSI_OPCODE_SEQ:
+   c0 = 0.0;
+   c1 = 1.0;
+vopc = CNDEv;
+   break;
+   case TGSI_OPCODE_SNE:
+   c0 = 1.0;
+   c1 = 0.0;
+vopc = CNDEv;
break;
}
 
@@ -859,7 +874,7 @@ translate_sge_slt(struct fd2_compile_context *ctx,
add_src_reg(ctx, instr, >Src[0].Register)->flags |= 
IR2_REG_NEGATE;
add_src_reg(ctx, instr, >Src[1].Register);
 
-   instr = ir2_instr_create_alu(next_exec_cf(ctx), CNDGTEv, ~0);
+   instr = ir2_instr_create_alu(next_exec_cf(ctx), vopc, ~0);
add_dst_reg(ctx, instr, >Dst[0].Register);
/* maybe should re-arrange the syntax some day, but
 * in assembler/disassembler and what ir.c expects
@@ -1057,7 +1072,9 @@ translate_instruction(struct fd2_compile_context *ctx,
break;
case TGSI_OPCODE_SLT:
case TGSI_OPCODE_SGE:
-   translate_sge_slt(ctx, inst, opc);
+case TGSI_OPCODE_SEQ:
+case TGSI_OPCODE_SNE:
+   translate_sge_slt_seq_sne(ctx, inst, opc);
break;
case TGSI_OPCODE_MAD:
instr = ir2_instr_create_alu(cf, MULADDv, ~0);
-- 
2.7.4

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[Mesa-dev] [PATCH v2 1/8] freedreno: a2xx: Update rnndb header for formats enumeration

2018-03-22 Thread Wladimir J. van der Laan

The format enumeration comes comes from the yamoto
register headers that are part of the amd-gpu kernel driver.
(see freedreno envytools commit 1b32c444f82cd7144d71602106462f59f146c1d0)

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/freedreno/a2xx/a2xx.xml.h | 33 +++
 1 file changed, 13 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h 
b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
index 55a4355..279a652 100644
--- a/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
+++ b/src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
@@ -84,13 +84,12 @@ enum a2xx_sq_surfaceformat {
FMT_5_5_5_1 = 13,
FMT_8_8_8_8_A = 14,
FMT_4_4_4_4 = 15,
-   FMT_10_11_11 = 16,
-   FMT_11_11_10 = 17,
+   FMT_8_8_8 = 16,
FMT_DXT1 = 18,
FMT_DXT2_3 = 19,
FMT_DXT4_5 = 20,
+   FMT_10_10_10_2 = 21,
FMT_24_8 = 22,
-   FMT_24_8_FLOAT = 23,
FMT_16 = 24,
FMT_16_16 = 25,
FMT_16_16_16_16 = 26,
@@ -106,29 +105,23 @@ enum a2xx_sq_surfaceformat {
FMT_32_FLOAT = 36,
FMT_32_32_FLOAT = 37,
FMT_32_32_32_32_FLOAT = 38,
-   FMT_32_AS_8 = 39,
-   FMT_32_AS_8_8 = 40,
-   FMT_16_MPEG = 41,
-   FMT_16_16_MPEG = 42,
-   FMT_8_INTERLACED = 43,
-   FMT_32_AS_8_INTERLACED = 44,
-   FMT_32_AS_8_8_INTERLACED = 45,
-   FMT_16_INTERLACED = 46,
-   FMT_16_MPEG_INTERLACED = 47,
-   FMT_16_16_MPEG_INTERLACED = 48,
+   FMT_ATI_TC_RGB = 39,
+   FMT_ATI_TC_RGBA = 40,
+   FMT_ATI_TC_555_565_RGB = 41,
+   FMT_ATI_TC_555_565_RGBA = 42,
+   FMT_ATI_TC_RGBA_INTERP = 43,
+   FMT_ATI_TC_555_565_RGBA_INTERP = 44,
+   FMT_ETC1_RGBA_INTERP = 46,
+   FMT_ETC1_RGB = 47,
+   FMT_ETC1_RGBA = 48,
FMT_DXN = 49,
-   FMT_8_8_8_8_AS_16_16_16_16 = 50,
-   FMT_DXT1_AS_16_16_16_16 = 51,
-   FMT_DXT2_3_AS_16_16_16_16 = 52,
-   FMT_DXT4_5_AS_16_16_16_16 = 53,
+   FMT_2_3_3 = 51,
FMT_2_10_10_10_AS_16_16_16_16 = 54,
-   FMT_10_11_11_AS_16_16_16_16 = 55,
-   FMT_11_11_10_AS_16_16_16_16 = 56,
+   FMT_10_10_10_2_AS_16_16_16_16 = 55,
FMT_32_32_32_FLOAT = 57,
FMT_DXT3A = 58,
FMT_DXT5A = 59,
FMT_CTX1 = 60,
-   FMT_DXT3A_AS_1_1_1_1 = 61,
 };
 
 enum a2xx_sq_ps_vtx_mode {
-- 
2.7.4

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[Mesa-dev] [PATCH v2 4/8] freedreno: a2xx: Prevent crash in emit_texture if view is not set

2018-03-22 Thread Wladimir J. van der Laan

Textures will sometimes be updated if texture view state was
un-set, without this change that causes an assertion crash or
segfault.

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/freedreno/a2xx/fd2_emit.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c 
b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
index 5a1db13..a787b71 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_emit.c
@@ -125,8 +125,9 @@ emit_texture(struct fd_ringbuffer *ring, struct fd_context 
*ctx,
 {
unsigned const_idx = fd2_get_const_idx(ctx, tex, samp_id);
static const struct fd2_sampler_stateobj dummy_sampler = {};
+   static const struct fd2_pipe_sampler_view dummy_view = {};
const struct fd2_sampler_stateobj *sampler;
-   struct fd2_pipe_sampler_view *view;
+   const struct fd2_pipe_sampler_view *view;
 
if (emitted & (1 << const_idx))
return 0;
@@ -134,13 +135,19 @@ emit_texture(struct fd_ringbuffer *ring, struct 
fd_context *ctx,
sampler = tex->samplers[samp_id] ?
fd2_sampler_stateobj(tex->samplers[samp_id]) :
_sampler;
-   view = fd2_pipe_sampler_view(tex->textures[samp_id]);
+   view = tex->textures[samp_id] ?
+   fd2_pipe_sampler_view(tex->textures[samp_id]) :
+   _view;
 
OUT_PKT3(ring, CP_SET_CONSTANT, 7);
OUT_RING(ring, 0x0001 + (0x6 * const_idx));
 
OUT_RING(ring, sampler->tex0 | view->tex0);
-   OUT_RELOC(ring, fd_resource(view->base.texture)->bo, 0, view->fmt, 0);
+   if (view->base.texture)
+   OUT_RELOC(ring, fd_resource(view->base.texture)->bo, 0, 
view->fmt, 0);
+   else
+   OUT_RING(ring, 0);
+
OUT_RING(ring, view->tex2);
OUT_RING(ring, sampler->tex3 | view->tex3);
OUT_RING(ring, sampler->tex4);
-- 
2.7.4

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[Mesa-dev] [PATCH v2 0/8] freedreno: a2xx improvements

2018-03-22 Thread Wladimir J. van der Laan

While working on a205 support for i.MX51/53, I've also written some patches
that are not specific to a20x but should apply to the whole a2xx range.

As I'm figuring out how to handle backward compatibility to other a2xx, I
think it makes sense to send these upstream already to reduce the patch stack.

Changes since first post:

- Split up rnndb patch into a patch that changes formate numeration
  and one that changed BLEND->BLEND2.
- fd2_emit emit_texture const correctness.

I checked that there is no Gallium capability to be set for TEXTURE_RECT.

Wladimir J. van der Laan (8):
  freedreno: a2xx: Update rnndb header for formats enumeration
  freedreno: a2xx: Change use of BLEND_ to BLEND2_
  freedreno: a2xx: Fix fd2_tex_swiz
  freedreno: a2xx: Prevent crash in emit_texture if view is not set
  freedreno: a2xx: Support TEXTURE_RECT
  freedreno: a2xx: Compressed textures support
  freedreno: a2xx: implement SEQ/SNE instructions
  freedreno: a2xx: Implement DP2 instruction

 src/gallium/drivers/freedreno/a2xx/a2xx.xml.h | 33 +++-
 src/gallium/drivers/freedreno/a2xx/fd2_compiler.c | 47 +--
 src/gallium/drivers/freedreno/a2xx/fd2_emit.c | 13 +--
 src/gallium/drivers/freedreno/a2xx/fd2_gmem.c |  4 +-
 src/gallium/drivers/freedreno/a2xx/fd2_util.c | 29 +-
 src/gallium/drivers/freedreno/a2xx/ir-a2xx.c  |  1 +
 src/gallium/drivers/freedreno/a2xx/ir-a2xx.h  |  1 +
 7 files changed, 90 insertions(+), 38 deletions(-)

-- 
2.7.4

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[Mesa-dev] [PATCH v2 3/8] freedreno: a2xx: Fix fd2_tex_swiz

2018-03-22 Thread Wladimir J. van der Laan

Compose swizzles using util_format_compose_swizzles instead
of the custom code (which somehow had a bug).

This makes the GL_ALPHA internal format work.

Signed-off-by: Wladimir J. van der Laan 
---
 src/gallium/drivers/freedreno/a2xx/fd2_util.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_util.c 
b/src/gallium/drivers/freedreno/a2xx/fd2_util.c
index 0bdcfcd..25f2bf4 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_util.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_util.c
@@ -309,14 +309,14 @@ fd2_tex_swiz(enum pipe_format format, unsigned swizzle_r, 
unsigned swizzle_g,
 {
const struct util_format_description *desc =
util_format_description(format);
-   uint8_t swiz[] = {
-   swizzle_r, swizzle_g, swizzle_b, swizzle_a,
-   PIPE_SWIZZLE_0, PIPE_SWIZZLE_1,
-   PIPE_SWIZZLE_1, PIPE_SWIZZLE_1,
-   };
+   unsigned char swiz[4] = {
+   swizzle_r, swizzle_g, swizzle_b, swizzle_a,
+   }, rswiz[4];
 
-   return A2XX_SQ_TEX_3_SWIZ_X(tex_swiz(swiz[desc->swizzle[0]])) |
-   A2XX_SQ_TEX_3_SWIZ_Y(tex_swiz(swiz[desc->swizzle[1]])) |
-   A2XX_SQ_TEX_3_SWIZ_Z(tex_swiz(swiz[desc->swizzle[2]])) |
-   A2XX_SQ_TEX_3_SWIZ_W(tex_swiz(swiz[desc->swizzle[3]]));
+   util_format_compose_swizzles(desc->swizzle, swiz, rswiz);
+
+   return A2XX_SQ_TEX_3_SWIZ_X(tex_swiz(rswiz[0])) |
+   A2XX_SQ_TEX_3_SWIZ_Y(tex_swiz(rswiz[1])) |
+   A2XX_SQ_TEX_3_SWIZ_Z(tex_swiz(rswiz[2])) |
+   A2XX_SQ_TEX_3_SWIZ_W(tex_swiz(rswiz[3]));
 }
-- 
2.7.4

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[Mesa-dev] [PATCH] st/mesa: silence unhandled switch case warning

2018-03-22 Thread Brian Paul

And improve the unreachable() error message.
---
 src/mesa/state_tracker/st_glsl_types.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_types.cpp 
b/src/mesa/state_tracker/st_glsl_types.cpp
index ef7b7fa..baba2d4 100644
--- a/src/mesa/state_tracker/st_glsl_types.cpp
+++ b/src/mesa/state_tracker/st_glsl_types.cpp
@@ -146,7 +146,8 @@ st_glsl_type_dword_size(const struct glsl_type *type)
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
case GLSL_TYPE_FUNCTION:
-  unreachable("not reached");
+   default:
+  unreachable("invalid type in st_glsl_type_dword_size()");
}
 
return 0;
-- 
2.7.4

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[Mesa-dev] [PATCH] egl/wayland: Make swrast display_sync the correct queue

2018-03-22 Thread Derek Foreman

commit 03dd9a88b0be17ff0ce91e92f6902a9a85ba584a introduced per surface
queues, but the display_sync for swrast_commit_backbuffer remained on
the old queue.  This is likely to break when dispatching the correct
queue at the top of function (which can't dispatch the sync callback
we're waiting for).

The easiest known reproduction case is running weston-subsurfaces under
weston --use-pixman

Signed-off-by: Derek Foreman 
---
 src/egl/drivers/dri2/platform_wayland.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 94f7defa65..80853ac00b 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -1751,7 +1751,7 @@ dri2_wl_swrast_commit_backbuffer(struct dri2_egl_surface 
*dri2_surf)
 * handle the commit and send a release event before checking for a free
 * buffer */
if (dri2_surf->throttle_callback == NULL) {
-  dri2_surf->throttle_callback = wl_display_sync(dri2_dpy->wl_dpy_wrapper);
+  dri2_surf->throttle_callback = 
wl_display_sync(dri2_surf->wl_dpy_wrapper);
   wl_callback_add_listener(dri2_surf->throttle_callback,
_listener, dri2_surf);
}
-- 
2.14.3

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[Mesa-dev] [PATCH 1/2] amd/addrlib: update to the latest version for Vega12

2018-03-22 Thread Marek Olšák

From: Marek Olšák 

Reviewed-by: Alex Deucher 
---
 src/amd/addrlib/addrinterface.cpp|  32 -
 src/amd/addrlib/addrinterface.h  |  62 ++
 src/amd/addrlib/addrtypes.h  |   6 +-
 src/amd/addrlib/amdgpu_asic_addr.h   |   3 +
 src/amd/addrlib/core/addrlib.cpp |  80 +++--
 src/amd/addrlib/core/addrlib.h   |  36 +-
 src/amd/addrlib/core/addrlib1.cpp|  14 ++-
 src/amd/addrlib/core/addrlib2.cpp|  10 ++
 src/amd/addrlib/core/addrlib2.h  |   6 -
 src/amd/addrlib/gfx9/gfx9addrlib.cpp | 224 +--
 src/amd/addrlib/gfx9/gfx9addrlib.h   |  21 ++--
 src/amd/addrlib/r800/ciaddrlib.cpp   |  40 +--
 src/amd/addrlib/r800/ciaddrlib.h |   4 +-
 src/amd/addrlib/r800/egbaddrlib.cpp  |   8 +-
 src/amd/addrlib/r800/siaddrlib.cpp   |  35 --
 src/amd/addrlib/r800/siaddrlib.h |   4 +-
 src/amd/common/ac_surface.c  |   2 +-
 17 files changed, 439 insertions(+), 148 deletions(-)

diff --git a/src/amd/addrlib/addrinterface.cpp 
b/src/amd/addrlib/addrinterface.cpp
index 5fdf7fc3c65..112431e2cb4 100644
--- a/src/amd/addrlib/addrinterface.cpp
+++ b/src/amd/addrlib/addrinterface.cpp
@@ -1047,38 +1047,68 @@ ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
 *
 *   @brief
 *   Convert maximum alignments
 *
 *   @return
 *   ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
 

 */
 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
 ADDR_HANDLE hLib, ///< address lib handle
-ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) ///< [out] output structure
+ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
 {
 Addr::Lib* pLib = Lib::GetLib(hLib);
 
 ADDR_E_RETURNCODE returnCode = ADDR_OK;
 
 if (pLib != NULL)
 {
 returnCode = pLib->GetMaxAlignments(pOut);
 }
 else
 {
 returnCode = ADDR_ERROR;
 }
 
 return returnCode;
 }
 
+/**
+
+*   AddrGetMaxMetaAlignments
+*
+*   @brief
+*   Convert maximum alignments for metadata
+*
+*   @return
+*   ADDR_OK if successful, otherwise an error code of ADDR_E_RETURNCODE
+
+*/
+ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
+ADDR_HANDLE hLib, ///< address lib handle
+ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) ///< [out] output structure
+{
+Addr::Lib* pLib = Lib::GetLib(hLib);
+
+ADDR_E_RETURNCODE returnCode = ADDR_OK;
+
+if (pLib != NULL)
+{
+returnCode = pLib->GetMaxMetaAlignments(pOut);
+}
+else
+{
+returnCode = ADDR_ERROR;
+}
+
+return returnCode;
+}
 
 
 

 //Surface functions for Addr2
 

 
 /**
 

 *   Addr2ComputeSurfaceInfo
 *
diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index 8124b745f21..be9e5c2b81e 100644
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -521,21 +521,22 @@ typedef union _ADDR_SURFACE_FLAGS
 UINT_32 needEquation : 1; ///< Make the surface tile setting 
equation compatible.
   ///  This flag indicates we need to 
override tile
   ///  mode to PRT_* tile mode to 
disable slice rotation,
   ///  which is needed by swizzle 
pattern equation.
 UINT_32 skipIndicesOutput: 1; ///< Skipping indices in output.
 UINT_32 rotateDisplay: 1; ///< Rotate micro tile type
 UINT_32 minimizeAlignment: 1; ///< Minimize alignment
 UINT_32 preferEquation   : 1; ///< Return equation index without 
adjusting tile mode
 UINT_32 matchStencilTileCfg  : 1; ///< Select tile index of stencil as 
well as depth surface
   ///  to make sure they share same 
tile config parameters
-UINT_32 reserved : 2; ///< Reserved bits
+UINT_32 disallowLargeThickDegrade   : 1;///< Disallow large thick 
tile degrade
+UINT_32 reserved : 1; ///< Reserved bits
 };
 
 UINT_32 value;
 } ADDR_SURFACE_FLAGS;
 
 /**
 

 *   ADDR_COMPUTE_SURFACE_INFO_INPUT
 *
 *   @brief
@@ -2266,21 +2267,21 @@ typedef struct

[Mesa-dev] [PATCH 2/2] radeonsi: add support for Vega12

2018-03-22 Thread Marek Olšák

From: Marek Olšák 

Reviewed-by: Alex Deucher 
---
 include/pci_ids/radeonsi_pci_ids.h  |  6 +
 src/amd/common/ac_llvm_util.c   |  1 +
 src/amd/common/ac_surface.c | 33 +++--
 src/amd/common/amd_family.h |  1 +
 src/gallium/drivers/radeonsi/si_get.c   |  1 +
 src/gallium/drivers/radeonsi/si_pipe.c  |  2 ++
 src/gallium/drivers/radeonsi/si_state.c |  4 ++-
 src/gallium/drivers/radeonsi/si_state_binning.c |  1 +
 8 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/include/pci_ids/radeonsi_pci_ids.h 
b/include/pci_ids/radeonsi_pci_ids.h
index 6a3594eabc9..62b130307a3 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -219,11 +219,17 @@ CHIPSET(0x699F, POLARIS12)
 CHIPSET(0x6860, VEGA10)
 CHIPSET(0x6861, VEGA10)
 CHIPSET(0x6862, VEGA10)
 CHIPSET(0x6863, VEGA10)
 CHIPSET(0x6864, VEGA10)
 CHIPSET(0x6867, VEGA10)
 CHIPSET(0x6868, VEGA10)
 CHIPSET(0x687F, VEGA10)
 CHIPSET(0x686C, VEGA10)
 
+CHIPSET(0x69A0, VEGA12)
+CHIPSET(0x69A1, VEGA12)
+CHIPSET(0x69A2, VEGA12)
+CHIPSET(0x69A3, VEGA12)
+CHIPSET(0x69AF, VEGA12)
+
 CHIPSET(0x15DD, RAVEN)
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index bb9e873af81..f3db1c5a4a4 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -107,20 +107,21 @@ const char *ac_get_llvm_processor_name(enum radeon_family 
family)
case CHIP_FIJI:
return "fiji";
case CHIP_STONEY:
return "stoney";
case CHIP_POLARIS10:
return "polaris10";
case CHIP_POLARIS11:
case CHIP_POLARIS12:
return "polaris11";
case CHIP_VEGA10:
+   case CHIP_VEGA12:
case CHIP_RAVEN:
return "gfx900";
default:
return "";
}
 }
 
 LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum 
ac_target_machine_options tm_options)
 {
assert(family >= CHIP_TAHITI);
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 603b7058bdc..12dfc0cb1f2 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -128,20 +128,24 @@ static void addrlib_family_rev_id(enum radeon_family 
family,
*addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
break;
case CHIP_POLARIS12:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
break;
case CHIP_VEGA10:
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
break;
+   case CHIP_VEGA12:
+   *addrlib_family = FAMILY_AI;
+   *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
+   break;
case CHIP_RAVEN:
*addrlib_family = FAMILY_RV;
*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
break;
default:
fprintf(stderr, "amdgpu: Unknown family.\n");
}
 }
 
 static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
@@ -898,22 +902,22 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
if (in->flags.depth) {
assert(in->swizzleMode != ADDR_SW_LINEAR);
 
/* HTILE */
ADDR2_COMPUTE_HTILE_INFO_INPUT hin = {0};
ADDR2_COMPUTE_HTILE_INFO_OUTPUT hout = {0};
 
hin.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_INPUT);
hout.size = sizeof(ADDR2_COMPUTE_HTILE_INFO_OUTPUT);
 
-   hin.hTileFlags.pipeAligned = 1;
-   hin.hTileFlags.rbAligned = 1;
+   hin.hTileFlags.pipeAligned = !in->flags.metaPipeUnaligned;
+   hin.hTileFlags.rbAligned = !in->flags.metaRbUnaligned;
hin.depthFlags = in->flags;
hin.swizzleMode = in->swizzleMode;
hin.unalignedWidth = in->width;
hin.unalignedHeight = in->height;
hin.numSlices = in->numSlices;
hin.numMipLevels = in->numMipLevels;
 
ret = Addr2ComputeHtileInfo(addrlib, , );
if (ret != ADDR_OK)
return ret;
@@ -960,22 +964,22 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
!compressed &&
in->swizzleMode != ADDR_SW_LINEAR) {
ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
ADDR2_META_MIP_INFO 
meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
 
din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
dout.pMipInfo =

[Mesa-dev] [PATCH 5/5] ac/gpu_info: print GB_ADDR_CONFIG

2018-03-22 Thread Marek Olšák

From: Marek Olšák 

---
 src/amd/common/ac_gpu_info.c | 50 
 src/amd/common/ac_gpu_info.h |  1 +
 2 files changed, 51 insertions(+)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 9fe1a318723..bd7bc50dafb 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -315,20 +315,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->has_ctx_priority = info->drm_minor >= 22;
/* TODO: Enable this once the kernel handles it efficiently. */
/*info->has_local_buffers = ws->info.drm_minor >= 20;*/
info->num_render_backends = amdinfo->rb_pipes;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
if (!info->clock_crystal_freq) {
fprintf(stderr, "amdgpu: clock crystal frequency is 0, 
timestamps will be wrong\n");
info->clock_crystal_freq = 1;
}
info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
+   info->gb_addr_config = amdinfo->gb_addr_cfg;
if (info->chip_class == GFX9) {
info->num_tile_pipes = 1 << 
G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
info->pipe_interleave_bytes =
256 << 
G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
} else {
info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
info->pipe_interleave_bytes =
256 << 
G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
}
info->r600_has_virtual_memory = true;
@@ -462,11 +463,60 @@ void ac_print_gpu_info(struct radeon_info *info)
printf("num_good_compute_units = %i\n", 
info->num_good_compute_units);
printf("max_se = %i\n", info->max_se);
printf("max_sh_per_se = %i\n", info->max_sh_per_se);
 
printf("Render backend info:\n");
printf("num_render_backends = %i\n", info->num_render_backends);
printf("num_tile_pipes = %i\n", info->num_tile_pipes);
printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
printf("max_alignment = %u\n", (unsigned)info->max_alignment);
+
+   printf("GB_ADDR_CONFIG:\n");
+   if (info->chip_class >= GFX9) {
+   printf("num_pipes = %u\n",
+  1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
+   printf("pipe_interleave_size = %u\n",
+  256 << 
G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
+   printf("max_compressed_frags = %u\n",
+  1 << 
G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
+   printf("bank_interleave_size = %u\n",
+  1 << 
G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
+   printf("num_banks = %u\n",
+  1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
+   printf("shader_engine_tile_size = %u\n",
+  16 << 
G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
+   printf("num_shader_engines = %u\n",
+  1 << 
G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
+   printf("num_gpus = %u (raw)\n",
+  G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
+   printf("multi_gpu_tile_size = %u (raw)\n",
+  G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
+   printf("num_rb_per_se = %u\n",
+  1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
+   printf("row_size = %u\n",
+  1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
+   printf("num_lower_pipes = %u (raw)\n",
+  G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
+   printf("se_enable = %u (raw)\n",
+  G_0098F8_SE_ENABLE(info->gb_addr_config));
+   } else {
+   printf("num_pipes = %u\n",
+  1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
+   printf("pipe_interleave_size = %u\n",
+  256 << 
G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
+   printf("bank_interleave_size = %u\n",
+  1 << 
G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
+   printf("num_shader_engines = %u\n",
+  1 << 
G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
+   printf("shader_engine_tile_size = %u\n",
+  16 << 
G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
+   printf("num_gpus = %u (raw)\n",
+  G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
+   printf("multi_gpu_tile_size = %u

[Mesa-dev] [PATCH 1/5] winsys/amdgpu: always allow GTT placements on APUs

2018-03-22 Thread Marek Olšák

From: Marek Olšák 

---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 7740b46b7b9..22b5a73143d 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -402,28 +402,26 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
   heap);
}
request.alloc_size = size;
request.phys_alignment = alignment;
 
if (initial_domain & RADEON_DOMAIN_VRAM)
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
if (initial_domain & RADEON_DOMAIN_GTT)
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
 
-   /* If VRAM is just stolen system memory, allow both VRAM and
-* GTT, whichever has free space. If a buffer is evicted from
-* VRAM to GTT, it will stay there.
-*
-* DRM 3.6.0 has good BO move throttling, so we can allow VRAM-only
-* placements even with a low amount of stolen VRAM.
+   /* Since VRAM and GTT have almost the same performance on APUs, we could
+* just set GTT. However, in order to decrease GTT(RAM) usage, which is
+* shared with the OS, allow VRAM placements too. The idea is not to use
+* VRAM usefully, but to use it so that it's not unused and wasted.
 */
-   if (!ws->info.has_dedicated_vram && ws->info.drm_minor < 6)
+   if (!ws->info.has_dedicated_vram)
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
 
if (flags & RADEON_FLAG_NO_CPU_ACCESS)
   request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
if (flags & RADEON_FLAG_GTT_WC)
   request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
if (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
ws->info.has_local_buffers)
   request.flags |= AMDGPU_GEM_CREATE_VM_ALWAYS_VALID;
 
-- 
2.15.1

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[Mesa-dev] [PATCH 4/5] ac/gpu_info: reorder the fields and print them nicely

2018-03-22 Thread Marek Olšák

From: Marek Olšák 

---
 src/amd/common/ac_gpu_info.c | 107 ---
 src/amd/common/ac_gpu_info.h |  24 ++
 2 files changed, 76 insertions(+), 55 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 8f01038a3a0..9fe1a318723 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -397,61 +397,76 @@ void ac_compute_device_uuid(struct radeon_info *info, 
char *uuid, size_t size)
 * */
memset(uuid, 0, size);
uint_uuid[0] = info->pci_domain;
uint_uuid[1] = info->pci_bus;
uint_uuid[2] = info->pci_dev;
uint_uuid[3] = info->pci_func;
 }
 
 void ac_print_gpu_info(struct radeon_info *info)
 {
-   printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
+   printf("Device info:\n");
+   printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
   info->pci_domain, info->pci_bus,
   info->pci_dev, info->pci_func);
-   printf("pci_id = 0x%x\n", info->pci_id);
-   printf("family = %i\n", info->family);
-   printf("chip_class = %i\n", info->chip_class);
-   printf("pte_fragment_size = %u\n", info->pte_fragment_size);
-   printf("gart_page_size = %u\n", info->gart_page_size);
-   printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 
1024*1024));
-   printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 
1024*1024));
-   printf("vram_vis_size = %i MB\n", 
(int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
-   printf("gds_size = %u kB\n", info->gds_size / 1024);
-   printf("gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size 
/ 1024);
-   printf("max_alloc_size = %i MB\n",
+   printf("pci_id = 0x%x\n", info->pci_id);
+   printf("family = %i\n", info->family);
+   printf("chip_class = %i\n", info->chip_class);
+   printf("num_compute_rings = %u\n", info->num_compute_rings);
+   printf("num_sdma_rings = %i\n", info->num_sdma_rings);
+   printf("clock_crystal_freq = %i\n", info->clock_crystal_freq);
+   printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
+
+   printf("Memory info:\n");
+   printf("pte_fragment_size = %u\n", info->pte_fragment_size);
+   printf("gart_page_size = %u\n", info->gart_page_size);
+   printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 
1024*1024));
+   printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 
1024*1024));
+   printf("vram_vis_size = %i MB\n", 
(int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
+   printf("gds_size = %u kB\n", info->gds_size / 1024);
+   printf("gds_gfx_partition_size = %u kB\n", 
info->gds_gfx_partition_size / 1024);
+   printf("max_alloc_size = %i MB\n",
   (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
-   printf("min_alloc_size = %u\n", info->min_alloc_size);
-   printf("address32_hi = %u\n", info->address32_hi);
-   printf("has_dedicated_vram = %u\n", info->has_dedicated_vram);
-   printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
-   printf("has_hw_decode = %u\n", info->has_hw_decode);
-   printf("ib_start_alignment = %u\n", info->ib_start_alignment);
-   printf("num_sdma_rings = %i\n", info->num_sdma_rings);
-   printf("num_compute_rings = %u\n", info->num_compute_rings);
-   printf("uvd_fw_version = %u\n", info->uvd_fw_version);
-   printf("vce_fw_version = %u\n", info->vce_fw_version);
-   printf("me_fw_version = %i\n", info->me_fw_version);
-   printf("me_fw_feature = %i\n", info->me_fw_feature);
-   printf("pfp_fw_version = %i\n", info->pfp_fw_version);
-   printf("pfp_fw_feature = %i\n", info->pfp_fw_feature);
-   printf("ce_fw_version = %i\n", info->ce_fw_version);
-   printf("ce_fw_feature = %i\n", info->ce_fw_feature);
-   printf("vce_harvest_config = %i\n", info->vce_harvest_config);
-   printf("clock_crystal_freq = %i\n", info->clock_crystal_freq);
-   printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
-   printf("drm = %i.%i.%i\n", info->drm_major,
+   printf("min_alloc_size = %u\n", info->min_alloc_size);
+   printf("address32_hi = %u\n", info->address32_hi);
+   printf("has_dedicated_vram = %u\n", info->has_dedicated_vram);
+
+   printf("CP info:\n");
+   printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
+   printf("ib_start_alignment = %u\n", info->ib_start_alignment);
+   printf("me_fw_version = %i\n", info->me_fw_version);
+   printf("me_fw_feature = %i\n", info->me_fw_feature);
+   printf("pfp_fw_version = %i\n", info->pfp_fw_version);
+   printf("pfp_fw_feature = %i\n", info->pfp_fw_feature);
+   printf("ce_fw_version = %i\n", info->ce_fw_version);
+   printf("

[Mesa-dev] [PATCH 2/5] ac/gpu_info: don't print irrelevant fields

2018-03-22 Thread Marek Olšák

From: Marek Olšák 

---
 src/amd/common/ac_gpu_info.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 73fc36203c1..ca556a8b11f 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -415,21 +415,20 @@ void ac_print_gpu_info(struct radeon_info *info)
printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 
1024*1024));
printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 
1024*1024));
printf("vram_vis_size = %i MB\n", 
(int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
printf("gds_size = %u kB\n", info->gds_size / 1024);
printf("gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size 
/ 1024);
printf("max_alloc_size = %i MB\n",
   (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
printf("min_alloc_size = %u\n", info->min_alloc_size);
printf("address32_hi = %u\n", info->address32_hi);
printf("has_dedicated_vram = %u\n", info->has_dedicated_vram);
-   printf("has_virtual_memory = %i\n", info->has_virtual_memory);
printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
printf("has_hw_decode = %u\n", info->has_hw_decode);
printf("ib_start_alignment = %u\n", info->ib_start_alignment);
printf("num_sdma_rings = %i\n", info->num_sdma_rings);
printf("num_compute_rings = %u\n", info->num_compute_rings);
printf("uvd_fw_version = %u\n", info->uvd_fw_version);
printf("vce_fw_version = %u\n", info->vce_fw_version);
printf("me_fw_version = %i\n", info->me_fw_version);
printf("me_fw_feature = %i\n", info->me_fw_feature);
printf("pfp_fw_version = %i\n", info->pfp_fw_version);
@@ -438,25 +437,21 @@ void ac_print_gpu_info(struct radeon_info *info)
printf("ce_fw_feature = %i\n", info->ce_fw_feature);
printf("vce_harvest_config = %i\n", info->vce_harvest_config);
printf("clock_crystal_freq = %i\n", info->clock_crystal_freq);
printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
printf("drm = %i.%i.%i\n", info->drm_major,
   info->drm_minor, info->drm_patchlevel);
printf("has_userptr = %i\n", info->has_userptr);
printf("has_syncobj = %u\n", info->has_syncobj);
printf("has_fence_to_handle = %u\n", info->has_fence_to_handle);
 
-   printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes);
printf("max_shader_clock = %i\n", info->max_shader_clock);
printf("num_good_compute_units = %i\n", info->num_good_compute_units);
printf("max_se = %i\n", info->max_se);
printf("max_sh_per_se = %i\n", info->max_sh_per_se);
 
-   printf("r600_gb_backend_map = %i\n", info->r600_gb_backend_map);
-   printf("r600_gb_backend_map_valid = %i\n", 
info->r600_gb_backend_map_valid);
-   printf("r600_num_banks = %i\n", info->r600_num_banks);
printf("num_render_backends = %i\n", info->num_render_backends);
printf("num_tile_pipes = %i\n", info->num_tile_pipes);
printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
printf("max_alignment = %u\n", (unsigned)info->max_alignment);
 }
-- 
2.15.1

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[Mesa-dev] [PATCH 3/5] ac/gpu_info: rename has_virtual_memory -> r600_has_virtual_memory

2018-03-22 Thread Marek Olšák

From: Marek Olšák 

---
 src/amd/common/ac_gpu_info.c  |  2 +-
 src/amd/common/ac_gpu_info.h  |  2 +-
 src/gallium/drivers/r600/r600_buffer_common.c |  4 ++--
 src/gallium/drivers/r600/r600_cs.h|  2 +-
 src/gallium/drivers/r600/r600_pipe_common.c   |  6 +++---
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 12 ++--
 src/gallium/winsys/radeon/drm/radeon_drm_cs.c |  6 +++---
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 16 
 8 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index ca556a8b11f..8f01038a3a0 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -324,21 +324,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
if (info->chip_class == GFX9) {
info->num_tile_pipes = 1 << 
G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
info->pipe_interleave_bytes =
256 << 
G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
} else {
info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
info->pipe_interleave_bytes =
256 << 
G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
}
-   info->has_virtual_memory = true;
+   info->r600_has_virtual_memory = true;
 
assert(util_is_power_of_two(dma.available_rings + 1));
assert(util_is_power_of_two(compute.available_rings + 1));
 
info->num_sdma_rings = util_bitcount(dma.available_rings);
info->num_compute_rings = util_bitcount(compute.available_rings);
 
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 3f08b577c4b..22ac015c23a 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -54,21 +54,21 @@ struct radeon_info {
uint32_tgart_page_size;
uint64_tgart_size;
uint64_tvram_size;
uint64_tvram_vis_size;
unsignedgds_size;
unsignedgds_gfx_partition_size;
uint64_tmax_alloc_size;
uint32_tmin_alloc_size;
uint32_taddress32_hi;
boolhas_dedicated_vram;
-   boolhas_virtual_memory;
+   boolr600_has_virtual_memory;
boolgfx_ib_pad_with_type2;
boolhas_hw_decode;
unsignedib_start_alignment;
uint32_tnum_sdma_rings;
uint32_tnum_compute_rings;
uint32_tuvd_fw_version;
uint32_tvce_fw_version;
booluvd_enc_supported;
uint32_tme_fw_version;
uint32_tme_fw_feature;
diff --git a/src/gallium/drivers/r600/r600_buffer_common.c 
b/src/gallium/drivers/r600/r600_buffer_common.c
index ca19af9b2ef..17a8c3a596f 100644
--- a/src/gallium/drivers/r600/r600_buffer_common.c
+++ b/src/gallium/drivers/r600/r600_buffer_common.c
@@ -199,21 +199,21 @@ bool r600_alloc_resource(struct r600_common_screen 
*rscreen,
return false;
}
 
/* Replace the pointer such that if res->buf wasn't NULL, it won't be
 * NULL. This should prevent crashes with multiple contexts using
 * the same buffer where one of the contexts invalidates it while
 * the others are using it. */
old_buf = res->buf;
res->buf = new_buf; /* should be atomic */
 
-   if (rscreen->info.has_virtual_memory)
+   if (rscreen->info.r600_has_virtual_memory)
res->gpu_address = 
rscreen->ws->buffer_get_virtual_address(res->buf);
else
res->gpu_address = 0;
 
pb_reference(_buf, NULL);
 
util_range_set_empty(>valid_buffer_range);
 
/* Print debug information. */
if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
@@ -647,21 +647,21 @@ r600_buffer_from_user_memory(struct pipe_screen *screen,
util_range_add(>valid_buffer_range, 0, templ->width0);
util_range_add(>b.valid_buffer_range, 0, templ->width0);
 
/* Convert a user pointer to a buffer. */
rbuffer->buf = ws->buffer_from_ptr(ws, user_memory, templ->width0);
if (!rbuffer->buf) {
FREE(rbuffer);
return NULL;
}
 
-   if (rscreen->info.has_virtual_memory)
+   if

Re: [Mesa-dev] [PATCH 4/7] freedreno: a2xx: Support TEXTURE_RECT

2018-03-22 Thread Ilia Mirkin

On Thu, Mar 22, 2018 at 10:43 AM, Wladimir J. van der Laan
 wrote:
> Hello Ilia,
>
> On Thu, Jan 25, 2018 at 08:41:11AM -0500, Ilia Mirkin wrote:
>> Should you also expose PIPE_CAP_TEXTURE_RECTANGLE? (Or whatever it's
>> called... I forget.)
>
> I checked and I don't think a capability exists for this (anymore?).
>
> Everywhere, the assumption is meant that all Gallium drivers support, or at 
> least emulate this.
>
> For example in src/mesa/state_tracker/st_extensions.c:
>
> extensions->NV_texture_rectangle = GL_TRUE;

You're probably right - texture rect is required as part of Gallium.
Probably always has been.
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