From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/builtin_functions.cpp | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/builtin_functions.cpp
b/src/compiler/glsl/builtin_functions.cpp
index
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/glsl_to_nir.cpp| 32 ++--
src/compiler/nir/nir_intrinsics.py | 11 +-
src/compiler/nir/nir_lower_atomics_to_ssbo.c | 6 +-
src/compiler/nir/nir_lower_io.c
From: Ian Romanick
This is a strictly alphabetic sort, as is done in extensions_table.h
There are other options. We should pick one and document it. Right
now, this file is chaos.
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/intel_extensions.c | 6 +++---
1 file changed, 3
From: Ian Romanick
Also expand the message type field by a single bit. This is necessary
for this Gen9 message type, but there are also Gen8 message types that
need the extra bit (mostly for bindless).
Signed-off-by: Ian Romanick
---
src/intel/compiler/brw_disasm.c | 15
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/lower_ubo_reference.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/compiler/glsl/lower_ubo_reference.cpp
b/src/compiler/glsl/lower_ubo_reference.cpp
index 453c0fa2b06..5e1f281174c 100644
I initially started implementing support for NV_shader_atomic_float. I
had misunderstood the hardware specs, and Intel hardware cannot actually
do that extension. It does have some floating-point atomic support, so
I decided to create an extension based on what the hardware actually can
do. I
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/glsl_parser_extras.cpp | 1 +
src/compiler/glsl/glsl_parser_extras.h | 2 ++
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 1 +
4 files changed, 5 insertions(+)
diff --git
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index a58158bb61d..f6cbfaf3812 100644
---
From: Ian Romanick
src/intel/compiler/brw_disasm_info.c: In function ‘nir_print_instr’:
src/intel/compiler/brw_disasm_info.c:30:61: warning: unused parameter ‘instr’
[-Wunused-parameter]
__attribute__((weak)) void nir_print_instr(const nir_instr *instr, FILE *fp) {}
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/gl_nir_lower_samplers_as_deref.c | 1 +
src/compiler/glsl/glsl_to_nir.cpp | 18 +-
src/compiler/nir/nir_intrinsics.py | 4
src/compiler/nir/nir_lower_atomics_to_ssbo.c
From: Ian Romanick
---
src/compiler/glsl/glsl_parser_extras.cpp | 1 +
src/compiler/glsl/glsl_parser_extras.h | 2 ++
src/mesa/main/extensions_table.h | 1 +
src/mesa/main/mtypes.h | 1 +
4 files changed, 5 insertions(+)
diff --git
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/builtin_functions.cpp | 51 +++--
1 file changed, 48 insertions(+), 3 deletions(-)
diff --git a/src/compiler/glsl/builtin_functions.cpp
b/src/compiler/glsl/builtin_functions.cpp
index
From: Ian Romanick
v2: Describe interactions with the capabilities added by
SPV_INTEL_shader_atomic_float_minmax
v3: Remove 64-bit float support.
v4: Explain NaN issues. Explain issues with atomicMin(-0, +0) and
atomicMax(-0, +0).
Signed-off-by: Ian Romanick
---
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/glsl/lower_shared_reference.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/compiler/glsl/lower_shared_reference.cpp
b/src/compiler/glsl/lower_shared_reference.cpp
index a46d05419e5..5954ccce445
Yes, CMASK can't have a greater size than 4 GB.
Marek
On Fri, Jun 22, 2018 at 7:13 PM, Timothy Arceri wrote:
> This does more than moving. Can you add a commit message about why its safe
> to change cmask_size from uint64_t -> uint32_t
>
>
> On 23/06/18 08:32, Marek Olšák wrote:
>>
>> From:
On 23/06/18 11:16, Mike Lothian wrote:
I think you forgot to bump PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY to 430
I should have been more clear. The missing extension support is:
ARB_draw_indirect/ARB_multi_draw_indirect
ARB_vertex_attrib_64bit
Once these are done we should be able to flip
I think you forgot to bump PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY to 430
On Fri, 22 Jun 2018 at 09:48 Timothy Arceri wrote:
> I've send all of these patches out already. The only change is to the
> first 2 patches which fixes things so we store a double as 2 unsigned ints
> rather than 2
On 22/06/18 18:47, Timothy Arceri wrote:
The extension is enabled for compat profile but there is currently
no display list support.
---
src/mesa/main/dlist.c | 87 +++
1 file changed, 87 insertions(+)
diff --git a/src/mesa/main/dlist.c
On Fri, Jun 22, 2018 at 8:22 PM, Miguel Angel Vico wrote:
>
>
> On Thu, 21 Jun 2018 22:09:14 -0400
> Ilia Mirkin wrote:
>
>> Hi Miguel,
>>
>> Preface: I know little about this ext, so feel free to educate me on
>> the wrongness of my thinking.
>>
>> On Thu, Jun 21, 2018 at 10:01 PM, Miguel A.
On Thu, 21 Jun 2018 22:09:14 -0400
Ilia Mirkin wrote:
> Hi Miguel,
>
> Preface: I know little about this ext, so feel free to educate me on
> the wrongness of my thinking.
>
> On Thu, Jun 21, 2018 at 10:01 PM, Miguel A. Vico wrote:
> > Add memory object support for nvc0 and nv50
> >
> >
Reviewed-by: Timothy Arceri
On 23/06/18 06:11, Eric Anholt wrote:
The always_active_io flag was only set according to the first variable
that got packed in, so NIR io compaction would end up compacting XFB
varyings that shouldn't move at that point.
---
This doesn't fix my XFB issues on V3D,
https://bugs.freedesktop.org/show_bug.cgi?id=106958
--- Comment #7 from Giovanni ongaro ---
could not start the trace with f12 but i managed to get an apitrace under win7
and rx480 i wonder if this could be useful
--
You are receiving this mail because:
You are the QA Contact for the bug.
You
In the subject line you need to change:
ac_build_gather_values -> lp_build_gather_values
Series:
Reviewed-by: Timothy Arceri
On 23/06/18 08:31, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 45 +--
This does more than moving. Can you add a commit message about why its
safe to change cmask_size from uint64_t -> uint32_t
On 23/06/18 08:32, Marek Olšák wrote:
From: Marek Olšák
---
src/amd/common/ac_surface.c | 6 +++---
src/amd/common/ac_surface.h | 16
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 34 ++-
.../drivers/radeonsi/si_shader_tgsi_alu.c | 10 +++---
.../drivers/radeonsi/si_shader_tgsi_mem.c | 15
3 files changed, 29 insertions(+), 30 deletions(-)
diff --git
From: Marek Olšák
cmask_buffer and surface.cmask_size can replace its role.
---
src/gallium/drivers/radeonsi/si_blit.c| 8 ++---
src/gallium/drivers/radeonsi/si_clear.c | 17 +++---
src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
src/gallium/drivers/radeonsi/si_pipe.h
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_pipe.h| 2 +-
src/gallium/drivers/radeonsi/si_texture.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_buffer.c | 16 ++--
src/gallium/drivers/radeonsi/si_pipe.c| 2 +-
src/gallium/drivers/radeonsi/si_pipe.h| 2 +-
src/gallium/drivers/radeonsi/si_texture.c | 30 +++
4 files changed, 25 insertions(+), 25
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
src/gallium/drivers/radeonsi/si_pipe.h | 1 -
src/gallium/drivers/radeonsi/si_shader.c | 6 +-
src/gallium/drivers/radeonsi/si_shader_internal.h | 2 --
From: Marek Olšák
---
src/amd/common/ac_surface.c | 61 +++
src/amd/common/ac_surface.h | 5 ++
src/gallium/drivers/radeonsi/si_clear.c | 14 ++--
src/gallium/drivers/radeonsi/si_pipe.h| 7 +-
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_texture.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index 3152f742ae6..307062daf2f 100644
---
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index c39b80bb396..9f2d323459d 100644
---
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 68 +--
.../drivers/radeonsi/si_shader_tgsi_mem.c | 15 ++--
2 files changed, 38 insertions(+), 45 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c| 17 -
.../drivers/radeonsi/si_shader_tgsi_alu.c | 17 -
.../drivers/radeonsi/si_shader_tgsi_mem.c | 7 ++-
3 files changed, 18 insertions(+), 23 deletions(-)
diff --git
From: Marek Olšák
---
src/amd/common/ac_surface.c | 6 +++---
src/amd/common/ac_surface.h | 16
src/amd/vulkan/radv_image.c | 4 ++--
src/gallium/drivers/radeonsi/si_texture.c | 6 +++---
4 files changed, 16 insertions(+), 16
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_texture.c | 152 ++
1 file changed, 71 insertions(+), 81 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index 05d5d1b8a6d..0cc5ad3f94a 100644
---
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_blit.c| 8 ++--
src/gallium/drivers/radeonsi/si_clear.c | 14 +++---
src/gallium/drivers/radeonsi/si_descriptors.c | 2 +-
src/gallium/drivers/radeonsi/si_pipe.h| 10 ++--
src/gallium/drivers/radeonsi/si_state.c
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 7 +++
.../drivers/radeonsi/si_shader_tgsi_setup.c | 19 ---
2 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 30 +--
src/gallium/drivers/radeonsi/si_shader.h | 1 -
.../drivers/radeonsi/si_shader_internal.h | 3 --
.../drivers/radeonsi/si_state_shaders.c | 7 +++--
4 files changed, 18 insertions(+),
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 4 ++--
src/gallium/drivers/radeonsi/si_shader_nir.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_blit.c| 4 ++--
src/gallium/drivers/radeonsi/si_pipe.h| 2 +-
src/gallium/drivers/radeonsi/si_state.c | 28 +++
src/gallium/drivers/radeonsi/si_texture.c | 2 +-
4 files changed, 18 insertions(+), 18
From: Marek Olšák
The real offset is passed through resource_from_memobj.
---
src/gallium/drivers/radeonsi/si_pipe.h| 1 -
src/gallium/drivers/radeonsi/si_texture.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 45 +--
.../drivers/radeonsi/si_shader_tgsi_mem.c | 5 +--
.../drivers/radeonsi/si_shader_tgsi_setup.c | 3 +-
3 files changed, 25 insertions(+), 28 deletions(-)
diff --git
zhaowei yuan writes:
> "sampler2DRect" and "sampler2DRectShadow" are specified as
> reserved from GLSL 1.1 and GLSL ES 1.0
>
> Signed-off-by: zhaowei yuan
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106906
It looks like this:
Fixes: 34f7e761bc61 ("glsl/parser: Track built-in
Quoting Marek Olšák (2018-06-22 14:16:36)
> On Fri, Jun 22, 2018 at 12:48 PM, Dylan Baker wrote:
> > Quoting Marek Olšák (2018-06-20 18:01:55)
> >> From: Marek Olšák
> >>
> >> Cc: 18.1
> >> ---
> >> src/gallium/drivers/radeonsi/si_texture.c | 5 +
> >> 1 file changed, 5 insertions(+)
> >>
On Fri, Jun 22, 2018 at 12:48 PM, Dylan Baker wrote:
> Quoting Marek Olšák (2018-06-20 18:01:55)
>> From: Marek Olšák
>>
>> Cc: 18.1
>> ---
>> src/gallium/drivers/radeonsi/si_texture.c | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/src/gallium/drivers/radeonsi/si_texture.c
This definitely breaks odd things at least on Kepler (which is
extremely odd, given that I have no idea what it does). Unfortunately
I don't have a record of what, but it's slightly odd things. I wonder
if it's texture buffers, which we've recently gotten some extra
information about.
On Fri, Jun
Patches 14-16 are
Reviewed-by: Rafael Antognolli
On Thu, Jun 21, 2018 at 05:29:13PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/dev/gen_device_info.c | 47 ++---
> src/intel/dev/gen_device_info.h | 5
> 2 files
It doesn't seem to be used and removing it doesn't seem to break things on
my GP106.
Signed-off-by: Rhys Perry
---
src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 3 ---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 8 +---
2 files changed, 1 insertion(+), 10 deletions(-)
diff --git
With this commit, things no longer break if NVC0_CB_AUX_TEX_INFO is
changed to anything other than 0x20.
Fixes: 902bbda81b31bacb2a8c60ca6a8ba8ca34ae73d3
("nvc0: avoid using magic numbers for the uniform_bo offsets")
Signed-off-by: Rhys Perry
---
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c |
Tested-by: Mark Janes
Iago Toral writes:
> Thanks Andrii, this version looks good to me.
>
> Mark: this change fixes a GPU hang in sandy bridge with geometry
> shaders (the change itself affects a path in the driver that is only
> executed in SNB with GS, so nothing else is affected). While I
The always_active_io flag was only set according to the first variable
that got packed in, so NIR io compaction would end up compacting XFB
varyings that shouldn't move at that point.
---
This doesn't fix my XFB issues on V3D, but seems like a step in the
right direction. Packing
On June 22, 2018 11:52:54 Kenneth Graunke wrote:
On Friday, June 22, 2018 8:28:47 AM PDT Jason Ekstrand wrote:
On Thu, Jun 21, 2018 at 1:03 AM, Kenneth Graunke
wrote:
On Thursday, May 31, 2018 10:06:47 PM PDT Jason Ekstrand wrote:
[snip]
@@ -529,57 +509,55 @@ static bool
On Thu, Jun 21, 2018 at 05:29:12PM +0100, Lionel Landwerlin wrote:
> From: Scott D Phillips
>
> For gen8+, write out PPGTT tables in aub files so that full 48-bit
> addresses can be serialized.
I don't fully understand how things worked before this patch, in the
GEN < 10 case. It looks to me
Hi Iago,
It is usually safe to push changes to CI which provoke GPU hangs.
Occasionally, systems do not recover, so I appreciate the extra
notification.
I've sent this commit for testing and will let you know how it goes.
-Mark
Iago Toral writes:
> Thanks Andrii, this version looks good to
FWIW,
Reviewed-by: James Jones
For the series, but someone more familiar with Nouveau should probably
review as well.
Thanks,
-James
On 06/21/2018 07:01 PM, Miguel A. Vico wrote:
Enable EXT_external_objects for nvc0 and nv50
Signed-off-by: Miguel A Vico Moya
---
On Friday, June 22, 2018 10:10:51 AM PDT Dylan Baker wrote:
> _xmvc -> _xvmc. Sigh
>
> Fixes: a6943bb4ce99ea7af7222552f1326fb80823d0b2
>("meson: Fix auto option for xvmc")
> Signed-off-by: Dylan Baker
> ---
> meson.build | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff
Ported from RadeonSI.
This appears to fix some random fails with:
dEQP-VK.query_pool.statistics_query.*
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 6 --
src/amd/vulkan/radv_private.h | 4
src/amd/vulkan/radv_query.c| 11 +++
_xmvc -> _xvmc. Sigh
Fixes: a6943bb4ce99ea7af7222552f1326fb80823d0b2
("meson: Fix auto option for xvmc")
Signed-off-by: Dylan Baker
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index e88616c9e82..b2722c71e5b 100644
---
On Friday, June 22, 2018 8:28:47 AM PDT Jason Ekstrand wrote:
> On Thu, Jun 21, 2018 at 1:03 AM, Kenneth Graunke
> wrote:
>
> > On Thursday, May 31, 2018 10:06:47 PM PDT Jason Ekstrand wrote:
> > [snip]
> > > @@ -529,57 +509,55 @@ static bool
> > > load_from_deref_entry_value(struct
Quoting Marek Olšák (2018-06-20 18:01:55)
> From: Marek Olšák
>
> Cc: 18.1
> ---
> src/gallium/drivers/radeonsi/si_texture.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_texture.c
> b/src/gallium/drivers/radeonsi/si_texture.c
> index
https://bugs.freedesktop.org/show_bug.cgi?id=106824
Alok Hota changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On 22/06/18 16:41, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-06-21 17:29:04)
From: Jason Ekstrand
This is a simple, invasive, liberally licensed red-black tree
implementation. It's an invasive data structure similar to the
Linux kernel linked-list where the intention is that you
Quoting Lionel Landwerlin (2018-06-21 17:29:04)
> From: Jason Ekstrand
>
> This is a simple, invasive, liberally licensed red-black tree
> implementation. It's an invasive data structure similar to the
> Linux kernel linked-list where the intention is that you embed a
s/linked-list/rbtree/
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Thu, Jun 21, 2018 at 2:39 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_device.c | 16 +++-
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_device.c
I'm wondering whether we need to do this more often in pipeline barriers?
Also I'd really appreciate if you could add a check to see if there is
any CP DMA activity in the first place.
On Thu, Jun 21, 2018 at 11:04 AM, Samuel Pitoiset
wrote:
> Ported from RadeonSI.
> This might fix some
On Thu, Jun 21, 2018 at 1:03 AM, Kenneth Graunke
wrote:
> On Thursday, May 31, 2018 10:06:47 PM PDT Jason Ekstrand wrote:
> [snip]
> > @@ -529,57 +509,55 @@ static bool
> > load_from_deref_entry_value(struct copy_prop_var_state *state,
> > struct copy_entry *entry,
This series replaces the dependency on
GRALLOC_MODULE_PERFORM_GET_DRM_FD with DRM node
probing and disables the support for drm_gralloc.
The series has been tested on Qemu+AOSP, where a
virtio gpu was successfully probed for and
opened.
The current branch can be found here:
From: Rob Herring
Maintaining both flink names and prime fd support which are provided by
2 different gralloc implementations is problematic because we have a
dependency on a specific gralloc implementation header.
This mostly disables the dependency on the gralloc implementation and
headers.
Signed-off-by: Robert Foss
Reviewed-by: Tomasz Figa
Reviewed-by: Marek Olšák
---
Changes since v4:
- Added r-b from Marek
Changes since v3:
- Added r-b from Tomasz
src/gallium/auxiliary/util/u_debug_stack_android.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
This patch both adds support for probing & filtering DRM nodes
and switches away from using the GRALLOC_MODULE_PERFORM_GET_DRM_FD
gralloc call.
Currently the filtering is based just on the driver name,
and the desired name is supplied using the "drm.gpu.vendor_name"
Android property.
https://bugs.freedesktop.org/show_bug.cgi?id=107001
Michel Dänzer changed:
What|Removed |Added
Component|Other |Drivers/Gallium/radeonsi
QA
https://bugs.freedesktop.org/show_bug.cgi?id=107001
Bug ID: 107001
Summary: hard system freeze with mesa 18.1.1 and 18.1.2 on AMD
RX 580
Product: Mesa
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux
---
.../swr/rasterizer/jitter/JitManager.cpp | 133 ++--
.../swr/rasterizer/jitter/builder_gfx_mem.cpp | 90 +
.../swr/rasterizer/jitter/builder_gfx_mem.h | 101 +-
.../jitter/functionpasses/lower_x86.cpp | 189 +-
4 files changed, 260
Sorry for the churn on these patches. They had to be split in three due
to some code changes in between a mass formatting change. Anyway this
patch contains only formatting changes for the files that were updated
in the last patch
Alok Hota (1):
swr/rast: Updating code style based on current
You are right.
On 06/22/2018 03:31 PM, Mike Lothian wrote:
I've just checked myself - this isn't in i965 yet:
Extended renderer info (GLX_MESA_query_renderer):
Vendor: Intel Open Source Technology Center (0x8086)
Device: Mesa DRI Intel(R) HD Graphics 530 (Skylake GT2) (0x191b)
If the driver doesn't support PIPE_FORMAT_B8G8R8A8_SRGB, fall back to
PIPE_FORMAT_R8G8B8A8_SRGB.
Drivers such as Virgl will have a hard time supporting
PIPE_FORMAT_B8G8R8A8_SRGB when the host runs GLES, as GL_ABGR isn't as
well suported there.
So go with PIPE_FORMAT_R8G8B8A8_SRGB so these
When Mesa itself implements ETC2 decompression, it currently
decompresses to formats in the GL_BGRA component order.
That can be problematic for drivers which cannot upload the texture data
as GL_BGRA, such as Virgl when it's backed by GLES on the host.
So this commit adds a flag to
and PIPE_FORMAT_R8G8B8A8_SRGB, as well.
The reason for this is that when Virgl runs with GLES on the host, it
cannot directly upload textures in BGRA.
So to avoid a conversion step, consider the RGB sRGB formats as well for
this extension.
Signed-off-by: Tomeu Vizoso
---
I've just checked myself - this isn't in i965 yet:
Extended renderer info (GLX_MESA_query_renderer):
Vendor: Intel Open Source Technology Center (0x8086)
Device: Mesa DRI Intel(R) HD Graphics 530 (Skylake GT2) (0x191b)
Version: 18.2.0
Accelerated: yes
Video memory: 3072MB
Hi
Does the whole of mesa support that or just radeonsi?
Cheers
Mike
On Fri, 22 Jun 2018 at 14:10 Samuel Pitoiset
wrote:
> Since mesa now exposes OpenGL 3.3 compat, we no longer need
> those workarounds.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/util/drirc | 12
> 1 file
On 06/20/2018 02:57 PM, emil.veli...@collabora.com wrote:
Hi Tomeu,
On Wed, May 23, 2018 at 10:54:06AM +0200, Tomeu Vizoso wrote:
--- a/src/mesa/main/texcompress_etc.h
+++ b/src/mesa/main/texcompress_etc.h
@@ -28,6 +28,7 @@
#include "glheader.h"
#include "texcompress.h"
#include
On 18 June 2018 at 23:19, Marek Olšák wrote:
> What about non-sRGB formats?
Only sRGB formats get unpacked to BGRA currently, so I don't need to
do anything about the others.
Thanks,
Tomeu
> Marek
>
> On Wed, May 23, 2018 at 4:54 AM, Tomeu Vizoso
> wrote:
>>
>> When Mesa itself implements
Since mesa now exposes OpenGL 3.3 compat, we no longer need
those workarounds.
Signed-off-by: Samuel Pitoiset
---
src/util/drirc | 12
1 file changed, 12 deletions(-)
diff --git a/src/util/drirc b/src/util/drirc
index 7f91035ae8..e50ec81865 100644
--- a/src/util/drirc
+++
Signed-off-by: Samuel Pitoiset
---
src/gallium/auxiliary/pipe-loader/driinfo_gallium.h | 1 -
src/gallium/include/state_tracker/st_api.h | 1 -
src/gallium/state_trackers/dri/dri_screen.c | 2 --
src/mesa/drivers/dri/i965/brw_context.c | 3 ---
Virgl could save a lot of work converting buffers in the host side
between formats if Mesa supported a bunch of other formats when reading
pixels.
This commit adds cases to handle specific formats so that the values
reported by the two calls match more closely the underlying native
formats.
In
Reviewed-by: Lionel Landwerlin
On 21/06/18 17:29, Lionel Landwerlin wrote:
From: Jason Ekstrand
This is a simple, invasive, liberally licensed red-black tree
implementation. It's an invasive data structure similar to the
Linux kernel linked-list where the intention is that you embed a
Reviewed-by: Bruce Cherniak
> On Jun 19, 2018, at 10:03 AM, Alok Hota wrote:
>
> These code changes were made in between some of the formatting changes.
> Unforunately we do have another formatting patch coming in after this,
> but I will keep that separate.
>
> These patches are primarily
https://bugs.freedesktop.org/show_bug.cgi?id=101405
Ashwini changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Resolution|FIXED
https://bugs.freedesktop.org/show_bug.cgi?id=101405
Ashwini changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=101405
Ashwini changed:
What|Removed |Added
CC||ashwini.patil@politrontech.
https://bugs.freedesktop.org/show_bug.cgi?id=106996
Sergii Romantsov changed:
What|Removed |Added
CC||sergii.romantsov@globallogi
https://bugs.freedesktop.org/show_bug.cgi?id=106283
--- Comment #13 from i...@yahoo.com ---
(In reply to Mark Janes from comment #12)
> do you have an apitrace file of your workload, so I can test this
> functionality in FrameRetrace?
The needed functionality was to dig deeper into bug #91808.
Thanks Andrii, this version looks good to me.
Mark: this change fixes a GPU hang in sandy bridge with geometry
shaders (the change itself affects a path in the driver that is only
executed in SNB with GS, so nothing else is affected). While I think
the change in here is correct according to the
For texture array lookup the slice index is evaluated according to
idx = floor(z + 0.5)
This patch implements the first part by adding 0.5 to the according
texture coordinate when appropriate.
Signed-off-by: Gert Wollny
---
src/gallium/drivers/r600/r600_shader.c | 64
these two patches correct the offets and the rounding modes for the
index evaluation when accessing texture arrays. The patches were tested
with the gles3 test suite where they fix a number of tests related to 2D
texture arrays and didn't show any regressions.
Best,
Gert
Gert Wollny (2):
The evaluation of the array layer index is "floor(z+0.5)", and the default
rounding mode doesn't correctly evaluate this. Therefore, set the rounding
mode to "trunc" and and z-filter mode to "point".
For 3D textures make sure the the default rounding mode and z-filter are
used.
Fixes:
---
src/mesa/main/extensions_table.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index bc1f21a2926..b1ee0214d6c 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@
The extension is enabled for compat profile but there is currently
no display list support.
---
src/mesa/main/dlist.c | 87 +++
1 file changed, 87 insertions(+)
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index b2b1f723a17..c11b4c06fe5
---
src/mapi/glapi/gen/apiexec.py| 16
src/mesa/main/extensions_table.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/src/mapi/glapi/gen/apiexec.py b/src/mapi/glapi/gen/apiexec.py
index e69c6b4df16..1a91785d375 100644
---
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