Re: [Mesa-dev] [PATCH 6/6] anv: Add support for the on-disk shader cache

Series: Reviewed-by: Timothy Arceri On 30/06/18 13:44, Jason Ekstrand wrote: --- src/intel/vulkan/anv_device.c | 36 ++ src/intel/vulkan/anv_pipeline_cache.c | 98 --- src/intel/vulkan/anv_private.h| 3 + 3 files changed, 126

Re: [Mesa-dev] [PATCH v2 6/9] nir: Add a large constants optimization pass

On Fri, Jun 29, 2018 at 9:56 PM, Timothy Arceri wrote: > On 30/06/18 10:13, Jason Ekstrand wrote: > >> This pass searches for reasonably large local variables which can be >> statically proven to be constant and moves them into shader constant >> data. This is especially useful when large

Re: [Mesa-dev] [PATCH] glsl/cache: save and restore ExternalSamplersUsed

Reviewed-by: Timothy Arceri On 30/06/18 14:59, Marek Olšák wrote: From: Marek Olšák Shaders that need special code for external samplers were broken if they were loaded from the cache. Cc: 18.1 --- src/compiler/glsl/serialize.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git

[Mesa-dev] [PATCH] glsl/cache: save and restore ExternalSamplersUsed

From: Marek Olšák Shaders that need special code for external samplers were broken if they were loaded from the cache. Cc: 18.1 --- src/compiler/glsl/serialize.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/glsl/serialize.cpp b/src/compiler/glsl/serialize.cpp index

Re: [Mesa-dev] [PATCH v2 6/9] nir: Add a large constants optimization pass

On 30/06/18 10:13, Jason Ekstrand wrote: This pass searches for reasonably large local variables which can be statically proven to be constant and moves them into shader constant data. This is especially useful when large tables are baked into the shader source code because they can be moved

[Mesa-dev] [PATCH] ac: move all LLVM module initialization into ac_create_module

From: Marek Olšák This removes some ugly code around module initialization. --- Dave, please rebase your code on top of this, and we don't need triple and data_layout in ac_llvm_compiler_info. src/amd/common/ac_llvm_helper.cpp | 10 ++ src/amd/common/ac_llvm_util.h

Re: [Mesa-dev] [PATCH 11/11] ac/radv: using tls to store llvm related info and speed up compiles (v3)

I wonder if we can somehow make the TLS magic apply to RADV only. Radeonsi can do it without TLS. Then, the RADV-specific TLS code can be moved to RADV, and other code (if any) can be shared. It doesn't make much sense to do the TLS initialization in ac_llvm_compiler_init. It could be done in

Re: [Mesa-dev] [PATCH 09/11] radeonsi: port to shared ac llvm per-thread structs.

On Tue, Jun 26, 2018 at 11:58 PM, Dave Airlie wrote: > From: Dave Airlie > > The new structs are pretty much based on the radeonsi code, > so it just ports over the uses to them. > --- > src/gallium/drivers/radeonsi/si_compute.c | 2 +- > src/gallium/drivers/radeonsi/si_pipe.c| 50

[Mesa-dev] [PATCH 0/6] anv: Add support for an on-disk transparent pipeline

I've been resisting this for a long time and I'm still a bit grumpy about it but I think Pierre-Loup has convinced me that it really is needed for steam shader caching. This series gives apps that don't use a pipeline cache a default in-memory cache as well as backing them with the disk cache in

[Mesa-dev] [PATCH 6/6] anv: Add support for the on-disk shader cache

--- src/intel/vulkan/anv_device.c | 36 ++ src/intel/vulkan/anv_pipeline_cache.c | 98 --- src/intel/vulkan/anv_private.h| 3 + 3 files changed, 126 insertions(+), 11 deletions(-) diff --git a/src/intel/vulkan/anv_device.c

[Mesa-dev] [PATCH 2/6] anv: Use a default pipeline cache if none is specified

If a client is dumb enough to not specify a pipeline cache, give it a default. We have to create one anyway for blorp so we may as well let the client cache shaders in it. --- src/intel/vulkan/anv_blorp.c | 12 +--- src/intel/vulkan/anv_device.c | 7 +++

[Mesa-dev] [PATCH 5/6] anv/pipeline_cache: Add a _locked suffix to a function

--- src/intel/vulkan/anv_pipeline_cache.c | 29 ++- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline_cache.c b/src/intel/vulkan/anv_pipeline_cache.c index 2bc64f5bdd1..e57cd1c75c6 100644 ---

[Mesa-dev] [PATCH 3/6] anv/pipeline: Stop optimizing for not having a cache

Before, we were only hashing the shader if we had a shader cache to cache things in. This means that if we ever get it wrong, we could end up trying to cache a shader with an undefined hash. Since not having a shader cache is an extremely uncommon case, let's optimize for code clarity and

[Mesa-dev] [PATCH 4/6] anv: Add device-level helpers for searching for and uploading kernels

--- src/intel/vulkan/anv_pipeline.c | 127 ++ src/intel/vulkan/anv_pipeline_cache.c | 34 +++ src/intel/vulkan/anv_private.h| 16 3 files changed, 98 insertions(+), 79 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c

[Mesa-dev] [PATCH 1/6] anv: Be more careful about hashing pipeline layouts

Previously, we just hashed the entire descriptor set layout verbatim. This meant that a bunch of extra stuff such as pointers and reference counts made its way into the cache. It also meant that we weren't properly hashing in the Y'CbCr conversion information information from bound immutable

Re: [Mesa-dev] [PATCH 07/11] ac/radv: move llvm compiler info to struct and init in one place

On Tue, Jun 26, 2018 at 11:58 PM, Dave Airlie wrote: > From: Dave Airlie > > This creates a common per-thread compiler info struct, and adds > the init code to it. This is mostly ported from radeonsi. > > The common info struct is used in radv first and replaces the > current code. > --- >

Re: [Mesa-dev] [PATCH 01/11] ac/radv: split the non-common init_once code from the common target code.

On Tue, Jun 26, 2018 at 11:58 PM, Dave Airlie wrote: > From: Dave Airlie > > This just splits out the non-shared code and reuses ac_get_llvm_target in > radv. > --- > src/amd/common/ac_llvm_util.c | 6 -- > src/amd/common/ac_llvm_util.h | 2 ++ >

[Mesa-dev] [PATCH v2] nvc0/ir: return 0 in imageLoad on incomplete textures

We already guarded all OP_SULDP against out of bound accesses, but those ended up just reusing whatever value was stored in the dest registers. fixes CTS test shader_image_load_store.incomplete_textures v2: fix for loads not ending up with predicates (bindless_texture) Signed-off-by: Karol

Re: [Mesa-dev] [PATCH 19/19] i965: Support saving the gen program with glGetProgramBinary

I've sent some minor nits. Otherwise the series looks good, although I did only skim most of the actual new i965 blob changes. Series: Reviewed-by: Timothy Arceri You might want to wait for Tapani to take a look also. On 15/05/18 02:52, Jordan Justen wrote: Signed-off-by: Jordan Justen ---

Re: [Mesa-dev] [PATCH 16/19] i965: Add brw_populate_default_key

On 15/05/18 02:52, Jordan Justen wrote: We will need to populate the default key for ARB_get_program_binary to allow us to retrieve the default gen program to store save in the store save - > store ??? program binary. Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_cs.c

Re: [Mesa-dev] [PATCH 09/19] i965: Add brw_stage_cache_id to map gl stages to brw cache_ids

On 15/05/18 02:52, Jordan Justen wrote: Signed-off-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_program_cache.c | 15 +++ src/mesa/drivers/dri/i965/brw_state.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_program_cache.c

Re: [Mesa-dev] [PATCH 03/19] st/mesa: i965: Use ShaderCacheSerializeDriverBlob driver function

The subject line contains i965: On 15/05/18 02:52, Jordan Justen wrote: Signed-off-by: Jordan Justen --- src/mesa/state_tracker/st_context.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/state_tracker/st_context.c b/src/mesa/state_tracker/st_context.c index

[Mesa-dev] [PATCH v2 6/9] nir: Add a large constants optimization pass

This pass searches for reasonably large local variables which can be statically proven to be constant and moves them into shader constant data. This is especially useful when large tables are baked into the shader source code because they can be moved into a UBO by the driver to reduce register

[Mesa-dev] [PATCH v2 9/9] anv, intel: Enable nir_opt_large_constants for Vulkan

According to RenderDoc, this shaves 99.6% of the run time off of the ambient occlusion pass in Skyrim Special Edition when running under DXVK and shaves 92% off the runtime for a reasonably representative frame. When running the actual game, Skyrim goes from being a slide-show to a very stable and

[Mesa-dev] [PATCH v2 5/9] nir: Add a concept of constant data associated with a shader

This commit adds a concept to NIR of having a blob of constant data associated with a shader. Instead of being a UBO or uniform that can be manipulated by the client, this constant data considered part of the shader and remains constant across all invocations of the given shader until the end of

[Mesa-dev] [PATCH v2 2/9] nir: Add a deref_instr_has_indirect helper

--- src/compiler/nir/nir.h | 2 ++ src/compiler/nir/nir_deref.c | 18 ++ 2 files changed, 20 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index c16ce547642..e35bef612df 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -987,6

[Mesa-dev] [PATCH v2 8/9] anv: Add state setup support for shader constants

--- .../vulkan/anv_nir_apply_pipeline_layout.c| 47 src/intel/vulkan/anv_private.h| 1 + src/intel/vulkan/genX_cmd_buffer.c| 72 ++- 3 files changed, 101 insertions(+), 19 deletions(-) diff --git

[Mesa-dev] [PATCH v2 4/9] nir/deref: Add helpers for getting offsets

These are very similar to the related function in nir_lower_io except that they don't handle per-vertex or packed things (that could be added, in theory) and they take a more detailed size/align function pointer. One day, we should consider switching nir_lower_io over to using the more detailed

[Mesa-dev] [PATCH v2 7/9] anv: Add support for shader constant data to the pipeline cache

--- src/intel/vulkan/anv_blorp.c | 1 + src/intel/vulkan/anv_pipeline.c | 16 src/intel/vulkan/anv_pipeline_cache.c | 27 +++ src/intel/vulkan/anv_private.h| 6 ++ 4 files changed, 50 insertions(+) diff --git

[Mesa-dev] [PATCH v2 3/9] nir/types: Add a natural size and alignment helper

The size and alignment are "natural" in the sense that everything is aligned to a scalar. This is a bit tighter than std430 where vec3s are required to be aligned to a vec4. --- src/compiler/nir_types.cpp | 56 ++ src/compiler/nir_types.h | 6 2 files

[Mesa-dev] [PATCH v2 1/9] util/macros: Import ALIGN_POT from ralloc.c

--- src/util/macros.h | 3 +++ src/util/ralloc.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/util/macros.h b/src/util/macros.h index 6d3df904082..95b86c7a31a 100644 --- a/src/util/macros.h +++ b/src/util/macros.h @@ -285,6 +285,9 @@ do { \

[Mesa-dev] [PATCH v2 0/9] anv,nir: Move large constants to a UBO

This little series adds an optimization pass to NIR and wires up up in anv that moves large constant variables to a UBO. This fixes a farily common case in some filter or ambient occlusion shaders where they put some sort of look-up table in the shader itself. This series takes Skyrim Special

[Mesa-dev] [PATCH v8 26/33] nvir/nir: implement variable indexing

We store those arrays in local memory and reserve some space for each of the arrays. With NIR we could store those arrays packed, but we don't do that yet as it causes MemoryOpt to generate unaligned memory accesses. v3: use fixed size vec4 arrays until we fix MemoryOpt v4: fix for 64 bit types

[Mesa-dev] [PATCH v8 30/33] nvir/nir: implement images

v3: fix compiler warnings v4: use loadFrom helper v5: fix signed min/max v6: set tex mask add support for indirect image access set cache mode v7: make compatible with 884d27bcf688d36c3bbe01bceca525595add3b33 rework the whole deref thing to prepare for bindless v8: port to deref

[Mesa-dev] [PATCH v8 33/33] nvir/nir: implement intrinsic shader_clock

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp index f4875113d00..ed2453136fd

[Mesa-dev] [PATCH v8 29/33] nvir/nir: implement ssbo intrinsics

v4: use loadFrom helper v5: support indirect buffer access v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 90 +++ 1 file changed, 90 insertions(+) diff --git

[Mesa-dev] [PATCH v8 23/33] nvir/nir: implement nir_instr_type_tex

a lot of those fields are not valid for a lot of tex ops. Not quite sure if it's worth the effort to check for those or just keep it like that. It seems to kind of work. v2: reworked offset handling add tex support with indirect R/S arguments handle GLSL_SAMPLER_DIM_EXTERNAL drop

[Mesa-dev] [PATCH v8 20/33] nvir/nir: implement intrinsic_discard(_if)

Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp index

[Mesa-dev] [PATCH v8 31/33] nvir/nir: add memory barriers

v5: add more barrier intrinsics Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v8 22/33] nvir/nir: implement nir_ssa_undef_instr

v2: use mkOp v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp| 13 + 1 file changed, 13 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v8 11/33] nvir/nir: run assignSlots

v2: add support for geometry shaders set idx add some missing mappings fix for 64bit inputs/outputs fix up some FP color output index messup parse centroid flag v3: fix arrays in outputs as well fix input/ouput size calculation for tessellation shaders v4: add

[Mesa-dev] [PATCH v8 28/33] nvir/nir: implement nir_intrinsic_load_ubo

v4: use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v8 21/33] nvir/nir: implement loading system values

v2: support more sys values fixed a bug where for multi component reads all values ended up in x v3: add load_patch_vertices_in v4: add subgroup stuff v5: add helper invocation v6: fix loading 64 bit system values v8: don't require C++11 features Signed-off-by: Karol Herbst ---

[Mesa-dev] [PATCH v8 18/33] nvir/nir: implement nir_intrinsic_store_(per_vertex_)output

v3: add workaround for RA issues indirects have to be multiplied by 0x10 fix indirect access v4: use smarter getIndirect helper use storeTo helper v5: don't use const_offset directly v8: don't require C++11 features Signed-off-by: Karol Herbst ---

[Mesa-dev] [PATCH v8 12/33] nvir/nir: add loadFrom and storeTo helpler

v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 72 +++ 1 file changed, 72 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v8 24/33] nvir/nir: add getOperation for intrinsics

v7: don't assert in default case Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 22 +++ 1 file changed, 22 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v8 25/33] nvir/nir: implement vote and ballot

v2: add vote_eq support use the new subop intrinsic helper add ballot v3: add read_(first_)invocation v8: handle vectorized intrinsics don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 44 +++ 1 file changed,

[Mesa-dev] [PATCH v8 27/33] nvir/nir: implement geometry shader nir_intrinsics

v4: use smarter getIndirect helper use new getSlotAddress helper use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 27 +++ 1 file changed, 27 insertions(+) diff --git

[Mesa-dev] [PATCH v8 32/33] nvir/nir: implement load_per_vertex_output

v4: use smarter getIndirect helper use new getSlotAddress helper v5: use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 23 +++ 1 file changed, 23 insertions(+) diff --git

[Mesa-dev] [PATCH v8 13/33] nvir/nir: parse NIR shader info

v2: parse a few more fields v3: add special handling for GL_ISOLINES v8: set info->prop.fp.readsSampleLocations don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 325 +- 1 file changed, 323 insertions(+), 2

[Mesa-dev] [PATCH v8 17/33] nvir/nir: implement nir_intrinsic_load_uniform

v2: use new getIndirect helper fixes symbols for 64 bit types v4: use smarter getIndirect helper simplify address calculation use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 10 ++

[Mesa-dev] [PATCH v8 10/33] nvir/nir: add nir type helper functions

v4: treat imul as unsigned v5: remove pointless !! v7: inot is unsigned as well v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 115 ++ 1 file changed, 115 insertions(+) diff --git

[Mesa-dev] [PATCH v8 19/33] nvir/nir: implement load_(interpolated_)input/output

v3: and load_output v4: use smarter getIndirect helper use new getSlotAddress helper v5: don't use const_offset directly fix for indirects v6: add support for interpolateAt v7: fix compiler warnings add load_barycentric_sample handle load_output for fragment shaders v8: set

[Mesa-dev] [PATCH v8 05/33] nouveau: add support for nir

not all those nir options are actually required, it just made the work a little easier. v2: fix asserts parse compute shaders don't lower bitfield_insert v3: fix memory leak v4: don't lower fmod32 v5: set lower_all_io_to_temps to false fix memory leak because we take over ownership of

[Mesa-dev] [PATCH v8 08/33] nvir/nir: run some passes to make the conversion easier

v2: add constant_folding v6: print non final NIR only for verbose debugging v8: add passes we will need for OpenCL compute shaders Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 41 +++ 1 file changed, 41 insertions(+) diff --git

[Mesa-dev] [PATCH v8 09/33] nvir/nir: track defs and provide easy access functions

v2: add helper function for indirects v4: add new getIndirect overload for easier use v5: use getSSA for ssa values we can just create the values for unassigned registers in getSrc v6: always create at least 32 bit values v8: don't require C++11 features Signed-off-by: Karol Herbst ---

[Mesa-dev] [PATCH v8 16/33] nvir/nir: implement nir_alu_instr handling

v2: user bitfield_insert instead of bfi rework switch helper macros remove some lowering code (LoweringHelper is now used for this) v3: add pack_half_2x16_split add unpack_half_2x16_split_x/y v5: replace first argument with nullptr in loadImm calls prefer getSSA over getScratch v8:

[Mesa-dev] [PATCH v8 15/33] nvir/nir: add skeleton for nir_intrinsic_instr

Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp| 17 + 1 file changed, 17 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp index

[Mesa-dev] [PATCH v8 14/33] nvir/nir: implement nir_load_const_instr

v8: fix loading 8/16 bit constants Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 28 +++ 1 file changed, 28 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v8 02/33] nvc0: print the shader type when dumping headers

this makes debugging the shader header a little easier Acked-by: Pierre Moreau Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c

[Mesa-dev] [PATCH v8 07/33] nouveau: fix nir and TGSI shader cache collision

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nouveau_screen.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c b/src/gallium/drivers/nouveau/nouveau_screen.c index 03c1c74160f..7acf2050f10 100644 ---

[Mesa-dev] [PATCH v8 00/33] Nouveau NIR support

I think this is finally getting complete. There are a handful of piglit and CTS regressions, but those are caused by issues in common nir and gallium code. Some features remain disabled like bindless textures, because there is more ground work needed to be able to properly do it with nir.

[Mesa-dev] [PATCH v8 03/33] nvir: move common converter code in base class

v2: remove TGSI related bits Signed-off-by: Karol Herbst Reviewed-by: Pierre Moreau --- src/gallium/drivers/nouveau/Makefile.sources | 2 + .../nouveau/codegen/nv50_ir_from_common.cpp | 107 ++ .../nouveau/codegen/nv50_ir_from_common.h | 58 ++

[Mesa-dev] [PATCH v8 04/33] nvir: add lowering helper

this is mostly usefull for lazy IR converters not wanting to deal with 64 bit lowering and other illegal stuff v5: also handle SAT v6: rename type variables fixed lowering of NEG add lowering of NOT v8: don't require C++11 features Signed-off-by: Karol Herbst ---

[Mesa-dev] [PATCH v8 06/33] nouveau: add env var to make nir default

v2: allow for non debug builds as well v3: move reading out env var more global disable tg4 with multiple offsets with nir disable caps for 64 bit types v6: nv50 support disable MS images disable bindless textures Signed-off-by: Karol Herbst ---

[Mesa-dev] [Bug 77449] Tracker bug for all bugs related to Steam titles

https://bugs.freedesktop.org/show_bug.cgi?id=77449 Bug 77449 depends on bug 99813, which changed state. Bug 99813 Summary: F1 2015 rendering broken at medium quality https://bugs.freedesktop.org/show_bug.cgi?id=99813 What|Removed |Added

Re: [Mesa-dev] [PATCH v2 1/2] r600: correct texture offset for array index lookup

Am Freitag, den 29.06.2018, 17:42 +0200 schrieb Roland Scheidegger: [...] Thanks for the review > > So for gather4_O (where you'd need to do it differently) it must not > be > done, but for gather4 it has to be done? > Still doesn't make all that much sense to me. The hw may be weird but > I

Re: [Mesa-dev] [ANNOUNCE] mesa 18.1.3

On Fri, Jun 29, 2018 at 2:00 PM, Dylan Baker wrote: > Hi List, > > Mesa 18.1.3 is now available. This is a bug fix point release in the 18.1 > series. > > In this release we have: > - numerous fixes for radv > - some fixes for common radeon code > - several meson fixes > - fixes for autotools

[Mesa-dev] [Bug 106842] Error de prueba

https://bugs.freedesktop.org/show_bug.cgi?id=106842 Andre Klapper changed: What|Removed |Added Component|Demos |Two QA

Re: [Mesa-dev] [PATCH v3 4/4] gallium/llvmpipe: Enable support bptc format.

For the series: Reviewed-by: Marek Olšák Marek On Tue, Jun 26, 2018 at 4:30 PM, Denis Pauk wrote: > v2: none > v3: none > > Signed-off-by: Denis Pauk > CC: Marek Olšák > CC: Rhys Perry > CC: Matt Turner > --- > src/gallium/drivers/llvmpipe/lp_screen.c | 3 +-- >

Re: [Mesa-dev] [PATCH v2 3/3] st/mesa: Also check for PIPE_FORMAT_A8R8G8B8_SRGB for texture_sRGB

For the series: Reviewed-by: Marek Olšák Marek On Fri, Jun 22, 2018 at 9:59 AM, Tomeu Vizoso wrote: > and PIPE_FORMAT_R8G8B8A8_SRGB, as well. > > The reason for this is that when Virgl runs with GLES on the host, it > cannot directly upload textures in BGRA. > > So to avoid a conversion step,

Re: [Mesa-dev] [PATCH v2 2/3] st/mesa: Fall back to R8G8B8A8_SRGB for ETC2

On Fri, Jun 22, 2018 at 9:59 AM, Tomeu Vizoso wrote: > If the driver doesn't support PIPE_FORMAT_B8G8R8A8_SRGB, fall back to > PIPE_FORMAT_R8G8B8A8_SRGB. > > Drivers such as Virgl will have a hard time supporting > PIPE_FORMAT_B8G8R8A8_SRGB when the host runs GLES, as GL_ABGR isn't as > well

Re: [Mesa-dev] [PATCH] i965: fix typo (wrong gen number) in comment

On Friday, June 29, 2018 11:39:34 AM PDT Caio Marcelo de Oliveira Filho wrote: > --- > src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c >

[Mesa-dev] [PATCH 6/6] anv, intel: Enable nir_opt_large_constants for Vulkan

According to RenderDoc, this shaves 99.6% of the run time off of the ambient occlusion pass in Skyrim Special Edition when running under DXVK and shaves 92% off the runtime for a reasonably representative frame. When running the actual game, Skyrim goes from being a slide-show to a very stable and

[Mesa-dev] [PATCH 5/6] anv: Add state setup support for shader constants

--- .../vulkan/anv_nir_apply_pipeline_layout.c| 47 src/intel/vulkan/anv_private.h| 1 + src/intel/vulkan/genX_cmd_buffer.c| 72 ++- 3 files changed, 101 insertions(+), 19 deletions(-) diff --git

[Mesa-dev] [PATCH 3/6] nir: Add a large constants optimization pass

This pass searches for reasonably large local variables which can be statically proven to be constant and moves them into shader constant data. This is especially useful when large tables are baked into the shader source code because they can be moved into a UBO by the driver to reduce register

[Mesa-dev] [PATCH 4/6] anv: Add support for shader constant data to the pipeline cache

--- src/intel/vulkan/anv_blorp.c | 1 + src/intel/vulkan/anv_pipeline.c | 12 src/intel/vulkan/anv_pipeline_cache.c | 26 ++ src/intel/vulkan/anv_private.h| 6 ++ 4 files changed, 45 insertions(+) diff --git

[Mesa-dev] [PATCH 1/6] nir: Add a deref_instr_has_indirect helper

--- src/compiler/nir/nir.h | 2 ++ src/compiler/nir/nir_deref.c | 18 ++ 2 files changed, 20 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index c16ce547642..e35bef612df 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -987,6

[Mesa-dev] [PATCH 2/6] nir: Add a concept of constant data associated with a shader

This commit adds a concept to NIR of having a blob of constant data associated with a shader. Instead of being a UBO or uniform that can be manipulated by the client, this constant data considered part of the shader and remains constant across all invocations of the given shader until the end of

[Mesa-dev] [PATCH 0/6] anv,nir: Move large constants to a UBO

This little series adds an optimization pass to NIR and wires up up in anv that moves large constant variables to a UBO. This fixes a farily common case in some filter or ambient occlusion shaders where they put some sort of look-up table in the shader itself. This series takes Skyrim Special

Re: [Mesa-dev] [PATCH] gallium/u_vbuf: drop min/max-scanning for empty indirect draws

Reviewed-by: Marek Olšák Marek On Thu, Jun 28, 2018 at 9:22 AM, Erik Faye-Lund wrote: > When building with asserts enabled, we'll end up triggering an assert > in pipe_buffer_map_range down this code-path, due to trying to map > an empty range. Even if we avoid that, we'll trigger another

Re: [Mesa-dev] [PATCH v2 14/18] mesa: add compat profile support for ARB_multi_draw_indirect

Reviewed-by: Marek Olšák Marek On Fri, Jun 29, 2018 at 5:23 AM, Timothy Arceri wrote: > v2: add missing ARB_base_instance support > --- > src/mesa/main/extensions_table.h | 2 +- > src/mesa/vbo/vbo_exec_array.c| 77 +++- > 2 files changed, 76 insertions(+), 3

Re: [Mesa-dev] [PATCH v2 12/18] mesa: add ARB_draw_indirect support to compat profile

Reviewed-by: Marek Olšák Marek On Fri, Jun 29, 2018 at 5:22 AM, Timothy Arceri wrote: > v2: add missing ARB_base_instance support > --- > src/mesa/main/bufferobj.c| 3 +- > src/mesa/main/extensions_table.h | 2 +- > src/mesa/vbo/vbo_exec_array.c| 71

[Mesa-dev] [PATCH] i965: fix typo (wrong gen number) in comment

--- src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index b279f01e1a1..921b420ab81 100644 ---

[Mesa-dev] [ANNOUNCE] mesa 18.1.3

Hi List, Mesa 18.1.3 is now available. This is a bug fix point release in the 18.1 series. In this release we have: - numerous fixes for radv - some fixes for common radeon code - several meson fixes - fixes for autotools with non-gnu grep - fixes for both the nir and glsl compilers - An

[Mesa-dev] [PATCH 1/2] mesa: MESA_framebuffer_flip_y extension [v3]

Adds an extension to glFramebufferParameteri that will specify if the framebuffer is vertically flipped. Historically system framebuffers are vertically flipped and user framebuffers are not. Checking to see the state was done by looking at the name field. This adds an explicit field. v2: *

Re: [Mesa-dev] [PATCH 08/11] radeonsi: fix memory exhaustion issue with DCC statistics gathering with DRI2

Quoting Marek Olšák (2018-06-29 09:48:08) > On Fri, Jun 29, 2018 at 11:40 AM, Dylan Baker wrote: > > Quoting Marek Olšák (2018-06-18 16:33:09) > >> From: Marek Olšák > >> > >> Cc: 18.1 > >> --- > >> src/gallium/drivers/radeonsi/si_blit.c | 30 +++--- > >> 1 file changed, 27

Re: [Mesa-dev] [PATCH 08/11] radeonsi: fix memory exhaustion issue with DCC statistics gathering with DRI2

On Fri, Jun 29, 2018 at 11:40 AM, Dylan Baker wrote: > Quoting Marek Olšák (2018-06-18 16:33:09) >> From: Marek Olšák >> >> Cc: 18.1 >> --- >> src/gallium/drivers/radeonsi/si_blit.c | 30 +++--- >> 1 file changed, 27 insertions(+), 3 deletions(-) >> >> diff --git

Re: [Mesa-dev] [PATCH 1/2] mesa: MESA_framebuffer_flip_y extension [v2]

On Fri, Jun 29, 2018 at 1:50 AM Erik Faye-Lund wrote: > > On Thu, Jun 28, 2018 at 11:12 PM Fritz Koenig wrote: > > > > Adds an extension to glFramebufferParameteri > > that will specify if the framebuffer is vertically > > flipped. Historically system framebuffers are > > vertically flipped and

Re: [Mesa-dev] [PATCH v2 2/2] r600: set rounding mode for texture array layer selection

Am 29.06.2018 um 16:35 schrieb Gert Wollny: > The evaluation of the array layer index is "floor(z+0.5)", and the default > rounding mode doesn't correctly evaluate this. Therefore, set the rounding > mode to "trunc" and z-filter mode to "point". > For other textures make sure the the default

Re: [Mesa-dev] [PATCH v2 1/2] r600: correct texture offset for array index lookup

Am 29.06.2018 um 16:35 schrieb Gert Wollny: > For texture array lookup the slice index is evaluated according to > idx = floor(z + 0.5) > > This patch implements the first part by adding 0.5 to the according > texture coordinate when appropriate. > > Fixes multi-sample tests out of: >

Re: [Mesa-dev] [PATCH 08/11] radeonsi: fix memory exhaustion issue with DCC statistics gathering with DRI2

Quoting Marek Olšák (2018-06-18 16:33:09) > From: Marek Olšák > > Cc: 18.1 > --- > src/gallium/drivers/radeonsi/si_blit.c | 30 +++--- > 1 file changed, 27 insertions(+), 3 deletions(-) > > diff --git a/src/gallium/drivers/radeonsi/si_blit.c >

Re: [Mesa-dev] [PATCH 32/53] intel/fs: Mark LINTERP opcode as writing accumulator implicitly on pre-Gen7.

Quoting Jason Ekstrand (2018-05-24 14:56:14) > From: Francisco Jerez > > --- > src/intel/compiler/brw_shader.cpp | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/src/intel/compiler/brw_shader.cpp > b/src/intel/compiler/brw_shader.cpp > index 141b64e..61211ef 100644 >

[Mesa-dev] [PATCH v2 2/2] r600: set rounding mode for texture array layer selection

The evaluation of the array layer index is "floor(z+0.5)", and the default rounding mode doesn't correctly evaluate this. Therefore, set the rounding mode to "trunc" and z-filter mode to "point". For other textures make sure the the default rounding mode and z-filter are used. Fixes single-sample

[Mesa-dev] [PATCH v2 1/2] r600: correct texture offset for array index lookup

For texture array lookup the slice index is evaluated according to idx = floor(z + 0.5) This patch implements the first part by adding 0.5 to the according texture coordinate when appropriate. Fixes multi-sample tests out of: dEQP-GLES3.functional.texture.shadow.2d_array.*

[Mesa-dev] [PATCH v2 0/2] r600: Fix array texture slice index evaluation

I reworded parts of the comments, and simplified the patch against the shader to correct the piglit failures and taking into account that a shader can not set an offset for the array index at all. Apart from the dEQP tests I've run ./piglit run gpu -t texture with no changes. (I always got

Re: [Mesa-dev] [PATCH v2] nv50/ir: improve maintainability of Target*::initOpInfo()

Reviewed-by: Ilia Mirkin On Fri, Jun 29, 2018 at 9:51 AM, Rhys Perry wrote: > This is mainly useful for when one needs to add new opcodes in a painless > and reliable way. > > Signed-off-by: Rhys Perry > --- > Changes in v2: > - use operation instead of uint32_t > - use ARRAY_SIZE() > - add

[Mesa-dev] [PATCH 03/18] nir/linker: use empty block info to assign uniform locations

For the cases of uniforms that doesn't have an explicit location. Under ARB_gl_spirv those are exceptions, like uniform atomic counters. --- src/compiler/glsl/gl_nir_link_uniforms.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git

[Mesa-dev] [PATCH 01/18] nir/linker: handle uniforms without explicit location

ARB_gl_spirv points that uniforms in general need explicit location. But there are still some cases of uniforms without location, like for example uniform atomic counters. Those doesn't have a location from the OpenGL point of view (they are identified with a binding), but Mesa internally assigns

[Mesa-dev] [PATCH 07/18] spirv/nir: tweak nir type when storage class is SpvStorageClassAtomicCounter

GLSL types differentiates uint from atomic uint. On SPIR-V the type is uint, and the variable has a specific storage class. So we need to tweak the type based on the storage class. Ideally we would like to get the proper type at vtn_handle_type, but we don't have the storage class at that moment.

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