Makes sense, sorry I missed this one;
Reviewed-by: Tapani Pälli
On 3/11/19 7:33 PM, Juan A. Suarez Romero wrote:
As stated in Vulkan spec:
"Resetting a descriptor pool recycles all of the resources from all
of the descriptor sets allocated from the descriptor pool back to
the
> The first patch was fine. Just not the second.
First patch is a duplicate of the linked patch.
___
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
On March 11, 2019 22:17:38 Alyssa Rosenzweig wrote:
[1] https://patchwork.freedesktop.org/patch/291616/
Ah-ha, somebody who knows what they're doing. That's good; ignore this
series then :)
The first patch was fine. Just not the second.
---
So is this a "no" for the deleting
> [1] https://patchwork.freedesktop.org/patch/291616/
Ah-ha, somebody who knows what they're doing. That's good; ignore this
series then :)
---
So is this a "no" for the deleting ~/mesa/src idea?
___
mesa-dev mailing list
On 12/3/19 2:09 pm, Alyssa Rosenzweig wrote:
A better fix might be to delete the Mesa src tree, that should fix up any
warnings :P
Huh, so it does!
No regressions on dEQP, possibly since all the tests were failing to
begin with on Panfrost.
I can only assume this was sent out by mistake?
> A better fix might be to delete the Mesa src tree, that should fix up any
> warnings :P
Huh, so it does!
No regressions on dEQP, possibly since all the tests were failing to
begin with on Panfrost.
> I can only assume this was sent out by mistake?
This was sent out by "I don't know what I'm
On 12/3/19 1:50 pm, Brian Paul wrote:
Thanks, but it looks like Alyssa's patches may be better.
-Brian
The second patch looks really wrong. Seems like a mistake to me.
On 03/11/2019 08:33 PM, Timothy Arceri wrote:
Thanks
Reviewed-by: Timothy Arceri
On 12/3/19 1:12 pm, Brian Paul wrote:
On 12/3/19 1:30 pm, Alyssa Rosenzweig wrote:
Fixes a gcc warning.
Signed-off-by: Alyssa Rosenzweig
---
src/compiler/nir/nir_opt_loop_unroll.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/compiler/nir/nir_opt_loop_unroll.c
b/src/compiler/nir/nir_opt_loop_unroll.c
index
Thanks, but it looks like Alyssa's patches may be better.
-Brian
On 03/11/2019 08:33 PM, Timothy Arceri wrote:
Thanks
Reviewed-by: Timothy Arceri
On 12/3/19 1:12 pm, Brian Paul wrote:
[33/630] Compiling C object
'src/compiler/nir/nir@sta/nir_loop_analyze.c.o'.
This patch is
Reviewed-by: Jason Ekstrand
On March 11, 2019 21:31:03 Alyssa Rosenzweig wrote:
Fixes a gcc warning (and a theoretical NULL dereference error, though I
suppose shortcircuiting avoids that).
Signed-off-by: Alyssa Rosenzweig
---
src/compiler/nir/nir_loop_analyze.c | 2 +-
1
Thanks
Reviewed-by: Timothy Arceri
On 12/3/19 1:12 pm, Brian Paul wrote:
[33/630] Compiling C object 'src/compiler/nir/nir@sta/nir_loop_analyze.c.o'.
../src/compiler/nir/nir_loop_analyze.c: In function
‘try_find_trip_count_vars_in_iand’:
../src/compiler/nir/nir_loop_analyze.c:846:29:
Fixes a gcc warning.
Signed-off-by: Alyssa Rosenzweig
---
src/compiler/nir/nir_opt_loop_unroll.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/compiler/nir/nir_opt_loop_unroll.c
b/src/compiler/nir/nir_opt_loop_unroll.c
index 9ab0a924c82..41f7a834164 100644
---
Fixes a gcc warning (and a theoretical NULL dereference error, though I
suppose shortcircuiting avoids that).
Signed-off-by: Alyssa Rosenzweig
---
src/compiler/nir/nir_loop_analyze.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_loop_analyze.c
[33/630] Compiling C object 'src/compiler/nir/nir@sta/nir_loop_analyze.c.o'.
../src/compiler/nir/nir_loop_analyze.c: In function
‘try_find_trip_count_vars_in_iand’:
../src/compiler/nir/nir_loop_analyze.c:846:29: warning: suggest parentheses
around ‘&&’ within ‘||’ [-Wparentheses]
if (*ind ==
---
docs/meson.html | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/docs/meson.html b/docs/meson.html
index 09b45be..08e4d1a 100644
--- a/docs/meson.html
+++ b/docs/meson.html
@@ -103,7 +103,8 @@ running "meson build/" but this feature is being discussed
upstream.
For now,
Split up the "Environment Variables" section into "Compiler Options"
and "Compiler Specification". I think this makes the information
easier to find and understand.
---
docs/meson.html | 58 ++---
1 file changed, 39 insertions(+), 19
pushed.
On Mon, Mar 11, 2019 at 3:15 PM Clayton Craft
wrote:
> On Mon, Mar 11, 2019 at 06:33:54PM +0100, Juan A. Suarez Romero wrote:
> >As stated in Vulkan spec:
> > "Resetting a descriptor pool recycles all of the resources from all
> >of the descriptor sets allocated from the
On 03/11/2019 04:47 PM, Eric Anholt wrote:
Brian Paul writes:
Since the compiler may not zero-out padding in the object.
Add a couple comments about this to prevent misunderstandings in
the future.
Fixes: 67d96816ff5 ("st/mesa: move, clean-up shader variant key decls/inits")
---
https://bugs.freedesktop.org/show_bug.cgi?id=109641
--- Comment #1 from Brian Paul ---
I believe this recent patch should help:
commit b344e32cdf7064a1f2ff7ef37027edda6589404f
Author: Ray Zhang
Date: Wed Feb 27 06:54:05 2019 +
glx: fix shared memory leak in X11
call XShmDetach
On Mon, Mar 11, 2019 at 8:18 PM Karol Herbst wrote:
>
> On Tue, Mar 12, 2019 at 1:09 AM Ilia Mirkin wrote:
> >
> > On Mon, Mar 11, 2019 at 8:05 PM Karol Herbst wrote:
> > >
> > > v9: convert to C++ style comments
> > > Signed-off-by: Karol Herbst
> > > ---
> > >
To all X.Org Foundation Members:
The election for the X.Org Foundation Board of Directors will begin on 14 March
2019. We have 6 candidates who are running for 4 seats. They are (in
alphabetical order):
Samuel Iglesias Gonsálvez
Arkadiusz Hiler
Manasi Navare
Lyude Paul
Daniel Vetter
Trevor
On Tue, Mar 12, 2019 at 1:09 AM Ilia Mirkin wrote:
>
> On Mon, Mar 11, 2019 at 8:05 PM Karol Herbst wrote:
> >
> > v9: convert to C++ style comments
> > Signed-off-by: Karol Herbst
> > ---
> > src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 6 +-
> > 1 file changed, 5
On Mon, Mar 11, 2019 at 8:05 PM Karol Herbst wrote:
>
> v9: convert to C++ style comments
> Signed-off-by: Karol Herbst
> ---
> src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git
v3: add workaround for RA issues
indirects have to be multiplied by 0x10
fix indirect access
v4: use smarter getIndirect helper
use storeTo helper
v5: don't use const_offset directly
v8: don't require C++11 features
v9: convert to C++ style comments
handle clip planes correctly
v7: don't assert in default case for getSubOp
Signed-off-by: Karol Herbst
Reviewed-by: Pierre Moreau
---
.../nouveau/codegen/nv50_ir_from_nir.cpp | 22 +++
1 file changed, 22 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
v2: support more sys values
fixed a bug where for multi component reads all values ended up in x
v3: add load_patch_vertices_in
v4: add subgroup stuff
v5: add helper invocation
v6: fix loading 64 bit system values
v8: don't require C++11 features
v9: convert to C++ style comments
v3: fix compiler warnings
v4: use loadFrom helper
v5: fix signed min/max
v6: set tex mask
add support for indirect image access
set cache mode
v7: make compatible with 884d27bcf688d36c3bbe01bceca525595add3b33
rework the whole deref thing to prepare for bindless
v8: port to deref
Signed-off-by: Karol Herbst
---
.../nouveau/codegen/nv50_ir_from_nir.cpp | 59 +--
1 file changed, 41 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index
v2: parse a few more fields
v3: add special handling for GL_ISOLINES
v8: set info->prop.fp.readsSampleLocations
don't require C++11 features
v9: replace '(*it).' with 'it->'
convert to C++ style comments
Signed-off-by: Karol Herbst
---
.../nouveau/codegen/nv50_ir_from_nir.cpp | 323
v9: mark as fixed
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index
We store those arrays in local memory and reserve some space for each of the
arrays. With NIR we could store those arrays packed, but we don't do that yet
as it causes MemoryOpt to generate unaligned memory accesses.
v3: use fixed size vec4 arrays until we fix MemoryOpt
v4: fix for 64 bit types
v2: add vote_eq support
use the new subop intrinsic helper
add ballot
v3: add read_(first_)invocation
v8: handle vectorized intrinsics
don't require C++11 features
v9: lower_subgroups to 32 bit (produces less instructions)
use getSSA and getScratch instead of new_LValue
v4: use smarter getIndirect helper
use new getSlotAddress helper
use loadFrom helper
v8: don't require C++11 features
Signed-off-by: Karol Herbst
---
.../nouveau/codegen/nv50_ir_from_nir.cpp | 27 +++
1 file changed, 27 insertions(+)
diff --git
v2: use mkOp
v8: don't require C++11 features
Signed-off-by: Karol Herbst
Reviewed-by: Pierre Moreau
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp| 13 +
1 file changed, 13 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
v8: fix loading 8/16 bit constants
Signed-off-by: Karol Herbst
Reviewed-by: Pierre Moreau
---
.../nouveau/codegen/nv50_ir_from_nir.cpp | 28 +++
1 file changed, 28 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
a lot of those fields are not valid for a lot of tex ops. Not quite sure if
it's worth the effort to check for those or just keep it like that. It seems
to kind of work.
v2: reworked offset handling
add tex support with indirect R/S arguments
handle GLSL_SAMPLER_DIM_EXTERNAL
drop
v4: treat imul as unsigned
v5: remove pointless !!
v7: inot is unsigned as well
v8: don't require C++11 features
v9: convert to C++ style comments
improve formatting
print error in all cases where codegen doesn't support a given type
Signed-off-by: Karol Herbst
Acked-by: Pierre Moreau
v9: use getSSA instead of new_LValue
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
v3: and load_output
v4: use smarter getIndirect helper
use new getSlotAddress helper
v5: don't use const_offset directly
fix for indirects
v6: add support for interpolateAt
v7: fix compiler warnings
add load_barycentric_sample
handle load_output for fragment shaders
v8: set
v2: use new getIndirect helper
fixes symbols for 64 bit types
v4: use smarter getIndirect helper
simplify address calculation
use loadFrom helper
v8: don't require C++11 features
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 10 ++
Signed-off-by: Karol Herbst
Reviewed-by: Pierre Moreau
---
.../nouveau/codegen/nv50_ir_from_nir.cpp| 17 +
1 file changed, 17 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
v5: add more barrier intrinsics
Signed-off-by: Karol Herbst
---
.../nouveau/codegen/nv50_ir_from_nir.cpp | 21 +++
1 file changed, 21 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
v9: convert to C++ style comments
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
v4: use loadFrom helper
v5: support indirect buffer access
v8: don't require C++11 features
Signed-off-by: Karol Herbst
---
.../nouveau/codegen/nv50_ir_from_nir.cpp | 90 +++
1 file changed, 90 insertions(+)
diff --git
v8: don't require C++11 features
Signed-off-by: Karol Herbst
---
.../nouveau/codegen/nv50_ir_from_nir.cpp | 72 +++
1 file changed, 72 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
v2: user bitfield_insert instead of bfi
rework switch helper macros
remove some lowering code (LoweringHelper is now used for this)
v3: add pack_half_2x16_split
add unpack_half_2x16_split_x/y
v5: replace first argument with nullptr in loadImm calls
prefer getSSA over getScratch
v8:
v2: add support for geometry shaders
set idx
add some missing mappings
fix for 64bit inputs/outputs
fix up some FP color output index messup
parse centroid flag
v3: fix arrays in outputs as well
fix input/ouput size calculation for tessellation shaders
v4: add
v4: use loadFrom helper
v8: don't require C++11 features
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
v4: use smarter getIndirect helper
use new getSlotAddress helper
v5: use loadFrom helper
v8: don't require C++11 features
Signed-off-by: Karol Herbst
---
.../nouveau/codegen/nv50_ir_from_nir.cpp | 23 +++
1 file changed, 23 insertions(+)
diff --git
this makes debugging the shader header a little easier
Acked-by: Pierre Moreau
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
v9: rename variable to driver_flags
use constants for shader cache flags
Signed-off-by: Karol Herbst
Reviewed-by: Pierre Moreau
---
src/gallium/drivers/nouveau/nouveau_screen.c | 8 +++-
src/gallium/drivers/nouveau/nouveau_screen.h | 3 +++
2 files changed, 10 insertions(+), 1
v2: add constant_folding
v6: print non final NIR only for verbose debugging
v8: add passes we will need for OpenCL compute shaders
v9: move type_size into anonymous namespace
convert to C++ style comments
lower bools to int32
Signed-off-by: Karol Herbst
Acked-by: Pierre Moreau
---
v2: add helper function for indirects
v4: add new getIndirect overload for easier use
v5: use getSSA for ssa values
we can just create the values for unassigned registers in getSrc
v6: always create at least 32 bit values
v8: don't require C++11 features
v9: include unordered_map on supported
not all those nir options are actually required, it just made the work a
little easier.
v2: fix asserts
parse compute shaders
don't lower bitfield_insert
v3: fix memory leak
v4: don't lower fmod32
v5: set lower_all_io_to_temps to false
fix memory leak because we take over ownership of
if we start supporting multiple input IRs we might want to move lowering code
into a common place and keep the initial translation simplier.
This will also allows us to react on ISA changes more easily.
v5: also handle SAT
v6: rename type variables
fixed lowering of NEG
add lowering of
Point size is a single component value and drivers might write the full vec4
potentially overwriting other values.
Signed-off-by: Karol Herbst
---
src/mesa/program/prog_to_nir.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/program/prog_to_nir.c
v2: remove TGSI related bits
Signed-off-by: Karol Herbst
Reviewed-by: Pierre Moreau
---
src/gallium/drivers/nouveau/Makefile.sources | 2 +
.../nouveau/codegen/nv50_ir_from_common.cpp | 107 ++
.../nouveau/codegen/nv50_ir_from_common.h | 58 ++
I think I will just go ahead and merge it over the next few days.
There are more patches to fix some crashes related to 64 bit types, but that is
touching current RA code and I would like to have better testing there.
So some piglit regressions, most related to 64 bit types though covered by the
Brian Paul writes:
> Since the compiler may not zero-out padding in the object.
> Add a couple comments about this to prevent misunderstandings in
> the future.
>
> Fixes: 67d96816ff5 ("st/mesa: move, clean-up shader variant key decls/inits")
> ---
> src/mesa/state_tracker/st_atom_shader.c | 9
r-b
On Mon, Mar 11, 2019 at 10:23 AM Samuel Pitoiset
wrote:
>
> The values should match the ones that are emitted.
>
> This fixes new CTS dEQP-VK.rasterization.primitive_size.points.*.
>
> Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
> Signed-off-by: Samuel Pitoiset
On Mon, 2019-03-11 at 17:04 +0200, Eleni Maria Stea wrote:
> The VkPhysicalDeviceSampleLocationPropertiesEXT struct is filled with
> implementation dependent values and according to the table from the
> Vulkan Specification section [36.1. Limit Requirements]:
>
> pname | max | min
>
On Mon, 2019-03-11 at 17:04 +0200, Eleni Maria Stea wrote:
> The VkPhysicalDeviceSampleLocationPropertiesEXT struct is filled with
> implementation dependent values and according to the table from the
> Vulkan Specification section [36.1. Limit Requirements]:
>
> pname | max | min
>
https://bugs.freedesktop.org/show_bug.cgi?id=109939
--- Comment #15 from Timur Kristóf ---
Will attach the contents of the preferences folder next time I encounter this
problem.
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the
Build mesa 10355 completed
Commit 3a9e2d6085 by Eric Anholt on 2/28/2019 8:02 PM:
vc4: Switch the post-RA scheduler over to the DAG datastructure.\n\nJust a small code reduction from shared infrastructure.
Configure your notification preferences
On Mon, Mar 11, 2019 at 06:33:54PM +0100, Juan A. Suarez Romero wrote:
As stated in Vulkan spec:
"Resetting a descriptor pool recycles all of the resources from all
of the descriptor sets allocated from the descriptor pool back to
the descriptor pool, and the descriptor sets are
https://bugs.freedesktop.org/show_bug.cgi?id=109939
--- Comment #14 from mikhail.v.gavri...@gmail.com ---
Alex, I am attach "Rise of the Tomb Raider" archive here.
For reproducing problem after continue the game.
Try fast travel to locations: "The Gulag" and "Valley Farmstead"
--
You are
https://bugs.freedesktop.org/show_bug.cgi?id=109939
--- Comment #13 from mikhail.v.gavri...@gmail.com ---
Created attachment 143627
--> https://bugs.freedesktop.org/attachment.cgi?id=143627=edit
Rise of the Tomb Raider
--
You are receiving this mail because:
You are the QA Contact for the
Build mesa 10354 failed
Commit 5f0a922c27 by Kristian H. Kristensen on 3/1/2019 10:33 PM:
freedreno/a6xx: Remove extra parens\n\nThere's a warning about this now.\n\nSigned-off-by: Kristian H. Kristensen
Configure your notification preferences
Reviewed-by: Jason Ekstrand
On Mon, Mar 11, 2019 at 12:34 PM Juan A. Suarez Romero
wrote:
> As stated in Vulkan spec:
>"Resetting a descriptor pool recycles all of the resources from all
> of the descriptor sets allocated from the descriptor pool back to
> the descriptor pool, and
As stated in Vulkan spec:
"Resetting a descriptor pool recycles all of the resources from all
of the descriptor sets allocated from the descriptor pool back to
the descriptor pool, and the descriptor sets are implicitly freed."
This fixes dEQP-VK.api.descriptor_pool.*
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=109535
Dylan Baker changed:
What|Removed |Added
Depends on|109695 |
Referenced Bugs:
On 11/03/2019 15:04, Eleni Maria Stea wrote:
Enabled the VK_EXT_sample_locations for Intel Gen >= 7.
---
src/intel/vulkan/anv_extensions.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index
One more brick in the wall :)
Reviewed-by: Tomeu Vizoso
On Sun, 10 Mar 2019 at 07:50, Alyssa Rosenzweig wrote:
>
> The fragment_extra structure contains additional fields extending the
> MRT framebuffer descriptor, snuck in between the main framebuffer
> descriptor and the render targets. Its
Enabled the VK_EXT_sample_locations for Intel Gen >= 7.
---
src/intel/vulkan/anv_extensions.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index 9e4e03e46df..99007544732 100644
---
In src/intel/vulkan/genX_blorp_exec.c we included the file:
common/gen_sample_positions.h but not use it. Removed.
---
src/intel/vulkan/genX_blorp_exec.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/intel/vulkan/genX_blorp_exec.c
b/src/intel/vulkan/genX_blorp_exec.c
index
We only emit sample locations when the extension is enabled by the user.
In all other cases the default locations are emitted once when the device
is initialized to increase performance.
---
src/intel/vulkan/anv_genX.h| 3 ++-
src/intel/vulkan/genX_cmd_buffer.c | 2 +-
Implemented the vkGetPhysicalDeviceMultisamplePropertiesEXT according to
the Vulkan Specification section [36.2. Additional Multisampling
Capabilities].
---
src/intel/Makefile.sources | 1 +
src/intel/vulkan/anv_sample_locations.c | 60 +
Allowing setting dynamic and non-dynamic sample locations on Gen7.
---
src/intel/vulkan/anv_genX.h| 13 ++---
src/intel/vulkan/genX_cmd_buffer.c | 9 ++--
src/intel/vulkan/genX_pipeline.c | 13 +
src/intel/vulkan/genX_state.c | 86 +-
4 files
Added the VK_EXT_sample_locations to the anv_extensions.py list to
generate the related entrypoints.
---
src/intel/vulkan/anv_extensions.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index 6fff293dee4..9e4e03e46df
Added support for setting the locations when the pipeline has been
created with the dynamic state bit enabled according to the Vulkan
Specification section [26.5. Custom Sample Locations] for the function:
'vkCmdSetSampleLocationsEXT'
The reason that we preferred to store the boolean valid
Allowing the user to set custom sample locations non-dynamically, by
filling the extension structs and chaining them to the pipeline structs
according to the Vulkan specification section [26.5. Custom Sample Locations]
for the following structures:
'VkPipelineSampleLocationsStateCreateInfoEXT'
The VkPhysicalDeviceSampleLocationPropertiesEXT struct is filled with
implementation dependent values and according to the table from the
Vulkan Specification section [36.1. Limit Requirements]:
pname | max | min
pname:sampleLocationSampleCounts |-|ename:VK_SAMPLE_COUNT_4_BIT
> If I comment the line immediately above, things work as expected.
Interesting, okay, this is definitely a regression on kbase too. I'll
investigate this evening -- I think I need to be checking the depth mask
before setting this bit..?
___
mesa-dev
> Can we use a constant instead?
The right solution is to actually RE the format bits for SFBD (which
will be necessary if we're serious about supporting https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> I'm pretty sure it will be obsolete in only 240 years too. :)
Ecclesiastes 1:9, alas :P
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Reviewed-by: Tomeu Vizoso
On Sun, 10 Mar 2019 at 07:50, Alyssa Rosenzweig wrote:
>
> This combination has not yet been seen "in the wild" in traces, but to
> support linear depth FBOs, ~bruteforce reveals this bit pattern is
> necessary. It's not yet clear why the meanings of 0x1 and 0x2 are
>
Reviewed-by: Tomeu Vizoso
On Sun, 10 Mar 2019 at 07:50, Alyssa Rosenzweig wrote:
>
> Previously, linear BOs shared memory with each other to minimize kernel
> round-trips / latency, as well as to work around a bug in the free_slab
> function. These concerns are invalid now, but continuing to
Hi guys,
When doing rebase from 18.3 to master branch, I found nir_intrinsic_load_uniform
use float const_offset now. But most gallium drivers still treat it as
int except
freedreno.
I don't know which commit did this, is this expected?
Regards,
Qiang
On Fri, Mar 8, 2019 at 3:59 PM Alyssa Rosenzweig wrote:
>
> > +/**
> > + * struct drm_panfrost_wait_bo - ioctl argument for waiting for
> > + * completion of the last DRM_PANFROST_SUBMIT_CL on a BO.
>
> Nit: Should be plain DRM_PANFROST_SUBMIT, there is no CL for us.
>
> > + __s64 timeout_ns;
https://bugs.freedesktop.org/show_bug.cgi?id=109939
--- Comment #12 from Alex Smith ---
Sounds like this is potentially a game issue.
Could both of you zip up the contents of the preferences folder
("~/.local/share/feral-interactive/Rise of the Tomb Raider") once you're
getting the issue, and
On Sun, 10 Mar 2019 at 07:50, Alyssa Rosenzweig wrote:
>
> With a unified layout field, we can specify the logic for BO layout
> explicitly, deciding between linear/tiled/AFBC based on the specified
> usage/binding flags.
>
> Signed-off-by: Alyssa Rosenzweig
Great stuff!
Reviewed-by: Tomeu
On Sun, 10 Mar 2019 at 07:50, Alyssa Rosenzweig wrote:
>
> Again, these formats are only properly known at the time of fragment job
> emit. Rather than hardcoding the format, at least for MFBD we begin to
> construct the format bits on-demand. This cleans up the code,
> futureproofs for ES3
On Sun, 10 Mar 2019 at 07:50, Alyssa Rosenzweig wrote:
>
> This emit is only implemented for AFBC depth/stencil buffers, so
> conceptually there is no change here, but we follow the style of the
> previous patch to improve robustness and clarity.
>
> Signed-off-by: Alyssa Rosenzweig
> ---
>
Reviewed-by: Tomeu Vizoso
On Sun, 10 Mar 2019 at 07:50, Alyssa Rosenzweig wrote:
>
> In an effort to cleanup framebuffer management code, we delay
> colour buffer setup until the FRAGMENT job is actually emitted, allowing
> the AFBC and linear codepaths to be unified.
>
> Signed-off-by: Alyssa
On Sun, 10 Mar 2019 at 07:50, Alyssa Rosenzweig wrote:
>
> AFBC, tiled, and linear BO layouts are mutually exclusive; they should
> be coupled via a single enum rather than ad hoc checks of booleans.
>
> Signed-off-by: Alyssa Rosenzweig
Reviewed-by: Tomeu Vizoso
> ---
>
On Sun, 10 Mar 2019 at 07:50, Alyssa Rosenzweig wrote:
>
> I'm not sure why we were checking for these additional criteria (likely
> inherited from some other driver); remove the needless checks to cleanup
> the code and perhaps fix some bugs down the line.
>
> Signed-off-by: Alyssa Rosenzweig
https://bugs.freedesktop.org/show_bug.cgi?id=109958
--- Comment #1 from joney ---
After searching a little bit more I just found
https://bugs.freedesktop.org/show_bug.cgi?id=109641 which looks like it might
be the same issue.
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You are receiving this mail because:
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Signed-off-by: Tomeu Vizoso
---
src/gallium/drivers/panfrost/pan_drm.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/panfrost/pan_drm.c
b/src/gallium/drivers/panfrost/pan_drm.c
index 6d1129ff5f2b..62a7b0ce5a30 100644
---
Hi,
I needed the below two patches to avoid regressions when testing this
series.
Thanks,
Tomeu
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Signed-off-by: Tomeu Vizoso
---
src/gallium/drivers/panfrost/pan_resource.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/panfrost/pan_resource.c
b/src/gallium/drivers/panfrost/pan_resource.c
index 1a6769b5508e..e398b6f6b7ce 100644
---
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