[Mesa-dev] [PATCH] radv: fix memory leak when restoring from cache
Fixes: 726a31df705b ("radv: Add the concept of radv shader binaries.")
---
src/amd/vulkan/radv_pipeline_cache.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/amd/vulkan/radv_pipeline_cache.c
b/src/amd/vulkan/radv_pipeline_cache.c
index 2b3fda6eb8e..b773de30c32 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -309,6 +309,7 @@ radv_create_shader_variants_from_pipeline_cache(struct
radv_device *device,
p += entry->binary_sizes[i];
entry->variants[i] = radv_shader_variant_create(device,
binary);
+ free(binary);
} else if (entry->binary_sizes[i]) {
p += entry->binary_sizes[i];
}
--
2.21.0
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[Mesa-dev] [Bug 100789] Mesa (Padoka Pkppa), Textures become corrupt in counterstrike 1.6 and in steam overlay after indeterminate amount of time
https://bugs.freedesktop.org/show_bug.cgi?id=100789 --- Comment #10 from calexil --- you don't see the blocked single colors where textures should be, for example in de_nuke at the ramp the guide rail should be a metal lattice, not a solid red block -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: compute correct number of input vertices for NGG
On Tue, Jul 9, 2019 at 9:19 AM Samuel Pitoiset
wrote:
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_pipeline.c | 25 -
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index 5942e20dafe..96b20c1c730 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -1616,6 +1616,29 @@ static void clamp_gsprims_to_esverts(unsigned
> *max_gsprims, unsigned max_esverts
> *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
> }
>
> +static unsigned
> +radv_get_num_input_vertices(struct radv_pipeline *pipeline)
> +{
> + if (radv_pipeline_has_gs(pipeline)) {
> + struct radv_shader_variant *gs =
> + radv_get_shader(pipeline, MESA_SHADER_GEOMETRY);
> +
> + return gs->info.gs.vertices_in;
> + }
> +
> + if (radv_pipeline_has_tess(pipeline)) {
> + struct radv_shader_variant *tes = radv_get_shader(pipeline,
> MESA_SHADER_TESS_EVAL);
> +
> + if (tes->info.tes.point_mode)
> + return 1;
> + if (tes->info.tes.primitive_mode == GL_ISOLINES)
> + return 2;
> + return 3;
> + }
> +
> + return 3;
I think this should be based on
pCreateInfo->pInputAssemblyState->topology, instead of assuming 3.
However for consistency with radeonsi for now, this is r-b
> +}
> +
> static struct radv_ngg_state
> calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
>struct radv_pipeline *pipeline)
> @@ -1625,7 +1648,7 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo
> *pCreateInfo,
> struct radv_es_output_info *es_info =
> radv_pipeline_has_tess(pipeline) ? _info->tes.es_info :
> _info->vs.es_info;
> unsigned gs_type = radv_pipeline_has_gs(pipeline) ?
> MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
> - unsigned max_verts_per_prim = 3; // triangles
> + unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline);
> unsigned min_verts_per_prim =
> gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
> unsigned gs_num_invocations = gs_info ? MAX2(gs_info->gs.invocations,
> 1) : 1;
> --
> 2.22.0
>
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[Mesa-dev] [Bug 99240] glxinfo reports different extensions for wayland vs xorg.
https://bugs.freedesktop.org/show_bug.cgi?id=99240 Adam Jackson changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #3 from Adam Jackson --- Fixed in xserver (1.21, once that's out) by: commit 8469241592b94b002a975274a596ca0dcdd9563f Author: Adam Jackson Date: Wed May 8 14:09:00 2019 -0400 xwayland: Add EGL-backed GLX provider -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] egl/android: Update color_buffer[] querying for buffer age
color_buffers[] is currently hard coded to 3 for android which fails
in droid_window_dequeue_buffer when ANativeWindow creates 4 color_buffers
on ChromeOS while querying buffer age during dEQP partial_update tests.
Fixes dEQP-EGL.functional.partial_update* tests on chromebooks with
enabling EGL_KHR_partial_update.
v2: update comment instead of removing (Eric Engestrom)
Fixes: 2acc69da8ce "EGL/Android: Add EGL_EXT_buffer_age extension"
Signed-off-by: Nataraj Deshpande
Acked-by: Eric Engestrom
---
src/egl/drivers/dri2/egl_dri2.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 943ff18..24a37e0 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -322,13 +322,12 @@ struct dri2_egl_surface
__DRIimage *dri_image_front;
/* Used to record all the buffers created by ANativeWindow and their ages.
-* Usually Android uses at most triple buffers in ANativeWindow
-* so hardcode the number of color_buffers to 3.
+* Set number of color_buffers to 4 as applicable to Android/chromeOS.
*/
struct {
struct ANativeWindowBuffer *buffer;
int age;
- } color_buffers[3], *back;
+ } color_buffers[4], *back;
#endif
/* surfaceless and device */
--
2.7.4
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Re: [Mesa-dev] [MR] Update README to recommend MRs instead of `git send-email`
On Tue, Jul 9, 2019 at 11:19 AM Kristian Høgsberg wrote: > On Tue, Jul 9, 2019 at 12:17 AM Daniel Stone wrote: > > > > Hi, > > > > On Sat, 6 Jul 2019 at 18:39, Ilia Mirkin wrote: > > > I see this as driving away contributions, esp from new people. MR's > > > are annoying to create, since they require dealing with the hosting > > > provider, getting it to host clones, etc. Everyone has email. > > > > My position - and the evidence of velocity from projects who have > > switched - is already pretty clear, but you might be interested to > > read that even kernel.org admins are trying to move away from email: > > > https://people.kernel.org/monsieuricon/patches-carved-into-developer-sigchains > > I have the same experience - I've used git since before it was usable > and I'm more than happy to not have to worry about making git > send-email work. I'm pretty sure that gitlab in general lowers the bar > for contributions considerably, I know I find my self doing a lot more > reviews and drive-by comments because of how easy it feels I know I'm a gitlab fan-boy so you all know I like this. What I will say is that it's not only easier for new developers because PRs are a concept they already know from GitHub and the like but it's also easier for maintainers. I've actually started getting annoyed when people send patches to the list and I have to apply them from e-mail. It's so much easier to just check that they've added all the tags and click a couple buttons in the web UI than to have to find the thing on patchwork, download it, hope it applies, and push it. I also don't get why this is controversial. It's just a recommendation to new people coming in off the internet who want to contribute. If they've got git-send-email set up and want to use that, we explicitly tell them that they can. But for those who don't, we suggest they make a PR which is most likely something they already know how to do. If you're already a contributor, just keep doing what you're doing. The only reason I could imagine to not make this change would be because someone is hoping that new people will come in and join the git-send-email camp and slow down the advance of GitLab. The reality is that the majority of mesa development is happening on GitLab these days anyway so people seem to like it. --Jason ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110735] Meson can't find 32-bit libXvMCW in non-standard path
https://bugs.freedesktop.org/show_bug.cgi?id=110735 --- Comment #7 from charlie --- I recompiled both 32-bit and 64-bit libXvMC with the patch applied and mesa meson configure error remains. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [MR] Update README to recommend MRs instead of `git send-email`
On Tue, Jul 9, 2019 at 12:17 AM Daniel Stone wrote: > > Hi, > > On Sat, 6 Jul 2019 at 18:39, Ilia Mirkin wrote: > > I see this as driving away contributions, esp from new people. MR's > > are annoying to create, since they require dealing with the hosting > > provider, getting it to host clones, etc. Everyone has email. > > My position - and the evidence of velocity from projects who have > switched - is already pretty clear, but you might be interested to > read that even kernel.org admins are trying to move away from email: > https://people.kernel.org/monsieuricon/patches-carved-into-developer-sigchains I have the same experience - I've used git since before it was usable and I'm more than happy to not have to worry about making git send-email work. I'm pretty sure that gitlab in general lowers the bar for contributions considerably, I know I find my self doing a lot more reviews and drive-by comments because of how easy it feels. > Cheers, > Daniel > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 --- Comment #11 from kyle.de...@mykolab.com --- Thanks! :) -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 Connor Abbott changed: What|Removed |Added CC||cwabbo...@gmail.com -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 --- Comment #10 from Connor Abbott --- Hopefully https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1298 should fix it. It now gets further with my machine, but it fails on 27.pipeline_test with: run: /home/cwabbott/src/vkpipeline-db/serialize.c:723: deserialize_depth_stencil_state: Assertion `pInfo->sType == VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO' failed. I have no idea why though, and it seems like a vkpipeline-db problem and not a problem with the game. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 --- Comment #9 from Connor Abbott --- Thanks, I managed to reproduce the crash with 124.pipeline_test. I'll look into it now. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 --- Comment #8 from kyle.de...@mykolab.com --- Okay, I've uploaded the shaders, and terminal output. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 --- Comment #7 from kyle.de...@mykolab.com --- Created attachment 144734 --> https://bugs.freedesktop.org/attachment.cgi?id=144734=edit Terminal output -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 --- Comment #6 from kyle.de...@mykolab.com --- Created attachment 144733 --> https://bugs.freedesktop.org/attachment.cgi?id=144733=edit All of the captured pipelines -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 --- Comment #5 from kyle.de...@mykolab.com --- Always the obvious things. :P -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092
--- Comment #4 from Rhys Perry ---
(In reply to kyle.devir from comment #3)
> vkpipeline-db isn't dumping any shaders... despite my environment variables
> being correct.
>
> This is how I run it:
>
> export
> VK_LAYER_PATH="/run/media/valmar/DataSSD/Games/WineLibraries/x64/
> VkLayer_vkpipeline_db.json"
> export
> LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/run/media/valmar/DataSSD/Games/
> WineLibraries/x64/libVkLayer_vkpipeline_db.so"
> export VK_INSTANCE_LAYERS="VK_LAYER_vkpipeline_db"
>
> mkdir -p
> "/run/media/valmar/DataSSD/Games/SteamLibraryLinux/steamapps/common/Devil
> May Cry 5/CapturedShaders"
> export
> VKPIPELINE_DB_CAPTURE_PATH="/run/media/valmar/DataSSD/Games/
> SteamLibraryLinux/steamapps/common/Devil May Cry 5/CapturedShaders"
> export ENABLE_VKPIPELINE_DB="1"
>
> ${ProtonWineBinary} "${GameDir}/${GameBinary}"
Try setting LD_LIBRARY_PATH to
"$LD_LIBRARY_PATH:/run/media/valmar/DataSSD/Games/WineLibraries/x64/" instead?
I also set VK_LAYER_PATH to the directory containing VkLayer_vkpipeline_db.json
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[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092
--- Comment #3 from kyle.de...@mykolab.com ---
vkpipeline-db isn't dumping any shaders... despite my environment variables
being correct.
This is how I run it:
export
VK_LAYER_PATH="/run/media/valmar/DataSSD/Games/WineLibraries/x64/VkLayer_vkpipeline_db.json"
export
LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/run/media/valmar/DataSSD/Games/WineLibraries/x64/libVkLayer_vkpipeline_db.so"
export VK_INSTANCE_LAYERS="VK_LAYER_vkpipeline_db"
mkdir -p
"/run/media/valmar/DataSSD/Games/SteamLibraryLinux/steamapps/common/Devil May
Cry 5/CapturedShaders"
export
VKPIPELINE_DB_CAPTURE_PATH="/run/media/valmar/DataSSD/Games/SteamLibraryLinux/steamapps/common/Devil
May Cry 5/CapturedShaders"
export ENABLE_VKPIPELINE_DB="1"
${ProtonWineBinary} "${GameDir}/${GameBinary}"
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[Mesa-dev] [ANNOUNCE] Mesa 19.1.2
Mesa 19.1.2 is now available.
In this release we have:
Different fixes for the Intel and AMD Vulkan drivers, Freedreno, the Meson
build system,
and some other fixes for other parts and/or drivers.
Worth to mention a fix for a crash in Wolfenstein II with the RADV driver, and
another fix
relevant for DXVK on Intel gen7 drivers.
Anuj Phogat (3):
Revert "i965/icl: Add WA_2204188704 to disable pixel shader panic
dispatch"
Revert "anv/icl: Add WA_2204188704 to disable pixel shader panic dispatch"
Revert "iris/icl: Add WA_2204188704 to disable pixel shader panic
dispatch"
Arfrever Frehtes Taifersar Arahesis (1):
meson: Improve detection of Python when using Meson >=0.50.
Bas Nieuwenhuizen (2):
radv: Only allocate supplied number of descriptors when variable.
radv: Fix interactions between variable descriptor count and inline
uniform blocks.
Caio Marcelo de Oliveira Filho (1):
spirv: Ignore ArrayStride in OpPtrAccessChain for Workgroup
Dylan Baker (2):
meson: Add support for using cmake for finding LLVM
Revert "meson: Add support for using cmake for finding LLVM"
Eric Anholt (2):
freedreno: Fix UBO load range detection on booleans.
freedreno: Fix up end range of unaligned UBO loads.
Eric Engestrom (1):
meson: bump required libdrm version to 2.4.81
Gert Wollny (2):
gallium: Add CAP for opcode DIV
vl: Use CS composite shader only if TEX_LZ and DIV are supported
Ian Romanick (1):
glsl: Don't increase the iteration count when there are no terminators
James Clarke (1):
meson: GNU/kFreeBSD has DRM/KMS and requires -D_GNU_SOURCE
Jason Ekstrand (2):
anv/descriptor_set: Only write texture swizzles if we have an image view
iris: Use a uint16_t for key sizes
Jory Pratt (2):
util: Heap-allocate 256K zlib buffer
meson: Search for execinfo.h
Juan A. Suarez Romero (4):
docs: add sha256 checksums for 19.1.1
intel: fix wrong format usage
Update version to 19.1.2
docs: add release notes for 19.1.2
Kenneth Graunke (2):
iris: Enable PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
gallium: Make util_copy_image_view handle shader_access
Lionel Landwerlin (2):
intel/compiler: fix derivative on y axis implementation
intel/compiler: don't use byte operands for src1 on ICL
Nanley Chery (2):
intel: Add and use helpers for level0 extent
isl: Don't align phys_level0_sa by block dimension
Nataraj Deshpande (1):
anv: Add HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED in vk_format
Pierre-Eric Pelloux-Prayer (2):
mesa: delete framebuffer texture attachment sampler views
radeon/uvd: fix calc_ctx_size_h265_main10
Rob Clark (1):
freedreno/a5xx: fix batch leak in fd5 blitter path
Sagar Ghuge (1):
glsl: Fix round64 conversion function
Samuel Pitoiset (1):
radv: only enable VK_AMD_gpu_shader_{half_float,int16} on GFX9+
Sergii Romantsov (1):
i965: leaking of upload-BO with push constants
Ville Syrjälä (1):
anv/cmd_buffer: Reuse gen8 Cmd{Set, Reset}Event on gen7
git tag: mesa-19.1.2
https://mesa.freedesktop.org/archive/mesa-19.1.2.tar.xz
MD5: 7cb3df6f46cfc08bba5245d091cd4524 mesa-19.1.2.tar.xz
SHA1: 05e0e5685892504958d7245f6877a8814e235f02 mesa-19.1.2.tar.xz
SHA256: 813a144ea8ebefb7b48b6733f3f603855b0f61268d86cc1cc26a6b4be908fcfd
mesa-19.1.2.tar.xz
SHA512:
cab30694a409a5037996dd50cef1567eb9e0b83ed69cdb4fbc893a844ed35434fcd05023d48fce2831219866fa420500b53650c791bea286233f4cd6c2703e19
mesa-19.1.2.tar.xz
PGP: https://mesa.freedesktop.org/archive/mesa-19.1.2.tar.xz.sig
signature.asc
Description: This is a digitally signed message part
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[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 --- Comment #2 from kyle.de...@mykolab.com --- Yeah, I will. Just realized I should have specified I ran it using DXVK, not VKD3D. Not that it makes a difference, perhaps. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 --- Comment #1 from Connor Abbott --- Can you upload a trace that shows the problem? I think the easiest way is to use vkpipeline-db (https://gitlab.freedesktop.org/mesa/vkpipeline-db) to capture the shaders using a mesa before the problem commit and then compile them using mesa master to find the problematic pipeline_test file. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] egl/android: Update color_buffer[] querying for buffer age
On Monday, 2019-07-08 11:58:11 -0700, Nataraj Deshpande wrote:
> color_buffers[] is currently hard coded to 3 for android which fails
> in droid_window_dequeue_buffer when ANativeWindow creates 4 color_buffers
> on ChromeOS while querying buffer age during dEQP partial_update tests.
>
> Fixes dEQP-EGL.functional.partial_update* tests on chromebooks with
> enabling EGL_KHR_partial_update.
>
> Fixes: 2acc69da8ce "EGL/Android: Add EGL_EXT_buffer_age extension"
> Signed-off-by: Nataraj Deshpande
> ---
> src/egl/drivers/dri2/egl_dri2.h | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
> index 943ff18..635a100 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -322,13 +322,11 @@ struct dri2_egl_surface
> __DRIimage *dri_image_front;
>
> /* Used to record all the buffers created by ANativeWindow and their ages.
> -* Usually Android uses at most triple buffers in ANativeWindow
> -* so hardcode the number of color_buffers to 3.
Might be good to update the comment instead of removing it, but either way:
Acked-by: Eric Engestrom
> */
> struct {
>struct ANativeWindowBuffer *buffer;
>int age;
> - } color_buffers[3], *back;
> + } color_buffers[4], *back;
> #endif
>
> /* surfaceless and device */
> --
> 2.7.4
>
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[Mesa-dev] [Bug 111092] Devil May Cry 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 kyle.de...@mykolab.com changed: What|Removed |Added Summary|Devil May 5 segfaults with |Devil May Cry 5 segfaults |"unsupported nir load_const |with "unsupported nir |bit_size: 1", first bad |load_const bit_size: 1", |commit: "radv: Use NIR |first bad commit: "radv: |barycentric intrinsics",|Use NIR barycentric |118a66df9907772bb9e5503b736 |intrinsics", |c95d7bb62d52c |118a66df9907772bb9e5503b736 ||c95d7bb62d52c -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 kyle.de...@mykolab.com changed: What|Removed |Added OS|All |Linux (All) Hardware|Other |x86-64 (AMD64) CC||kyle.de...@mykolab.com -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111092] Devil May 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c
https://bugs.freedesktop.org/show_bug.cgi?id=111092 Bug ID: 111092 Summary: Devil May 5 segfaults with "unsupported nir load_const bit_size: 1", first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c Product: Mesa Version: git Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Drivers/Vulkan/radeon Assignee: mesa-dev@lists.freedesktop.org Reporter: kyle.de...@mykolab.com QA Contact: mesa-dev@lists.freedesktop.org Devil May Cry 5 segfaults with the error "unsupported nir load_const bit_size: 1" The first bad commit: "radv: Use NIR barycentric intrinsics", 118a66df9907772bb9e5503b736c95d7bb62d52c -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: compute correct number of input vertices for NGG
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5942e20dafe..96b20c1c730 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1616,6 +1616,29 @@ static void clamp_gsprims_to_esverts(unsigned
*max_gsprims, unsigned max_esverts
*max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
}
+static unsigned
+radv_get_num_input_vertices(struct radv_pipeline *pipeline)
+{
+ if (radv_pipeline_has_gs(pipeline)) {
+ struct radv_shader_variant *gs =
+ radv_get_shader(pipeline, MESA_SHADER_GEOMETRY);
+
+ return gs->info.gs.vertices_in;
+ }
+
+ if (radv_pipeline_has_tess(pipeline)) {
+ struct radv_shader_variant *tes = radv_get_shader(pipeline,
MESA_SHADER_TESS_EVAL);
+
+ if (tes->info.tes.point_mode)
+ return 1;
+ if (tes->info.tes.primitive_mode == GL_ISOLINES)
+ return 2;
+ return 3;
+ }
+
+ return 3;
+}
+
static struct radv_ngg_state
calculate_ngg_info(const VkGraphicsPipelineCreateInfo *pCreateInfo,
struct radv_pipeline *pipeline)
@@ -1625,7 +1648,7 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo,
struct radv_es_output_info *es_info =
radv_pipeline_has_tess(pipeline) ? _info->tes.es_info :
_info->vs.es_info;
unsigned gs_type = radv_pipeline_has_gs(pipeline) ?
MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
- unsigned max_verts_per_prim = 3; // triangles
+ unsigned max_verts_per_prim = radv_get_num_input_vertices(pipeline);
unsigned min_verts_per_prim =
gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
unsigned gs_num_invocations = gs_info ? MAX2(gs_info->gs.invocations,
1) : 1;
--
2.22.0
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Re: [Mesa-dev] [MR] Update README to recommend MRs instead of `git send-email`
Hi, On Sat, 6 Jul 2019 at 18:39, Ilia Mirkin wrote: > I see this as driving away contributions, esp from new people. MR's > are annoying to create, since they require dealing with the hosting > provider, getting it to host clones, etc. Everyone has email. My position - and the evidence of velocity from projects who have switched - is already pretty clear, but you might be interested to read that even kernel.org admins are trying to move away from email: https://people.kernel.org/monsieuricon/patches-carved-into-developer-sigchains Cheers, Daniel ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] egl/android: Update color_buffer[] querying for buffer age
color_buffers[] is currently hard coded to 3 for android which fails
in droid_window_dequeue_buffer when ANativeWindow creates 4 color_buffers
on ChromeOS while querying buffer age during dEQP partial_update tests.
Fixes dEQP-EGL.functional.partial_update* tests on chromebooks with
enabling EGL_KHR_partial_update.
Fixes: 2acc69da8ce "EGL/Android: Add EGL_EXT_buffer_age extension"
Signed-off-by: Nataraj Deshpande
---
src/egl/drivers/dri2/egl_dri2.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 943ff18..635a100 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -322,13 +322,11 @@ struct dri2_egl_surface
__DRIimage *dri_image_front;
/* Used to record all the buffers created by ANativeWindow and their ages.
-* Usually Android uses at most triple buffers in ANativeWindow
-* so hardcode the number of color_buffers to 3.
*/
struct {
struct ANativeWindowBuffer *buffer;
int age;
- } color_buffers[3], *back;
+ } color_buffers[4], *back;
#endif
/* surfaceless and device */
--
2.7.4
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[Mesa-dev] [Bug 107942] Isaac AntiBirth under wine has invisible entities tu to clipping plane issue
https://bugs.freedesktop.org/show_bug.cgi?id=107942 Timothy Arceri changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |NOTOURBUG -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/6] radv: emit VGT_GS_MAX_VERT_OUT for legacy and NGG paths for GS
Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 703dbe54507..ce315da47c3 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3563,8 +3563,6 @@ radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs, offset += num_components[3] * gs_max_out_vertices; radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset); - radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out); - radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4); radeon_emit(ctx_cs, num_components[0]); radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0); @@ -3626,6 +3624,9 @@ radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs, radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs, ngg_state); else radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs, gs_state); + + radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT, + gs->info.gs.vertices_out); } static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16) -- 2.22.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 6/6] radv: set correct number of VGPRs for GS on GFX10
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index b6270136643..8298498fbdc 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -795,7 +795,7 @@ static void radv_postprocess_config(const struct
radv_physical_device *pdevice,
}
if (pdevice->rad_info.chip_class >= GFX10 &&
- (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL)) {
+ (stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL ||
stage == MESA_SHADER_GEOMETRY)) {
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
/* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 /
InstanceID) */
--
2.22.0
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[Mesa-dev] [PATCH 5/6] radv: fix VGT_ESGS_RING_ITEMSIZE for GS as NGG on GFX10
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index ce315da47c3..147d72d146e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1624,7 +1624,7 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo,
struct radv_shader_variant_info *gs_info =
>shaders[MESA_SHADER_GEOMETRY]->info;
struct radv_es_output_info *es_info =
radv_pipeline_has_tess(pipeline) ? _info->tes.es_info :
_info->vs.es_info;
- unsigned gs_type = MESA_SHADER_VERTEX;
+ unsigned gs_type = radv_pipeline_has_gs(pipeline) ?
MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
unsigned max_verts_per_prim = 3; // triangles
unsigned min_verts_per_prim =
gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
@@ -1795,7 +1795,12 @@ calculate_ngg_info(const VkGraphicsPipelineCreateInfo
*pCreateInfo,
ngg.prim_amp_factor = prim_amp_factor;
ngg.max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
ngg.ngg_emit_size = max_gsprims * gsprim_lds_size;
- ngg.vgt_esgs_ring_itemsize = 1;
+
+ if (gs_type == MESA_SHADER_GEOMETRY) {
+ ngg.vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
+ } else {
+ ngg.vgt_esgs_ring_itemsize = 1;
+ }
pipeline->graphics.esgs_ring_size = 4 * max_esverts * esvert_lds_size;
--
2.22.0
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[Mesa-dev] [PATCH 1/6] radv: add radv_pipeline_generate_hw_gs() helper
For legacy GS path.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 29 -
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 91ce108ef92..fc09bad5fe1 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3531,22 +3531,18 @@ radv_pipeline_generate_tess_shaders(struct
radeon_cmdbuf *ctx_cs,
}
static void
-radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
- struct radeon_cmdbuf *cs,
- struct radv_pipeline *pipeline,
- const struct radv_gs_state *gs_state)
+radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
+struct radeon_cmdbuf *cs,
+struct radv_pipeline *pipeline,
+struct radv_shader_variant *gs,
+const struct radv_gs_state *gs_state)
{
- struct radv_shader_variant *gs;
unsigned gs_max_out_vertices;
uint8_t *num_components;
uint8_t max_stream;
unsigned offset;
uint64_t va;
- gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
- if (!gs)
- return;
-
gs_max_out_vertices = gs->info.gs.vertices_out;
max_stream = gs->info.info.gs.max_stream;
num_components = gs->info.info.gs.num_stream_output_components;
@@ -3611,6 +3607,21 @@ radv_pipeline_generate_geometry_shader(struct
radeon_cmdbuf *ctx_cs,
radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline,
pipeline->gs_copy_shader);
}
+static void
+radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
+ struct radeon_cmdbuf *cs,
+ struct radv_pipeline *pipeline,
+ const struct radv_gs_state *gs_state)
+{
+ struct radv_shader_variant *gs;
+
+ gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
+ if (!gs)
+ return;
+
+ radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs, gs_state);
+}
+
static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool
float16)
{
uint32_t ps_input_cntl;
--
2.22.0
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[Mesa-dev] [PATCH 2/6] radv: keep track of whether NGG is used for GS on GFX10
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 1 +
src/amd/vulkan/radv_pipeline.c| 4 +++-
src/amd/vulkan/radv_shader.h | 6 ++
3 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index b72d1aa0023..f93ee779f0a 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3971,6 +3971,7 @@ ac_fill_shader_info(struct radv_shader_variant_info
*shader_info, struct nir_sha
shader_info->gs.vertices_out = nir->info.gs.vertices_out;
shader_info->gs.output_prim = nir->info.gs.output_primitive;
shader_info->gs.invocations = nir->info.gs.invocations;
+shader_info->is_ngg = options->key.gs.as_ngg;
break;
case MESA_SHADER_TESS_EVAL:
shader_info->tes.primitive_mode =
nir->info.tess.primitive_mode;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index fc09bad5fe1..bb6f877a6ee 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2254,7 +2254,9 @@ radv_fill_shader_keys(struct radv_device *device,
}
if (device->physical_device->rad_info.chip_class >= GFX10) {
- if (nir[MESA_SHADER_TESS_CTRL]) {
+ if (nir[MESA_SHADER_GEOMETRY]) {
+ keys[MESA_SHADER_GEOMETRY].gs.as_ngg = true;
+ } else if (nir[MESA_SHADER_TESS_CTRL]) {
keys[MESA_SHADER_TESS_EVAL].tes.out.as_ngg = true;
} else {
keys[MESA_SHADER_VERTEX].vs.out.as_ngg = true;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index f8933614bd7..b4f833d7570 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -112,12 +112,18 @@ struct radv_fs_variant_key {
uint32_t is_int10;
};
+
+struct radv_gs_variant_key {
+ uint32_t as_ngg:1;
+};
+
struct radv_shader_variant_key {
union {
struct radv_vs_variant_key vs;
struct radv_fs_variant_key fs;
struct radv_tes_variant_key tes;
struct radv_tcs_variant_key tcs;
+ struct radv_gs_variant_key gs;
};
bool has_multiview_view_index;
};
--
2.22.0
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[Mesa-dev] [PATCH 3/6] radv: emit the geometry shader as NGG if enabled on GFX10
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index bb6f877a6ee..703dbe54507 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3613,7 +3613,8 @@ static void
radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
struct radeon_cmdbuf *cs,
struct radv_pipeline *pipeline,
- const struct radv_gs_state *gs_state)
+ const struct radv_gs_state *gs_state,
+ const struct radv_ngg_state *ngg_state)
{
struct radv_shader_variant *gs;
@@ -3621,7 +3622,10 @@ radv_pipeline_generate_geometry_shader(struct
radeon_cmdbuf *ctx_cs,
if (!gs)
return;
- radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs, gs_state);
+ if (gs->info.is_ngg)
+ radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs,
ngg_state);
+ else
+ radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs,
gs_state);
}
static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool
float16)
@@ -3944,7 +3948,7 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess, ngg);
radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess, ngg);
- radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs);
+ radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline, gs, ngg);
radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
--
2.22.0
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[Mesa-dev] [PATCH 3/4] radv: fix computing the number of ES VGPRS for TES on GFX10
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index b6270136643..ec68f51901f 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -802,7 +802,8 @@ static void radv_postprocess_config(const struct
radv_physical_device *pdevice,
if (stage == MESA_SHADER_VERTEX) {
es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3
: 0;
} else if (stage == MESA_SHADER_TESS_EVAL) {
- es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3
: 2;
+ bool enable_prim_id = info->tes.export_prim_id ||
info->info.uses_prim_id;
+ es_vgpr_comp_cnt = enable_prim_id ? 3 : 2;
}
bool tes_triangles = stage == MESA_SHADER_TESS_EVAL &&
--
2.22.0
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[Mesa-dev] [PATCH 4/4] radv: fix setting VGT_REUSE_OFF for TES on GFX10
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 91ce108ef92..d2002dd904b 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3338,6 +3338,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs,
const struct radv_ngg_state *ngg_state)
{
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
+ gl_shader_stage es_type =
+ radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL :
MESA_SHADER_VERTEX;
radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
radeon_emit(cs, va >> 8);
@@ -3388,9 +3390,12 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs,
cull_dist_mask << 8 |
clip_dist_mask);
- /* TODO: Correctly set REUSE_OFF */
+ bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family
== CHIP_NAVI10 &&
+
pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 &&
+es_type == MESA_SHADER_TESS_EVAL;
+
radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
- S_028AB4_REUSE_OFF(0));
+ S_028AB4_REUSE_OFF(vgt_reuse_off));
radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
ngg_state->vgt_esgs_ring_itemsize);
--
2.22.0
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[Mesa-dev] [PATCH 2/4] radv: set max workgroup size to 128 for TES as NGG on GFX10
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 9644185f870..67630c4ee92 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3721,7 +3721,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct
ac_llvm_compiler *ac_llvm,
}
if (ctx.ac.chip_class >= GFX10) {
- if (shaders[0]->info.stage == MESA_SHADER_VERTEX &&
+ if (is_pre_gs_stage(shaders[0]->info.stage) &&
options->key.vs.out.as_ngg) {
ctx.max_workgroup_size = 128;
}
--
2.22.0
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[Mesa-dev] [PATCH 1/4] radv: fix allocating USER SGPRs on GFX10
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index b72d1aa0023..9644185f870 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1004,13 +1004,6 @@ static void create_function(struct radv_shader_context
*ctx,
struct arg_info args = {};
LLVMValueRef desc_sets;
bool needs_view_index = needs_view_index_sgpr(ctx, stage);
- allocate_user_sgprs(ctx, stage, has_previous_stage,
- previous_stage, needs_view_index, _sgpr_info);
-
- if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
- add_arg(, ARG_SGPR,
ac_array_in_const_addr_space(ctx->ac.v4i32),
- >ring_offsets);
- }
if (ctx->ac.chip_class >= GFX10) {
if (is_pre_gs_stage(stage) && ctx->options->key.vs.out.as_ngg) {
@@ -1021,6 +1014,14 @@ static void create_function(struct radv_shader_context
*ctx,
}
}
+ allocate_user_sgprs(ctx, stage, has_previous_stage,
+ previous_stage, needs_view_index, _sgpr_info);
+
+ if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
+ add_arg(, ARG_SGPR,
ac_array_in_const_addr_space(ctx->ac.v4i32),
+ >ring_offsets);
+ }
+
switch (stage) {
case MESA_SHADER_COMPUTE:
declare_global_input_sgprs(ctx, _sgpr_info, ,
--
2.22.0
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[Mesa-dev] [Bug 100789] Mesa (Padoka Pkppa), Textures become corrupt in counterstrike 1.6 and in steam overlay after indeterminate amount of time
https://bugs.freedesktop.org/show_bug.cgi?id=100789 --- Comment #9 from Timothy Arceri --- I'm confused. Those new screen shots don't appear to have any problem. What are you trying to show? -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
