Re: [Mesa-dev] How to build mesa to run vulkan application on Intel HD graphics?

2019-07-23 Thread Xu, Xing
This works! Thanks dave! Regards, Xing -Original Message- From: Dave Airlie [mailto:airl...@gmail.com] Sent: Wednesday, July 24, 2019 10:53 AM To: Xu, Xing Cc: mesa-dev@lists.freedesktop.org Subject: Re: [Mesa-dev] How to build mesa to run vulkan application on Intel HD graphics? On

Re: [Mesa-dev] How to build mesa to run vulkan application on Intel HD graphics?

2019-07-23 Thread Dave Airlie
On Wed, 24 Jul 2019 at 11:55, Xu, Xing wrote: > > Hi, I tried to add some logs as below in file > ./src/vulkan/wsi/wsi_common_x11.c (x11_queue_present): > > printf("%s,%d\n",__FUNCTION__,__LINE__); > > assert(0); > > but got nothing(no logs and assert didn’t happen) when I run my application. >

[Mesa-dev] How to build mesa to run vulkan application on Intel HD graphics?

2019-07-23 Thread Xu, Xing
Hi, I tried to add some logs as below in file ./src/vulkan/wsi/wsi_common_x11.c (x11_queue_present): printf("%s,%d\n",__FUNCTION__,__LINE__); assert(0); but got nothing(no logs and assert didn't happen) when I run my application. Here is how I build run my applications: 1), Build install

[Mesa-dev] [PATCH] intel/ir: Fix CFG corruption in opt_predicated_break().

2019-07-23 Thread Francisco Jerez
Specifically the optimization of a conditional BREAK + WHILE sequence into a conditional WHILE seems pretty broken. The list of successors of "earlier_block" (where the conditional BREAK was found) is emptied and then re-created with the same edges for no apparent reason. On top of that the list

[Mesa-dev] [PATCH 2/4] panfrost: Use nir_gather_info information about discards

2019-07-23 Thread Alyssa Rosenzweig
No need to track this ourselves! Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_assemble.c | 2 +- src/panfrost/midgard/compiler.h | 3 --- src/panfrost/midgard/midgard_compile.c | 4 src/panfrost/midgard/midgard_compile.h | 1 - 4 files

[Mesa-dev] [PATCH 3/4] panfrost: Don't DIY point size/coord fields

2019-07-23 Thread Alyssa Rosenzweig
Again, it's in shader_info for us! Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_assemble.c | 8 ++-- src/panfrost/midgard/midgard_compile.h | 3 --- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/panfrost/pan_assemble.c

[Mesa-dev] [PATCH 0/4] panfrost: Use shader_info more

2019-07-23 Thread Alyssa Rosenzweig
We already have all this information available to us, so let's use it rather than duplicating code left and right. This is obviously a maintainability win (and means there are less places for things to wrong). But almost more important is simplifying the compiler backend specific ABI, which will

[Mesa-dev] [PATCH 4/4] panfrost: Compute I/O counts from shader_info

2019-07-23 Thread Alyssa Rosenzweig
...rather than exposing it in the vendored compiler region. Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_assemble.c | 17 ++--- src/panfrost/midgard/midgard_compile.c | 3 --- src/panfrost/midgard/midgard_compile.h | 3 --- 3 files changed, 14

[Mesa-dev] [PATCH 1/4] panfrost: Use NIR helper invocations info

2019-07-23 Thread Alyssa Rosenzweig
We don't need to guesstimate this ourselves. This will help when we bringup derivatives. Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_assemble.c | 1 + src/gallium/drivers/panfrost/pan_context.c | 2 +- src/gallium/drivers/panfrost/pan_context.h | 3 +++ 3 files

[Mesa-dev] [ANNOUNCE] glu 9.0.1

2019-07-23 Thread Matt Turner
Amarnath Valluri (1): libutils/mipmap.c: Fixed possible memory leak John Hein (1): pkgconfig: Include -I path for glu itself Krzysztof Kosiński (1): Remove all uses of the register keyword. Matt Turner (4): Add -D(N)DEBUG to CFLAGS dependent on --enable-debug libutil:

[Mesa-dev] [AppVeyor] mesa master #12016 failed

2019-07-23 Thread AppVeyor
Build mesa 12016 failed Commit 2631fd3b0b by Dave Airlie on 7/22/2019 2:04 AM: gallivm: rework lp_build_tgsi_soa to take a struct\n\nThe parameters were getting messy and I have to add a few more\nfor compute shaders, so clean it up before

[Mesa-dev] [Bug 111150] [BRW] WRC 5 asserts with gallium nine and iris.

2019-07-23 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=50 --- Comment #7 from Nanley Chery --- (In reply to Matías Zúñiga from comment #6) > (In reply to Nanley Chery from comment #3) > > *** Bug 62 has been marked as a duplicate of this bug. *** > > Sorry, i didn't find this bug before posting.

Re: [Mesa-dev] [PATCH 5/5] radv/gfx10: enable VK_EXT_transform_feedback

2019-07-23 Thread Bas Nieuwenhuizen
r-b for the series if you resolve my comment on patch 4. On Tue, Jul 23, 2019 at 3:21 PM Samuel Pitoiset wrote: > > When a pipeline uses transform feedback, the driver fallbacks to > the legacy path because NGG support for streamout is a non-trivial > amount of work. > > AMDVLK also uses the

Re: [Mesa-dev] [PATCH 4/5] radv/gfx10: do not enable NGG if a pipeline uses XFB

2019-07-23 Thread Bas Nieuwenhuizen
On Tue, Jul 23, 2019 at 3:21 PM Samuel Pitoiset wrote: > > NGG GS for streamout requires a bunch of work, so enable it with > the legacy path only for now. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_pipeline.c | 28 > 1 file changed, 28

Re: [Mesa-dev] [PATCH v3] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Bas Nieuwenhuizen
r-b On Tue, Jul 23, 2019 at 2:44 PM Samuel Pitoiset wrote: > > For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1. > > v3: fix instanceID input VGPR for geometry > v2: fix instanceID > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_nir_to_llvm.c | 12

[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization

2019-07-23 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #16 from Steven Newbury --- Replaying the trace with a recent Mesa causes my GPU to crash in such a way it requires reboot. Is that expected to work? I've rebuit mesa + llvm + xorg-server git master using gcc-9.1 and

Re: [Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Karol Herbst
yeah.. I am not quite sure myself about it. But skipping on the div emulation seems like a good idea in general. But it's also not common enough to actually care all that much about it. On Tue, Jul 23, 2019 at 5:18 PM Ilia Mirkin wrote: > > On Tue, Jul 23, 2019 at 11:15 AM Karol Herbst wrote: >

Re: [Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Ilia Mirkin
On Tue, Jul 23, 2019 at 11:15 AM Karol Herbst wrote: > > On Tue, Jul 23, 2019 at 4:50 PM Ilia Mirkin wrote: > > > > You handle 1/n but not 1%n? TBH, the 1/n code isn't 100% obvious to > > me... 1/n = |n|-1 > 0 ? i forget how SLCT works, but I can't > > think of a way to finish that

Re: [Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Karol Herbst
On Tue, Jul 23, 2019 at 4:50 PM Ilia Mirkin wrote: > > You handle 1/n but not 1%n? TBH, the 1/n code isn't 100% obvious to > me... 1/n = |n|-1 > 0 ? i forget how SLCT works, but I can't > think of a way to finish that expression in terms of |n|-1 and n. And > what about n == 0. I'd just as

Re: [Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Ilia Mirkin
You handle 1/n but not 1%n? TBH, the 1/n code isn't 100% obvious to me... 1/n = |n|-1 > 0 ? i forget how SLCT works, but I can't think of a way to finish that expression in terms of |n|-1 and n. And what about n == 0. I'd just as soon drop that case. On Tue, Jul 23, 2019 at 10:20 AM Mark

[Mesa-dev] [PATCH] nv50/ir: Add mul and mod constant optimizations

2019-07-23 Thread Mark Menzynski
Optimizations for 0/n, 1/n and 0%n. No changes in shader db tests, because it is never used here, but it should become handy. Signed-off-by: Mark Menzynski --- .../nouveau/codegen/nv50_ir_peephole.cpp | 30 +-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH v2] gm107/ir: Add stg, ldg instructions and function for checking offset length

2019-07-23 Thread Mark Menzynski
Nvidia actively uses these instructions, maybe they are better in something. Long offset checking function was made because these functions only have 24 bit address offsets. v2: removed long offset funnction Signed-off-by: Mark Menzynski --- .../nouveau/codegen/nv50_ir_emit_gm107.cpp| 24

Re: [Mesa-dev] [PATCH] gm107/ir: Add stg, ldg instructions and function for checking offset length

2019-07-23 Thread Mark Menzynski
> > @@ -2414,6 +2428,17 @@ CodeEmitterGM107::emitLDS() > > emitGPR (0x00, insn->def(0)); > > } > > > > +void > > +CodeEmitterGM107::emitLDG() > > +{ > > + emitInsn (0xeed0); > > + emitLDSTs(0x30, insn->dType); > > + emitLDSTc(0x2e); > > + emitField(0x2d, 1,

[Mesa-dev] [PATCH 1/5] radv/gfx10: update streamout descriptors

2019-07-23 Thread Samuel Pitoiset
Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 84d627340e9..c2e3f3b5fd0 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++

[Mesa-dev] [PATCH 3/5] radv/gfx10: emit streamout shader config

2019-07-23 Thread Samuel Pitoiset
Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 5fd1022b05a..56f421026b7 100644 --- a/src/amd/vulkan/radv_shader.c +++

[Mesa-dev] [PATCH 4/5] radv/gfx10: do not enable NGG if a pipeline uses XFB

2019-07-23 Thread Samuel Pitoiset
NGG GS for streamout requires a bunch of work, so enable it with the legacy path only for now. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 28 1 file changed, 28 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c

[Mesa-dev] [PATCH 5/5] radv/gfx10: enable VK_EXT_transform_feedback

2019-07-23 Thread Samuel Pitoiset
When a pipeline uses transform feedback, the driver fallbacks to the legacy path because NGG support for streamout is a non-trivial amount of work. AMDVLK also uses the legacy path for streamout, while RadeonSI uses the new NGG path. Signed-off-by: Samuel Pitoiset ---

[Mesa-dev] [PATCH 2/5] radv/gfx10: declare streamout user SGPRs

2019-07-23 Thread Samuel Pitoiset
Required for legacy streamout. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_nir_to_llvm.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index cf73cdc692b..020c6d17771 100644 ---

[Mesa-dev] [PATCH v3] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Samuel Pitoiset
For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1. v3: fix instanceID input VGPR for geometry v2: fix instanceID Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_nir_to_llvm.c | 12 +--- src/amd/vulkan/radv_shader.c | 8 ++-- 2 files changed, 15

Re: [Mesa-dev] [PATCH v2] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Bas Nieuwenhuizen
r-b On Tue, Jul 23, 2019 at 2:10 PM Samuel Pitoiset wrote: > > For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1. > > v2: fix instanceID > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_nir_to_llvm.c | 12 +--- > src/amd/vulkan/radv_shader.c | 2

[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization

2019-07-23 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #15 from Steven Newbury --- I've tried recent versions, and compiled with just "-O2", every version since the commit behaves that way for me. I'm going to try to rebuild llvm with -O2, perhaps llvm is getting subtly miscompiled.

[Mesa-dev] [PATCH v2] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Samuel Pitoiset
For some reasons, InstanceID is VGPR3 although StepRate0 is set to 1. v2: fix instanceID Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_nir_to_llvm.c | 12 +--- src/amd/vulkan/radv_shader.c | 2 +- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] radv: fix crash in vkCmdClearAttachments with unused attachment

2019-07-23 Thread Juan A. Suarez Romero
On Mon, 2019-07-22 at 10:12 +0200, Samuel Pitoiset wrote: > depth_stencil_attachment and/or ds_resolve attachment can be NULL. > > This fixes crashes with > dEQP-VK.renderpass.suballocation.unused_clear_attachments.* > > Cc: 19.1 > Signed-off-by: Samuel Pitoiset > --- This does not apply

Re: [Mesa-dev] [PATCH] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Samuel Pitoiset
On 7/23/19 1:37 PM, Bas Nieuwenhuizen wrote: So does this work with tests that use multiple instances? Apparently no. If so, r-b. On Tue, Jul 23, 2019 at 1:29 PM Samuel Pitoiset wrote: Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_nir_to_llvm.c | 3 ++- 1 file changed, 2

Re: [Mesa-dev] [PATCH] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Bas Nieuwenhuizen
So does this work with tests that use multiple instances? If so, r-b. On Tue, Jul 23, 2019 at 1:29 PM Samuel Pitoiset wrote: > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_nir_to_llvm.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git

[Mesa-dev] [PATCH] radv/gfx10: fix VS input VGPRs with the legacy path

2019-07-23 Thread Samuel Pitoiset
Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_nir_to_llvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 336bae28614..9cea92e8a69 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++

[Mesa-dev] [Bug 111200] Xorg Graphical Corruption when using anything Vulkan on Navi10

2019-07-23 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=111200 Bas Nieuwenhuizen changed: What|Removed |Added Status|NEW |NEEDINFO --- Comment #1 from Bas

[Mesa-dev] [ANNOUNCE] Mesa 19.1.3

2019-07-23 Thread Juan A. Suarez Romero
Mesa 19.1.3 is now available. In this release we have: Mostly in fixes for ANV and RADV drivers, as well as NIR backend fixes. Several of those patches fixe actually crashes with the drivers, and a couple of them fix memory leaks. Bas Nieuwenhuizen (3): radv: Handle cmask being

[Mesa-dev] [Bug 111200] Xorg Graphical Corruption when using anything Vulkan on Navi10

2019-07-23 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=111200 Bug ID: 111200 Summary: Xorg Graphical Corruption when using anything Vulkan on Navi10 Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All)

Re: [Mesa-dev] [PATCH] radv/gfx10: enable CLEAR_state

2019-07-23 Thread Bas Nieuwenhuizen
r-b On Tue, Jul 23, 2019 at 8:37 AM Samuel Pitoiset wrote: > > It actually works. > > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_device.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c >

[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization

2019-07-23 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #14 from Connor Abbott --- I tried this on my polaris10 card (Rx 580) and I couldn't see the corruption with either the commit you mentioned + LLVM 8.0, or a recent mesa master + LLVM master. The before trace wouldn't render with an

[Mesa-dev] [AppVeyor] mesa master #11986 completed

2019-07-23 Thread AppVeyor
Build mesa 11986 completed Commit b1c35fa6d6 by Eric Engestrom on 7/19/2019 9:13 PM: st/nir: use asprintf() wrapper to fix MSVC issues\n\nFixes: 856e84083eee9b22408a ("mesa/st: add sampler uniforms")\nSigned-off-by: Eric Engestrom \nReviewed-by: Eric Anholt

Re: [Mesa-dev] [PATCH] radv: fix dumping disassembly with RADV_DEBUG=shaders

2019-07-23 Thread Bas Nieuwenhuizen
r-b On Tue, Jul 23, 2019 at 9:51 AM Samuel Pitoiset wrote: > > Fixes: a20a9d0c5e7 ("radv: dont store disasm string unless keep_shader_info > flag set") > Signed-off-by: Samuel Pitoiset > --- > src/amd/vulkan/radv_shader.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff

[Mesa-dev] [PATCH] radv: fix dumping disassembly with RADV_DEBUG=shaders

2019-07-23 Thread Samuel Pitoiset
Fixes: a20a9d0c5e7 ("radv: dont store disasm string unless keep_shader_info flag set") Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_shader.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index

[Mesa-dev] [PATCH] radv/gfx10: enable CLEAR_state

2019-07-23 Thread Samuel Pitoiset
It actually works. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_device.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 992e12840f7..93b03afda22 100644 --- a/src/amd/vulkan/radv_device.c +++