On Tuesday, January 22, 2013 11:02:34 AM Eric Anholt wrote:
128 pixels of 32bpp is a tile width, and 128 pixels high of that is 16
tiles. The values I see this function having are:
mask_x = 127
mask_y = 15
draw_x = 0
draw_y = 128
image-offset = (16 * 4096)
So when we go to texture
- Rename draw_x/y to tile_x/y in dri image struct. These are now used as
adjustment pixels from our stored aligned offset to the exported image
instead of the entire x/y offset from the base address.
- Take into consideration the offset from our bo so that sub-image functions
resolves
Add create image from texture extension and bump version.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
include/GL/internal/dri_interface.h | 14 +-
src/egl/drivers/dri2/egl_dri2.c | 85 +++
2 files changed, 98 insertions(+), 1
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_regions.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_regions.h
b/src/mesa/drivers/dri/intel/intel_regions.h
index 8737a6d..1eef3b5 100644
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 37
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 14 -
2 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri
Add helper to calculate fine-grained x and y adjustment pixels
to an image within a miptree level for tiled regions.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 15 +++
src/mesa/drivers/dri/intel
If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++-
src/mesa
We need to take account the offset from original bo when using glTexSubImage()
and other functions that manipulate the subregion of an exported texture.
Offsets are appended to mapped region address and when blitting from a source
region.
Signed-off-by: Abdiel Janulgue abdiel.janul
to
offset alignment issues, report INVALID_OPERATION as per spec wording.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 179 +
1 file changed, 159 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers
When binding a region to a texture image, re-create the miptree base-level
considering the offset and dimension information exported by DRIImage.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 31 --
1
Hi,
On Tuesday, January 29, 2013 04:00:28 PM Eric Anholt wrote:
Part of my motivation here was the number of cache misses we have in the
first reference of a region after referencing the miptree wrapping it, for
things that should all live in the first cacheline of one struct.
I think I've
On Tuesday, January 29, 2013 07:54:59 AM Eric Anholt wrote:
Abdiel Janulgue abdiel.janul...@linux.intel.com writes:
- Rename draw_x/y to tile_x/y in dri image struct. These are now used as
adjustment pixels from our stored aligned offset to the exported image
instead of the entire x
KHR_gl_image7 branch
CC: Eric Anholt e...@anholt.net
Reviewed-by: Eric Anholt e...@anholt.net (v6)
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org
Add create image from texture extension and bump version.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
include/GL/internal/dri_interface.h | 14 +-
src/egl/drivers/dri2/egl_dri2.c | 85 +++
2 files changed, 98 insertions(+), 1
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_regions.h |6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_regions.h
b/src/mesa/drivers/dri/intel/intel_regions.h
index 1aff5d9..84cf08b 100644
Add helper to calculate fine-grained x and y adjustment pixels
to an image within a miptree level for tiled regions.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 15 +++
src/mesa/drivers/dri/intel
If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++-
src/mesa
When binding a region to a texture image, re-create the miptree base-level
considering the offset and dimension information exported by DRIImage.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 30 --
1
We need to take account the offset from original bo when using glTexSubImage()
and other functions that manipulate the subregion of an exported texture.
Offsets are appended to mapped region address and when blitting from a source
region.
Signed-off-by: Abdiel Janulgue abdiel.janul
to
offset alignment issues, report INVALID_OPERATION as per spec wording.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 179 +
1 file changed, 159 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers
to
offset alignment issues, report INVALID_OPERATION as per spec wording.
v8: Bump intelImageExtension version
Reviewed-by: Eric Anholt e...@anholt.net (v6)
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 181
On Thursday, January 31, 2013 10:31:33 AM Chad Versace wrote:
+#include egl/main/eglcurrent.h
+static __DRIimage *
+intel_create_image_from_texture(__DRIcontext *context, int target,
+unsigned texture, int zoffset,
+
. This was spotted by Eric earlier.
Reviewed-by: Eric Anholt e...@anholt.net (v6)
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 60 +++---
1 file changed, 53 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri
Android build problems based on feedback from
Adrian M Negreanu and Chad Versace.
-Move the non-tile-aligned check and error-reporting to
intel_set_texture_image_region
Reviewed-by: Eric Anholt e...@anholt.net (v6)
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=60212
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c |1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel
-dev/2013-May/039088.html
Abdiel Janulgue (12):
intel: Add resource streamer control defines
intel: On Haswell hardware, enable the resource streamer on batchbuffer
start
i965: Temporarily disable resource streamer when state base address is
updated.
i965: Add
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_reg.h |4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h
b/src/mesa/drivers/dri/i965/intel_reg.h
index f45a8f3..2cf68dd 100644
--- a/src/mesa/drivers
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 409df29..84736a8 100644
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 5730eed..436077b 100644
--- a/src/mesa
Prior to changing the Surface State Base Address, the resouce streamer must be
disabled
within a batch buffer where the RS is enabled. RS is re-enabled again once the
SBA is updated.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_misc_state.c
On Haswell hardware with resource streamer enabled, enable the on-chip hardware
binding tables. The hw-bt can be updated directly using EDIT commands.
Skip manual generation of binding tables when this is activated.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h |5 +
src/mesa/drivers/dri/i965/brw_state.h |6 ++
src/mesa/drivers/dri/i965/gen7_misc_state.c | 31 +++
3 files changed, 42 insertions
When surface_state pointing to pull constant surfaces are changed, update
on-chip binding table. Same with VS ubo surface states.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 10 ++
1 file changed, 10 insertions
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 16 +++-
src/mesa/drivers/dri/i965/gen7_blorp.cpp |3 ++-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src
Address GPU hung due to skipping selection of 3D pipeline in blorp when RS
is switched on. I've yet to figure out the reason for this.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 11 +++
1 file changed, 11 insertions
This patch set adds support for KHR_gl_texture_2D_image,
KHR_gl_texture_cubemap_image
and KHR_gl_texture_3D_image for Gen 4 - Gen7 HW. The extension enables us to
be a bit
more conformant to the spec in Android at least. I've tested it on SandyBridge
and IvyBridge.
The approach is to export a
Add create image from texture extension.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
include/GL/internal/dri_interface.h | 12 +
src/egl/drivers/dri2/egl_dri2.c | 83 +++
2 files changed, 95 insertions(+)
diff --git a/include/GL
Add intel_miptree_create_for_offset which adds support for creating a single-
level miptree based on the existing offsets and dimensions of another
mip-tree level. Use this function as well in intel_miptree_create_for_region,
but for the whole region.
Signed-off-by: Abdiel Janulgue abdiel.janul
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 31
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 10
2 files changed, 41 insertions(+)
diff --git a/src/mesa/drivers/dri/intel
If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++-
src/mesa
Save miptree level info to DRIImage, taking offsets into consideration.
For = gen4 hw which doesn't support non-tile aligned offset, re-create
the mipmap tree internally before exporting the updated offsets to
avoid alignment problems.
Signed-off-by: Abdiel Janulgue abdiel.janul
When binding a region to a texture image, re-create the miptree base-level
considering the offset and dimension information exported by DRIImage.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 27 --
1
On Friday, December 14, 2012 03:28:12 PM Abdiel Janulgue wrote:
This patch set adds support for KHR_gl_texture_2D_image,
KHR_gl_texture_cubemap_image and KHR_gl_texture_3D_image for Gen 4 - Gen7
HW. The extension enables us to be a bit more conformant to the spec in
Android at least. I've
On Friday, December 14, 2012 11:38:04 AM Eric Anholt wrote:
Abdiel Janulgue abdiel.janul...@linux.intel.com writes:
This patch set adds support for KHR_gl_texture_2D_image,
KHR_gl_texture_cubemap_image and KHR_gl_texture_3D_image for Gen 4 -
Gen7 HW. The extension enables us to be a bit
corrected offsets back to our exported image. In this version, for
non-tile-aligned
surfaces, we copy the image to a temporary single-level miptree and refer to
the
offsets there instead of re-creating the whole miptree from scratch.
Tested on: Gen4, SandyBridge, IvyBridge
Abdiel Janulgue (6
Add create image from texture extension.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
include/GL/internal/dri_interface.h | 12 +
src/egl/drivers/dri2/egl_dri2.c | 83 +++
2 files changed, 95 insertions(+)
diff --git a/include/GL
Add intel_miptree_create_for_offset which adds support for creating a single-
level miptree based on the existing offsets and dimensions of another
mip-tree level. Use this function as well in intel_miptree_create_for_region,
but for the whole region.
Signed-off-by: Abdiel Janulgue abdiel.janul
Expose intel_miptree_copy_slice and add function calculating
x and y offsets of a miptree level within a tiled region.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 17 -
src/mesa/drivers/dri/intel
If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++-
src/mesa
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 181 +
1 file changed, 161 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index
When binding a region to a texture image, re-create the miptree base-level
considering the offset and dimension information exported by DRIImage.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 27 --
1
On Thursday, January 03, 2013 05:00:39 PM Eric Anholt wrote:
Sorry for the delay, I think we all disappeared over the holidays.
Let's see if I've got this all right. It looks like today we have
extensions for:
OES_EGL_image:
* turn an EGLImage into a 0-level texture
* turn an EGLImage
v3 here. Hopefully I've addressed the issues.
In this revision, we now report GL_INVALID_OPERATION when we
can't resolve back to specific offsets within a shared region.
For non-tile-aligned HW, this means that only base-levels of
textures can be exported.
I've also found and fixed an error in
Add create image from texture extension and
bump version.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
include/GL/internal/dri_interface.h | 14 +-
src/egl/drivers/dri2/egl_dri2.c | 83 +++
2 files changed, 96 insertions(+), 1
Expose intel_miptree_copy_slice and add function calculating
x and y offsets of a miptree level within a tiled region.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 17 -
src/mesa/drivers/dri/intel
Add intel_miptree_create_for_offset which adds support for creating a single-
level miptree based on the existing offsets and dimensions of another
mip-tree level. Use this function as well in intel_miptree_create_for_region,
but for the whole region.
Signed-off-by: Abdiel Janulgue abdiel.janul
Save miptree level info to DRIImage, taking offsets into consideration.
In non-tile-aligned surface cases where resolving back to the original image
proves problematic due to alignment issues, report INVALID_OPERATION as per
spec wording.
Signed-off-by: Abdiel Janulgue abdiel.janul
If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++-
src/mesa
When binding a region to a texture image, re-create the miptree base-level
considering the offset and dimension information exported by DRIImage.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 27 --
1
On Friday, January 11, 2013 04:27:23 PM Abdiel Janulgue wrote:
v3 here. Hopefully I've addressed the issues.
patch series lives on git://gitorious.org/mesa3d/mesa.git KHR_gl_image3
branch
In this revision, we now report GL_INVALID_OPERATION when we
can't resolve back to specific offsets
Changes from v3:
- Unexport intel_miptree_copy_slice. We don't need fake storage anymore for
non-tile aligned surfaces.
- Fix error in gen6 caught by piglit test for this extension. This is another
case where
I forgot to consider the miptree slices; this time in updating SURFACE_STATE.
--
Add create image from texture extension and
bump version.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
include/GL/internal/dri_interface.h | 14 +-
src/egl/drivers/dri2/egl_dri2.c | 83 +++
2 files changed, 96 insertions(+), 1
Add helper to calculate x and y offsets of a miptree level within a tiled
region.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 15 +++
src/mesa/drivers/dri/intel/intel_mipmap_tree.h |6 ++
2 files
Add intel_miptree_create_for_offset which adds support for creating a single-
level miptree based on the existing offsets and dimensions of another
mip-tree level. Use this function as well in intel_miptree_create_for_region,
but for the whole region.
Signed-off-by: Abdiel Janulgue abdiel.janul
If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++-
src/mesa
.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 178 +
1 file changed, 158 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
When binding a region to a texture image, re-create the miptree base-level
considering the offset and dimension information exported by DRIImage.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 27 --
1
On Tuesday, January 15, 2013 02:05:00 PM Eric Anholt wrote:
+static void
+intel_image_set_level_info(__DRIimage *image, struct intel_mipmap_tree
*mt, + int level, int slice,
+ uint32_t mask_x, uint32_t mask_y)
+{
+ image-width =
Changes since v4:
* Drop texture 3D support for now (until we test it with piglit).
I plan to add it incrementally as soon as piglit tests for it are done.
* Drop useless errors warnings and report proper EGL errors.
* Expose intel_miptree_create_internal as intel_miptree_create_layout
*
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_regions.h |7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/intel/intel_regions.h
b/src/mesa/drivers/dri/intel/intel_regions.h
index 8737a6d..95b65de 100644
Add create image from texture extension and bump version.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
include/GL/internal/dri_interface.h | 14 +-
src/egl/drivers/dri2/egl_dri2.c | 85 +++
2 files changed, 98 insertions(+), 1
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 37
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 14 -
2 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri
Add helper to calculate fine-grained x and y adjustment pixels
to an image within a miptree level for tiled regions.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 15 +++
src/mesa/drivers/dri/intel
alignment issues, report INVALID_OPERATION as per spec wording.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_screen.c | 186 +
1 file changed, 166 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri
If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++-
src/mesa
When binding a region to a texture image, re-create the miptree base-level
considering the offset and dimension information exported by DRIImage.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/intel/intel_tex_image.c | 31 --
1
I found a crash where updating the texture unit states ends up requesting a
fallback texture for a GL_TEXTURE_EXTERNAL_OES target and sets a null current
texture object for the current unit.
This is a fix by supporting TEXTURE_EXTERNAL_INDEX target in
_mesa_get_fallback_texture() and making
mesa: Fix a crash in update_texture_state() when requesting a fallback for
an external texture target.
NOTE: This is a candidate for the stable branch.
Signed-off-by: Abdiel abdiel.janul...@intel.com
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index
Probably non-intentional, but the SURFACE_STATE setup refactoring
for buffer surfaces had missed the scs bits when creating constant
surface states.
Fixes broken GLB 2.5 on Haswell where the knight's textures are missing
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src
I re-ran piglit with my resource streamer v2 implementation + this patch and
actually this fixed sporadic lockups that I've been struggling with. As
discussed at F2F with Chad and Paul, we need this for RS. I'll be posting the
RS v2 soon quite soon.
-abdiel
On Friday, September 27, 2013
Prerequisites:
- Kernel patches: [1]
(do 'make headers_install' and update libdrm headers after compiling
the kernel)
- Mesa patch: [2]
This is an update from my previous RFC patches [3]. Most notable
change is that the resource streamer is an experimental feature
disabled by
Used to toggle the resource streamer within a batchbuffer
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_reg.h |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h
b/src/mesa/drivers/dri/i965
export INTEL_RESOURCE_STREAMER={0,1} To switch on/off resource streamer.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h |1 +
src/mesa/drivers/dri/i965/intel_context.c | 24
2 files changed, 25
This is passed on the kernel to enable the resource streamer enable bit
on MI_BATCHBUFFER_START
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers
Bspec: Prior to changing the Surface State Base Address, the resouce streamer
must be disabled within a batch buffer where the RS is enabled. RS is
re-enabled again once the SBA is updated.
The resource streamer can be toggled within a batch using MI_RS_CONTROL.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_draw.c | 14 ++
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 14 ++
2 files changed, 28 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 4d1a65e..031e21e 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++
.
In addition, this change inserts the required brw_tracked_state objects
to enable hw-generated binding tables in normal render path.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 84
src/mesa/drivers
Update the on-chip binding table for every generated texture surface_state
entries. Instead of generating binding tables manually, we update individual
slots of surface state entries using the new EDIT commands for gen7.5
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src
When hardware-generated binding tables are taken into use, skip uploading
of binding tables generated manually by the driver.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 12 ++--
1 file changed, 10 insertions(+), 2
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 36
src/mesa/drivers/dri/i965/brw_defines.h|5
src/mesa/drivers/dri/i965/brw_state.h | 15 +-
3 files changed, 55
When surface_state pointing to pull constant surfaces are changed, update
on-chip binding table. Same with VS ubo surface states.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_vs_surface_state.c |9 +
1 file changed, 9 insertions
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d82a7cf
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 08c5720
When hw-generated binding tables are enabled edit the binding table
state for new SURFACE_STATE entries that are generated in the blorp path.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 ++-
1 file changed, 14
entry
within
the command only allows until 32k. Therefore, ensure that offset fits within the
highest bit of the command.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp |4 +++-
src/mesa/drivers/dri/i965/gen7_vs_state.c |3
On Wednesday, October 09, 2013 12:41:37 AM Abdiel Janulgue wrote:
Prerequisites:
- Kernel patches: [1]
(do 'make headers_install' and update libdrm headers after compiling
the kernel)
- Mesa patch: [2]
Series lives on http://cgit.freedesktop.org/~abj/mesa/ mesa_rs branch
: Eric Anholt e...@anholt.net
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965
implementation failed to catch this flags.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 87
src/mesa/drivers/dri/i965/brw_context.c|1 +
src/mesa/drivers/dri/i965/brw_context.h|1
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