I think you need to set this if *any* geometry shader in the program
tries to use a nonzero stream. Currently it looks like the last shader
wins.
On Wed, Jun 11, 2014 at 7:49 PM, Iago Toral Quiroga ito...@igalia.com wrote:
On Intel hardware when a geometry shader outputs GL_POINTS primitives we
This is pretty weird.
We should be able to generate a normal builtin function body here
which consists of just the ir_emit_vertex, passing the stream
parameter to it. This would then get inlined like any other function
leaving a bare ir_emit_vertex / ir_end_primitive with a constant
operand. If
On Wed, Jun 11, 2014 at 7:49 PM, Iago Toral Quiroga ito...@igalia.com wrote:
---
src/mesa/main/context.c | 2 +-
src/mesa/main/mtypes.h | 1 +
src/mesa/main/queryobj.c | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
On Wed, Jun 11, 2014 at 7:49 PM, Iago Toral Quiroga ito...@igalia.com wrote:
It should be possible to query the number of primitives written to each
individual stream by a geometry shader in a single draw call. For that
we need to have up to MAX_VERTEX_STREAM separate query objects.
---
I sent comments on patches 1, 3, 5, 9, 11, 16, 18
Patches 2, 4, 6-8, 10, 12-15, 17 are:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
You should also include a patch to docs/GL3.txt marking off this
subfeature for i965 :)
Do you have a bunch of piglits which exercise all the tricky corners
and there
is no consumer, then input_var must be NULL too, in which case the
linker_error would never take place.
If input_var is not NULL then there has to be a consumer stage, and in
that case we should check that we can link both stages, right?
Iago
On Wed, 2014-06-11 at 20:48 +1200, Chris Forbes wrote
(as
they are a single qualifier in the spec prior to
ARB_shading_language_420pack)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/glsl_parser.yy | 36
1 file changed, 8 insertions(+), 28 deletions(-)
diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
* spec/glsl-1.50/compiler/layout-fs-no-output.frag
* spec/glsl-1.50/compiler/layout-vs-no-input.vert
* spec/glsl-1.50/compiler/layout-vs-no-output.vert
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/ast_to_hir.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/glsl
it, hopefully that's enough information for someone to tell
what is missing in the implementation or if there is some other problem
that is causing all this.
Iago
On Wed, 2014-06-11 at 21:25 +1200, Chris Forbes wrote:
This is pretty weird.
We should be able to generate a normal
Fixes the piglit test:
spec/glsl-1.50/compiler/interface-blocks-structs-defined-within-block-instanced.vert
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/ast_to_hir.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
Ping.
This has been broken for ages, and at least tesseract is carrying
hacks to work around it (extra color buffer containing depth values,
in their g-buffer). Getting rid of that wins us about 15%.
-- Chris
On Sat, Feb 8, 2014 at 3:54 PM, Chris Forbes chr...@ijw.co.nz wrote:
Previously, we
, Iago Toral ito...@igalia.com wrote:
Hi Chris,
On Sat, 2014-06-14 at 08:34 +1200, Chris Forbes wrote:
Right, this happens because ir_emit_vertex doesn't take a proper
operand, so it can't keep it alive.
What I think you want to do is change the stream in ir_emit_vertex and
ir_end_primitive
Sounds good to me.
On Thu, Jun 19, 2014 at 7:23 PM, Iago Toral ito...@igalia.com wrote:
On Wed, 2014-06-18 at 13:05 -0700, Ian Romanick wrote:
On 06/18/2014 02:51 AM, Iago Toral Quiroga wrote:
On Intel hardware when a geometry shader outputs GL_POINTS primitives we
only need to emit vertex
(but maybe in a separate patch)
On Thu, Jun 19, 2014 at 7:53 PM, Chris Forbes chr...@ijw.co.nz wrote:
Sounds good to me.
On Thu, Jun 19, 2014 at 7:23 PM, Iago Toral ito...@igalia.com wrote:
On Wed, 2014-06-18 at 13:05 -0700, Ian Romanick wrote:
On 06/18/2014 02:51 AM, Iago Toral Quiroga
This looks like it's adding a pile of uniform scanning overhead even
to draws which don't need the feature. Can we stash the index we need
earlier?
On Sat, Jun 21, 2014 at 1:01 PM, Ian Romanick i...@freedesktop.org wrote:
From: Ian Romanick ian.d.roman...@intel.com
Signed-off-by: Ian Romanick
This will be broken for indirect draws too, and possibly
performance-crippling to fix there, since we don't have the baseVertex
value available to shove into a uniform.
On Sun, Jun 22, 2014 at 3:36 AM, Roland Scheidegger srol...@vmware.com wrote:
Am 21.06.2014 03:00, schrieb Ian Romanick:
This
are kinda
required there.
Marek
On Sun, Jun 22, 2014 at 12:27 AM, Chris Forbes chr...@ijw.co.nz wrote:
This will be broken for indirect draws too, and possibly
performance-crippling to fix there, since we don't have the baseVertex
value available to shove into a uniform.
On Sun, Jun 22
Reviewed-by: Chris Forbes chr...@ijw.co.nz
Have you got a case where this makes a noticeable difference to performance?
On Mon, Jun 23, 2014 at 5:27 PM, Kenneth Graunke kenn...@whitecape.org wrote:
On i965, enabling and disabling the GS is not free: you have to do a
full pipeline stall
It looks like you can have the SOL stage increment that counter even
when not doing any actual streamout, which should give you the correct
semantics.
See the definition of 3DSTATE_STREAMOUT in the Haswell PRM, Volume 2b. You want:
- dw1.31 SO Function Enable = 1
- dw1.25 SO Statistics Enable =
I sent comments on patch 18 - I think it can be made to work correctly
when not doing real SO.
It seems everyone allows EmitStreamVertex(0), so I think you should
follow suit. It would be nice to get the spec clarified to explicitly
allow this.
Patches 11, 12 and 21 are:
Reviewed-by: Chris
filtered by dw1.27-28 Render Stream Select.
On Tue, Jun 24, 2014 at 9:53 PM, Chris Forbes chr...@ijw.co.nz wrote:
It looks like you can have the SOL stage increment that counter even
when not doing any actual streamout, which should give you the correct
semantics.
See the definition
As an alternative -- we know if we have this scenario at link time --
could we perhaps just not do anything in EmitStreamVertex if there are
no varyings captured to that stream?
On Thu, Jun 26, 2014 at 10:26 PM, Iago Toral ito...@igalia.com wrote:
Hello,
while testing various scenarios for
at 08:08 +1200, Chris Forbes wrote:
As an alternative -- we know if we have this scenario at link time --
could we perhaps just not do anything in EmitStreamVertex if there are
no varyings captured to that stream?
On Thu, Jun 26, 2014 at 10:26 PM, Iago Toral ito...@igalia.com wrote:
Hello
If another layout qualifier appeared to the left of `invocations` in the
GS input layout declaration, the invocation count would be dropped on
the floor.
Fixes the piglit test:
spec/ARB_transform_feedback3/arb_transform_feedback3-ext_interleaved_two_bufs_gs_max
Signed-off-by: Chris Forbes chr
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Thu, Jun 26, 2014 at 6:24 PM, Iago Toral Quiroga ito...@igalia.com wrote:
So far we have been using CL_INVOCATION_COUNT to resolve this query but this
is no good with streams, as only stream 0 reaches the clipping stage. Instead
we will use
Ilia,
That bikeshed is already done :)
I just send an r-b for v3 of patch 18, which is the last patch that lacked one.
I think this is all good to land now.
-- Chris
On Sat, Jun 28, 2014 at 5:11 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
Iago,
Not sure where you are with these patches...
Also fixes
spec/ARB_gpu_shader5/execution/invocations-conflicting
Apparently my baseline... wasnt.
On Sat, Jun 28, 2014 at 11:18 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Fri, Jun 27, 2014 at 5:21 AM, Chris Forbes chr...@ijw.co.nz wrote:
If another layout qualifier appeared to the left
On Sat, Jun 28, 2014 at 10:19 AM, Jason Ekstrand ja...@jlekstrand.net wrote:
@@ -653,135 +613,6 @@ _swrast_texture_span( struct gl_context *ctx, SWspan
*span )
[snip]
-
- /*
-* Must do all texture sampling before combining in order to
-* accomodate GL_ARB_texture_env_crossbar.
On Tue, Jul 1, 2014 at 9:40 AM, Matt Turner matts...@gmail.com wrote:
/** Fixed brw_reg. */
@@ -452,7 +452,7 @@ fs_reg::equals(const fs_reg r) const
memcmp(fixed_hw_reg, r.fixed_hw_reg,
sizeof(fixed_hw_reg)) == 0
stride == r.stride
-
Assuming this causes no piglit regressions,
Reviewed-by: Chris Forbes chr...@ijw.co.nz
Can we get some piglits which demonstrate these problems? oglconform
is too secret.
On Wed, Jul 2, 2014 at 10:54 PM, Popov, Pavel E pavel.e.po...@intel.com wrote:
Hi Chris,
Could you review this patch
These were looking in the wrong field.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index cd5bc9f
- Don't try to disassemble send's src1 as a descriptor if it's not an
immediate.
- In the same case, show src1 as an operand (makes it easier to see
bogus register regions, etc -- the hardware is very fussy)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965
We'd otherwise go looking into virtual_grf_sizes for things that aren't
in there at all.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src
I think you want to move the memset after the !annotation-ann bail
out. Currently, if that allocation were to fail (and we care enough to
check...) , you'll segfault.
On Wed, Jul 9, 2014 at 3:44 PM, Matt Turner matts...@gmail.com wrote:
Otherwise we'd compare uninitialized pointers with NULL and
After a bunch of experiments with lowering schemes, I've come full circle, back
to pretty much the same design as the RFC patches sent out some time ago.
This series adds support for the ir_*_interpolate_at_* expression types in the
i965 driver. The corresponding glsl parts have already landed.
The backend will have to do a message send, so we want to keep these in
one piece, just like texture ops.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
.../dri/i965/brw_fs_channel_expressions.cpp| 25 ++
1 file changed, 25 insertions(+)
diff --git a/src/mesa
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_eu.h | 10
src/mesa/drivers/dri/i965/brw_eu_emit.c | 43 +
2 files changed, 53 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965
These got lost in the big brw_inst shakeup.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_defines.h | 5 +
src/mesa/drivers/dri/i965/brw_inst.h| 11 +++
2 files changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b
SIMD8-only for now.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 135 ++-
2 files changed, 134 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
V3: Rework for brw_inst changes
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_disasm.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index f37da19..d7362c1
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_defines.h| 1 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 ++
src/mesa/drivers/dri/i965/brw_fs.h | 4
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 19 +++
src
Yeah, I can inline brw_set_pixel_interpolator_query_message into its one caller.
On Sat, Jul 12, 2014 at 6:56 PM, Kenneth Graunke kenn...@whitecape.org wrote:
On Saturday, July 12, 2014 03:20:12 PM Chris Forbes wrote:
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu.h | 10 ++
src/mesa/drivers/dri/i965/brw_eu_emit.c | 28
2 files changed, 38 insertions(+)
diff --git a/src/mesa/drivers
The backend will have to do a message send, so we want to keep these in
one piece, just like texture ops.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
.../dri/i965/brw_fs_channel_expressions.cpp| 25 ++
1 file
V5: - Split into separate opcodes
- Pass message data in src1 immediate
- Put noperspective bit in fs_inst rather than adding any junk to
backend_instruction
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_defines.h| 4 +++
src/mesa/drivers
V3: Rework for brw_inst changes
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_disasm.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa
These got lost in the big brw_inst shakeup.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h | 5 +
src/mesa/drivers/dri/i965/brw_inst.h| 11 +++
2 files changed, 16 insertions(+)
diff
Here's a new version of the series incorporating the review feedback from
earlier today.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
SIMD8-only for now.
V5: - Fix style complaints
- Move prototype to be with other oddball emit functions
- Use unreachable() instead of assert() where possible
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +
src/mesa/drivers/dri/i965
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/lower_ubo_reference.cpp | 50
1 file changed, 30 insertions(+), 20 deletions(-)
diff --git a/src/glsl/lower_ubo_reference.cpp b/src/glsl/lower_ubo_reference.cpp
index c49ae34..80edd93 100644
Previously this was a block index with special semantics for -1.
With ARB_gpu_shader5, this need not be a compile-time constant, so
allow any rvalue here and convert the -1 to a NULL pointer.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/lower_ubo_reference.cpp | 15
This series adds various relaxations and extra plumbing to allow indexing
arrays of uniform blocks with dynamically uniform expressions rather than
only constant expressions.
Covers only the GLSL part -- there are still a few loose ends in the
corresponding i965 patches, so I'll send that support
Without doing a lot more work, we have no idea which indices may
be used at runtime, so just mark them all.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/link_uniform_block_active_visitor.cpp | 51 --
1 file changed, 32 insertions(+), 19 deletions(-)
diff
Instead of falling back to just the block name (which we won't find),
look for the first element of the block array. We'll deal with the rest
in the backend by arranging for the blocks to be laid out contiguously.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/lower_ubo_reference.cpp
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/ast_array_index.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_index.cpp
index f3b060e..50f9987 100644
--- a/src/glsl/ast_array_index.cpp
+++ b/src/glsl
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/ir_validate.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index 42142da..74ae318 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -495,7 +495,6
Accidentally replied privately only, sorry.
-- Forwarded message --
From: Chris Forbes chr...@ijw.co.nz
Date: Tue, Jul 15, 2014 at 10:27 PM
Subject: Re: [Mesa-dev] [PATCH 2/6] glsl: Mark entire UBO array active
if indexed with non-constant.
To: Ilia Mirkin imir...@alum.mit.edu
Indeed, will fix.
On Tue, Jul 15, 2014 at 10:24 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Sat, Jul 12, 2014 at 9:51 PM, Chris Forbes chr...@ijw.co.nz wrote:
Previously this was a block index with special semantics for -1.
With ARB_gpu_shader5, this need not be a compile-time constant, so
Oh dear. This hunk should have been squashed together with the change
to it later. By itself, it doesn't get us anywhere.
On Tue, Jul 15, 2014 at 10:26 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Sat, Jul 12, 2014 at 9:51 PM, Chris Forbes chr...@ijw.co.nz wrote:
Instead of falling back
It's still started though -- there's a partial implementation in master.
On Wed, Jul 23, 2014 at 10:30 AM, Dave Airlie airl...@gmail.com wrote:
It appears Paul isn't working on this.
Signed-off-by: Dave Airlie airl...@redhat.com
---
docs/GL3.txt | 2 +-
1 file changed, 1 insertion(+), 1
These are
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Fri, Jul 25, 2014 at 11:04 AM, Jordan Justen jljus...@gmail.com wrote:
On Thu, Jul 24, 2014 at 3:56 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Thu, Jul 24, 2014 at 6:44 PM, Jordan Justen
jordan.l.jus...@intel.com wrote:
This fixes
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 29 +++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 174 +++--
1 file changed, 135 insertions(+), 39 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index
We're about to be using this infrastructure to build descriptors in
src1 of non-send instructions, when preparing to do an indirect send.
Don't accidentally clobber the conditionalmod field of those
instructions with SFID bits, which aren't part of the descriptor.
Signed-off-by: Chris Forbes chr
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 30 +---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 77 +++-
1 file changed, 62 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
This provides a reasonable place to enforce the hardware restriction
that indirect descriptors must be in a0.0
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_eu.h | 5 +
src/mesa/drivers/dri/i965/brw_eu_emit.c | 15 +++
2 files changed, 20
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
docs/GL3.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index e241257..b90f4ca 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -102,7 +102,7 @@ GL 4.0:
GL_ARB_gpu_shader5
Since we were just discussing this in IRC,
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Mon, Aug 4, 2014 at 6:54 PM, Kenneth Graunke kenn...@whitecape.org wrote:
We have a CPU-side implementation of conditional rendering; it really
should be done on the GPU. It's not necessarily that hard
Reduces duplication, and will do so even more when we change the sampler
plumbing.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 31
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri
Reduces duplication, and will do so even more when we change the sampler
plumbing.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 31 ++--
1 file changed, 11 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri
Previously sampler indices were stored in a dedicated field of
backend_instruction. This series reworks them to be passed as the src1 operand,
mirroring how we deal with
UBO accesses, etc.
This is required in order to relax the restriction that sampler array indices
be constant expressions.
---
src/mesa/drivers/dri/i965/brw_fs.h | 15 +++---
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 29 ++--
3 files changed, 25 insertions(+), 23 deletions(-)
diff --git
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs.h | 3 ++-
src/mesa/drivers/dri/i965/gen8_fs_generator.cpp | 18 --
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs.h | 3 ++-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 18 --
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index c1676a9..7d4b327 100644
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 38 --
1 file changed, 12 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.h | 6 +++---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 12
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers
The generators no longer use this.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 1 -
src/mesa/drivers/dri/i965/brw_fs.cpp| 1 -
src/mesa/drivers/dri/i965/brw_fs_cse.cpp| 1 -
src/mesa/drivers/dri/i965/brw_fs_fp.cpp
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.h | 3 ++-
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 19 +--
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.h | 5 +++--
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 18 --
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Fri, Jul 25, 2014 at 6:40 PM, Tapani Pälli tapani.pa...@intel.com wrote:
This patch fixes regressions caused by commit 48deb4d. Regressions
happened because 'run_default' var did not initialized when default
case was the last one.
Now all
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Wed, Aug 6, 2014 at 6:57 PM, Kenneth Graunke kenn...@whitecape.org wrote:
Due to the destination register width of 1 or 2, these instructions get
ExecSize 1 or 2. But dir and offset (used as src0) are both registers
of width 4, violating
Yes -- there's no interaction between patches 3 and 4. Blorp only
shares the generator.
On Tue, Aug 5, 2014 at 1:32 PM, Ian Romanick i...@freedesktop.org wrote:
Does it still build with patch 3 without patch 4?
On 08/04/2014 01:58 AM, Chris Forbes wrote:
Signed-off-by: Chris Forbes chr
Does this actually work on all Gen7?
The IVB PRM Vol 4 Part 1 Page 83 says:
Errata: BC6H_SF16, BC6H_UF16, and BC7_SRGB are not supported and
may result in data corruption if used.
On Thu, Aug 7, 2014 at 4:27 AM, Neil Roberts n...@linux.intel.com wrote:
Here is a v2 of the BPTC texture
OK, assuming no one complains, I'll push the series later today.
On Thu, Aug 7, 2014 at 8:44 AM, Ian Romanick i...@freedesktop.org wrote:
On 08/06/2014 12:40 PM, Chris Forbes wrote:
Yes -- there's no interaction between patches 3 and 4. Blorp only
shares the generator.
Okay. Then these two
The last big piece of ARB_gpu_shader5!
This series adds support for using dynamically uniform expressions
in sampler array indexing, as required by ARB_gpu_shader5. Gen7 is
supported (including Haswell's high samplers). Gen8 support would
be a straightforward addition for someone who has access
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/ast_array_index.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_index.cpp
index 50f9987..f8dca80 100644
--- a/src/glsl/ast_array_index.cpp
+++ b/src/glsl
If the array index is not a constant expression, the existing support
will assume a zero offset (giving us the sampler index of the base of
the array).
For dynamically uniform indexing of sampler arrays, we need both that
and the indexing expression.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
For now, assume that the addressed sampler can be in any of the
16-sampler banks. If we preserved range information this far, we
could avoid emitting these instructions if the sampler were known
to be contained within one bank.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 52 +++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index
---
src/mesa/drivers/dri/i965/brw_vec4.h | 2 +-
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 53 +++---
2 files changed, 49 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 47 +---
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_eu.h | 5
src/mesa/drivers/dri/i965/brw_eu_emit.c | 35
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 17 +---
3 files changed, 41 insertions(+), 16
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 52 +-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs.h | 4 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 60
2 files changed, 55 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 17 +
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 28b3525
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 47 ++
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
docs/GL3.txt | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 65facf5..29535ec 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -94,18 +94,18 @@ GL 4.0, GLSL 4.00
[Applies on top of the dynamically uniform UBO indexing and sampler
indexing series sent to the list recently]
All the pieces are now in place for ARB_gpu_shader5 on
Ivybridge/Baytrail/Haswell, and Broadwell is close.
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