[Mesa-dev] [RFC] r600/evergreen compute shader + glsl 4.30 support

This set of patches enables compute shaders on r600 and exposes GLSL 4.30 support. They are pretty alpha level, but I'd like to land some of them (maybe disabled) so I can avoid the rebasing fun with the more intrusive ones. It is based on the previous ssbo support patch. It may not be stable, I

[Mesa-dev] [PATCH 18/21] r600: handle image/buffer sizes correctly.

From: Dave Airlie <airl...@redhat.com> This adds support to compute for the resq workarounds (buffer/cube sizes) Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/evergreen_compute.c | 7 +++ src/gallium/drivers/r600/r600_pipe.h | 2 ++

[Mesa-dev] [PATCH 01/21] st/mesa: handle compute atomics

From: Dave Airlie <airl...@redhat.com> Just reuse the cs atomics bit and emit the hw atomic state. --- src/mesa/state_tracker/st_atom_atomicbuf.c | 4 src/mesa/state_tracker/st_context.c| 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/state_t

[Mesa-dev] [PATCH 02/21] r600: add support for compute pkt flags to debug dumping.

From: Dave Airlie <airl...@redhat.com> This just lets us see packets marked for compute. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/eg_debug.c | 13 +++-- 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/r60

[Mesa-dev] [PATCH 07/21] r600: handle compute null key shader state

From: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_state_common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index b6a4728..e312b33 100644 --- a/src/gallium/driver

[Mesa-dev] [PATCH] r600: add ARB_shader_storage_buffer_object support (v3)

From: Dave Airlie <airl...@redhat.com> This just builds on the image support. Evergreen only has ssbo for fragment and compute no other stages. v2: handle images and ssbo in the same shader properly (Ilia) v3: fix RESQ on buffers, fix missing atom emit fix first element offset

[Mesa-dev] [PATCH] r600: fix bfe where src/dst are same.

From: Dave Airlie <airl...@redhat.com> This fixes overlaps where src/dst are the same. Fixes a bunch of the deqp bitfield tests. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 29 - 1 file changed, 24 inse

[Mesa-dev] [PATCH 2/2] vulkan/wsi: drop local_fd parameter from lots of places.

From: Dave Airlie <airl...@redhat.com> this won't change over the driver lifetime, so just set it in the wsi_device at init, and avoid passing it around afterwards. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_wsi.c | 3 +-- src/amd/vulkan/ra

[Mesa-dev] [PATCH 1/2] vulkan/wsi: drop can handle different gpu from the x11 interfaces

From: Dave Airlie <airl...@redhat.com> Jason dropped this elsewhere, just seemed to miss here. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_wsi_x11.c | 4 ++-- src/intel/vulkan/anv_wsi_x11.c | 4 ++-- src/vulkan/wsi/wsi_common_x11.c | 5 - sr

Re: [Mesa-dev] [PATCH v2 00/32] vulkan/wsi: Rework WSI to look a lot more like a layer

Daniel or Chad to look some of it over, but I'm happy to give Reviewed-by: Dave Airlie <airl...@redhat.com> for the whole series, it really makes the WSI and prime into a contained space, and is what I wished the initial modifier series had looked like :-) Dave. _

[Mesa-dev] [PATCH] r600/cayman: looks like cmpxchg moved to Z

From: Dave Airlie <airl...@redhat.com> On cayman it appears the cmp component is now in Z. Fixes: arb_shader_image_load_store-dead-fragments on cayman. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 7 +-- 1 file changed, 5 inse

[Mesa-dev] [PATCH] r600/sb: handle jump after target to end of program. (v2)

From: Dave Airlie <airl...@redhat.com> This fixes hangs on cayman with tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test This has a single if/else in it, and when this peephole activated, it would set the jump target to NULL if there was no instruction

[Mesa-dev] [PATCH] r600/sb: handle jump after target to end of program.

From: Dave Airlie <airl...@redhat.com> This fixes hangs on cayman with tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test This has a single if/else in it, and when this peephole activated, it would set the jump target to NULL if there was no instruction

Re: [Mesa-dev] [PATCH] r600: set DX10_CLAMP for compute shader too

in a different source file...). Reviewed-by: Dave Airlie <airl...@redhat.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/2] ac/nir: don't write tcs outputs to LDS that aren't read back.

From: Dave Airlie <airl...@redhat.com> If the TCS doesn't read back the outputs, no need to store them to LDS in the first place. (except for tess factors). This seems to give about 50fps (3290->3330) with tessellation demo. I haven't tested if it impacts DoW3 at all. Signed-off

[Mesa-dev] [PATCH 1/2] nir: fill outputs_read field and add patch outputs read (v2)

From: Dave Airlie <airl...@redhat.com> This is to be used for TCS optimisations on radv. v2: don't set written on reads (nha) --- src/compiler/nir/nir_gather_info.c | 40 ++ src/compiler/shader_info.h | 2 ++ 2 files changed, 30 insertions(

[Mesa-dev] [PATCH] r600: add cull distance support

From: Dave Airlie <airl...@redhat.com> This passes all the tests in piglit. Signed-off-by: Dave Airlie <airl...@redhat.com> --- docs/features.txt| 2 +- docs/relnotes/17.4.0.html| 1 + src/gallium/drivers/r600/evergreen_state.c |

[Mesa-dev] [PATCH] r600: add ARB_shader_storage_buffer_object support (v2)

From: Dave Airlie <airl...@redhat.com> This just builds on the image support. Evergreen only has ssbo for fragment and compute no other stages. v2: handle images and ssbo in the same shader properly (Ilia) --- docs/features.txt| 4 +- src/gallium/driver

[Mesa-dev] [PATCH 2/2] r600: add ARB_shader_storage_buffer_object support

From: Dave Airlie <airl...@redhat.com> This just builds on the image support. Evergreen only has ssbo for fragment and compute no other stages. --- docs/features.txt| 4 +- src/gallium/drivers/r600/evergreen_state.c | 131 ++- src/g

[Mesa-dev] [PATCH 1/2] st/mesa: don't move ssbo after atomic buffers if we support hw atomics

From: Dave Airlie <airl...@redhat.com> There is no need to have these overlap if we support hw atomics. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/mesa/state_tracker/st_atom_storagebuf.c | 8 +--- src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 14 -- 2 f

Re: [Mesa-dev] [PATCH] svga: add missing PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER* cases

On 17 November 2017 at 09:41, Charmaine Lee <charmai...@vmware.com> wrote: > > Reviewed-by: Charmaine Lee <charmai...@vmware.com> > Oops, Acked-by: Dave Airlie <airl...@redhat.com> > > From: Brian Paul <bri...@vmwar

Re: [Mesa-dev] [PATCH] r600: shader CF_OP_VTX also doesn't use the EOP bit.

On 17 November 2017 at 08:00, Gert Wollny <gw.foss...@gmail.com> wrote: > Am Mittwoch, den 15.11.2017, 11:28 +1000 schrieb Dave Airlie: >> On 15 November 2017 at 04:50, Gert Wollny <gw.foss...@gmail.com> >> wrote: >> > Although the EOP bit is do

[Mesa-dev] [PATCH] radv: get rid of another api bypass in the wsi code.

From: Dave Airlie <airl...@redhat.com> This just uses the vulkan api to get the fd from the memory. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_wsi.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/amd/vulkan/radv

[Mesa-dev] [PATCH] radv/wsi: don't use a helper for blit, just call copy image.

From: Dave Airlie <airl...@redhat.com> We ignore layout currently, not sure what would be correct to pass. (this is based on Jason's last wsi rfc) Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_meta.h | 4 src/amd/vulkan/radv_meta

[Mesa-dev] [PATCH] vulkan/wsi: use function ptr definitions from the spec.

From: Dave Airlie <airl...@redhat.com> This just seems cleaner, and we may expand this in future. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_wsi.c | 3 ++- src/intel/vulkan/anv_wsi.c | 3 ++- src/vulkan/wsi/wsi_common.h |

Re: [Mesa-dev] [PATCH 3/3] RFC: vulkan/wsi: Rework the way prime support works

adv and, in my opinion, > actually makes the radv code more straightforward. For the record, PRIME is not radv specific, stop trying to make it so, anv should support display to other GPUs. I've tested these patches work and I'm only acking them because nobody seems to be listening to my object

Re: [Mesa-dev] [PATCH] r600: shader CF_OP_VTX also doesn't use the EOP bit.

On 15 November 2017 at 04:50, Gert Wollny wrote: > Although the EOP bit is documented for the vertex fetch clause, it is not > properly interpreted. As a result the piglit > spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs > creates a TESS_EVAL shader

[Mesa-dev] [PATCH] r600: don't emit vfetch if tess eval isn't accessing any inputs.

From: Dave Airlie <airl...@redhat.com> This should avoid emitting anything in the shader if we aren't accessing any inputs. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[Mesa-dev] [PATCH 11/11] docs: update features/relnotes for r600 shader image support.

From: Dave Airlie <airl...@redhat.com> Signed-off-by: Dave Airlie <airl...@redhat.com> --- docs/features.txt | 14 +++--- docs/relnotes/17.4.0.html | 2 ++ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index 86d0

[Mesa-dev] [PATCH 05/11] r600/shader: implement getting thread id.

From: Dave Airlie <airl...@redhat.com> We need the thread id to use the immediate buffer readback mechanism, so add support for calculating it. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 74 ++ 1 file

[Mesa-dev] [PATCH 02/11] r600: allocate immed buffer resource for images.

From: Dave Airlie <airl...@redhat.com> In order to image readback we have to execute a MEM_RAT instruction that needs a buffer to transfer the result into until the shader can fetch it. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_buffer_c

[Mesa-dev] [PATCH 08/11] r600/sb: disable SB for images.

From: Dave Airlie <airl...@redhat.com> Until we can work further on sb, disable it for images for now. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/r600/r600_sha

[Mesa-dev] [PATCH 10/11] r600: enable ARB_shader_image_load_store, ARB_shader_image_size

From: Dave Airlie <airl...@redhat.com> This also enables GL4.2 for gpus with hw fp64 (cayman, cypress) Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_pipe.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/gal

[Mesa-dev] [PATCH 03/11] r600: implement basic memory barrier.

From: Dave Airlie <airl...@redhat.com> This isn't 100% perfect (fglrx also fails a bunch of those tests) but implement the start of a memory barrier for image support. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_pipe_common.c | 5 -

[Mesa-dev] [PATCH 07/11] r600/shader: add support for load/store/atomic ops on images.

From: Dave Airlie <airl...@redhat.com> This adds support to the shader assembler for load/store/atomic ops on images which are handled via the RAT operations. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 316

[Mesa-dev] [PATCH 01/11] r600: handle writes_memory properly

From: Dave Airlie <airl...@redhat.com> This implements proper handling for shaders with side effects. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/evergreen_state.c | 10 +++--- src/gallium/drivers/r600/evergreend.h | 6 ++ 2 files

[Mesa-dev] [PATCH 09/11] r600: handle image size support.

From: Dave Airlie <airl...@redhat.com> This adds support for the RESQ opcode with the workaround required due to hw bugs for buffers and cube arrays. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 78 ++--

[Mesa-dev] [PATCH 04/11] r600/shader: add flag to denote if shader uses images

From: Dave Airlie <airl...@redhat.com> Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 1 + src/gallium/drivers/r600/r600_shader.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/

[Mesa-dev] [PATCH 06/11] r600: add core pieces of image support.

From: Dave Airlie <airl...@redhat.com> This adds the atoms and gallium api implementations, along with support for compress/decompress paths for shader images. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/evergreen_state.c | 294

[Mesa-dev] r600 evergreen+ shader image support

I've been hacking on this on/off for quite a while now, and I think I'm finally happy with where is has reached. It's not 100% on piglits, but it's quite close, and better than fglrx does, so I'd probably prefer to land it before doing too much more destructive hacking on it! If you have a

Re: [Mesa-dev] [PATCH 1/2] r600/shader: reserve first register of vertex shader.

On 15 November 2017 at 01:12, Andres Gomez wrote: > Dave, this nominated patch landed without mentioning any specific > stable queue. > > From what I'm seeing, they depend on ea1b97714d9b which didn't make it > for 17.2 so I'm dropping it for that queue. > > Let me know what

[Mesa-dev] [PATCH] r600: fix cubemap arrays

From: Dave Airlie <airl...@redhat.com> A lot of cubemap array piglits fail, port the texture type picking code from radeonsi which seems to fix most of them. For images I will port the rest of the code. Fixes: getteximage-depth gl_texture_cube_map_array-* fbo-generatemipmap-cubemap

[Mesa-dev] [PATCH 1/2] nir: fill outputs_read field and add patch outputs read

From: Dave Airlie <airl...@redhat.com> This is to be used for TCS optimisations on radv. --- src/compiler/nir/nir_gather_info.c | 29 ++--- src/compiler/shader_info.h | 2 ++ 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/src/compil

[Mesa-dev] [PATCH 2/2] ac/nir: don't write tcs outputs to LDS that aren't read back.

From: Dave Airlie <airl...@redhat.com> If the TCS doesn't read back the outputs, no need to store them to LDS in the first place. (except for tess factors). This seems to give about 50fps (3290->3330) with tessellation demo. I haven't tested if it impacts DoW3 at all. Signed-off

Re: [Mesa-dev] [PATCH 1/2] radv: Free syncobj with multiple imports.

Reviewed-by: Dave Airlie <airl...@redhat.com> On 14 November 2017 at 09:45, Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> wrote: > Otherwise we can leak the old syncobj. > > Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)" > --- &g

[Mesa-dev] [PATCH] radv: it isn't an error to not support a format or driver

From: Dave Airlie <airl...@redhat.com> This reverts two of the vk_error changes: reporting unsupported format is common, and testing non-amdgpu drivers and ignoring them is also common. Fixes: cd64a4f70 (radv: use vk_error() everywhere an error is returned) Signed-off-by: Dave Airlie

[Mesa-dev] [PATCH] virgl: also remove dimension on indirect.

From: Dave Airlie <airl...@redhat.com> This fixes some dEQP tests that generated bad shaders. Fixes: b6f6ead19 (virgl: drop const dimensions on first block.) Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/virgl/virgl_tgsi.c | 1 - 1 file changed, 1 delet

[Mesa-dev] [PATCH] r600/shader: handle bitfield extract semantics properly.

From: Dave Airlie <airl...@redhat.com> Fixes: tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldExtract.shader_test Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 57 +++--- 1 file changed, 5

[Mesa-dev] [PATCH] r600: handle bitfieldInsert corner case.

From: Dave Airlie <airl...@redhat.com> This handles the bits >= 32 corner case in bitfieldInsert. Fixes: tests/spec/arb_gpu_shader5/execution/built-in-functions/fs-bitfieldInsert.shader_test. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r60

[Mesa-dev] [PATCH] r600: fix isoline tess factor component swapping.

From: Dave Airlie <airl...@redhat.com> As per radeonsi, the tess factor components for isolines are reversed. Fixes: tests/spec/arb_tessellation_shader/execution/isoline.shader_test Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_shader.c | 7 +++

[Mesa-dev] [PATCH 1/2] r600/shader: reserve first register of vertex shader.

From: Dave Airlie <airl...@redhat.com> r0 in input into vertex shaders contains things like vertexid, we need to reserve it even if we have no inputs. This fixes a bunch of tessellation piglits. --- src/gallium/drivers/r600/r600_shader.c | 6 -- 1 file changed, 4 insertions(+), 2 del

[Mesa-dev] [PATCH 2/2] r600: add gs tri strip adjacency fix.

From: Dave Airlie <airl...@redhat.com> Like radeonsi: generate GS prolog to (partially) fix triangle strip adjacency rotation evergreen hw suffers from the same problem, so rotate the geometry inputs to fix this. This fixes: ./bin/glsl-1.50-geometry-primitive-types GL_TRIANGLE_STRIP_ADJ

[Mesa-dev] [PATCH] r600: don't emit atomic save if we have no atomic counters.

From: Dave Airlie <airl...@redhat.com> Otherwise we end up emitting the fence. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/evergreen_state.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gal

[Mesa-dev] [PATCH] r600/query: drop rest of vi workaround code.

From: Dave Airlie <airl...@redhat.com> This isn't needed in r600 anymore. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/drivers/r600/r600_query.c | 46 ++- src/gallium/drivers/r600/r600_query.h | 4 --- 2 files changed, 13 inser

Re: [Mesa-dev] [PATCH 7/9] st/mesa: add support for hw atomics to glsl->tgsi. (v4)

On 9 November 2017 at 11:54, Dave Airlie <airl...@gmail.com> wrote: > From: Dave Airlie <airl...@redhat.com> > > This adds support for creating the hw atomic tgsi from > the glsl codepaths. > > v2: drop the atomic index and move to backend. > v3: drop buffer de

[Mesa-dev] [PATCH 5/9] st/mesa: start adding support for hw atomics atom. (v2)

From: Dave Airlie <airl...@redhat.com> This adds a new atom that calls the new driver API to bind buffers containing hw atomics. v2: fixup bindings for sparse buffers. (mareko/nha) don't bind buffer atomics when hw atomics are enabled. use NewAtomicBuffer (mareko) Signed-off-by: Dave

[Mesa-dev] [PATCH 8/9] r600: add support for hw atomic counters. (v3)

From: Dave Airlie <airl...@redhat.com> This adds support for the evergreen/cayman atomic counters. These are implemented using GDS append/consume counters. The values for each counter are loaded before drawing and saved after each draw using special CP packets. v2: move hw atomic assi

[Mesa-dev] [PATCH 9/9] docs: update r600 atomic counter status.

From: Dave Airlie <airl...@redhat.com> Signed-off-by: Dave Airlie <airl...@redhat.com> --- docs/features.txt | 6 +++--- docs/relnotes/17.4.0.html | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index 10ccf9d..86

[Mesa-dev] [PATCH 6/9] st/mesa: setup hw atomic limits. (v1.1)

From: Dave Airlie <airl...@redhat.com> HW atomics need to use caps to set some limits, and some other limits may also need limiting. This fixes things up to work for evergreen hw, it may need more changes in the future if other hw wants to use this path. v1.1: fix indent. Reviewed-by: N

[Mesa-dev] [PATCH 3/9] gallium: add hw atomic buffer binding API.

From: Dave Airlie <airl...@redhat.com> This API binds atomic buffers for all bound shaders (as per the GL semantics). This is needed to support cross shader hw atomic counters. Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> Reviewed-by: Marek Olšák <marek.ol...@amd.

[Mesa-dev] [PATCH 7/9] st/mesa: add support for hw atomics to glsl->tgsi. (v4)

From: Dave Airlie <airl...@redhat.com> This adds support for creating the hw atomic tgsi from the glsl codepaths. v2: drop the atomic index and move to backend. v3: drop buffer decls. (Marek) v4: fix off by one (Gert) Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> Review

[Mesa-dev] [PATCH 2/9] gallium/tgsi: start adding hw atomics (v3.1)

From: Dave Airlie <airl...@redhat.com> This adds support for a hw atomic counters to TGSI. A new register file for storing atomic counters is added, along with a new atomic counter semantic, along with docs for both. v2: drop semantic, move hw counter to backend, Ilia pointed out SSO woul

[Mesa-dev] [PATCH 4/9] mesa/program: add hw atomic counter file

From: Dave Airlie <airl...@redhat.com> This is needed for the GLSL->TGSI translation for hw atomic counters. Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> Reviewed-by: Marek Olšák <marek.ol...@amd.com> Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/

[Mesa-dev] gallium/r600 atomic - v4

Hopefully last pass, a few fixes in here, patch 5 is the only outstanding non-reviewed one, I think I've fixed the sparse buffer binding in it well enough, there is also fix for Gert's off-by one. Dave. ___ mesa-dev mailing list

[Mesa-dev] [PATCH 1/9] gallium: add CAPs to support HW atomic counters. (v3)

From: Dave Airlie <airl...@redhat.com> This looks like an evergreen specific feature, but with atomic counters AMD have hw specific counters they use instead of operating on buffers directly. These are separate to the buffer atomics, so require different limits and code paths. I've left t

Re: [Mesa-dev] gallium/r600 hw atomic support (v3)

On 7 November 2017 at 20:45, Gert Wollny <gw.foss...@gmail.com> wrote: > Am Dienstag, den 07.11.2017, 16:30 +1000 schrieb Dave Airlie: >> This is the 3rd submission of the gallium/r600 hw atomic counter >> support. >> >> This is fixes some rebase artifac

[Mesa-dev] [PATCH] ac/nir: add support for all intrinsics. (v2)

From: Dave Airlie <airl...@redhat.com> This is derived from tgsi/radeonsi code from the GLSL intrinsics. This should pre-fix radv for the upcoming spirv patches. v2: actually use wait_cnt, sleep deprived dad time! (Bas) Signed-off-by: Dave Airlie <airl...@redhat.com> --- sr

[Mesa-dev] [PATCH] ac/nir: add support for all intrinsics.

From: Dave Airlie <airl...@redhat.com> This is derived from tgsi/radeonsi code from the GLSL intrinsics. This should pre-fix radv for the upcoming spirv patches. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/common/ac_nir_to_llvm.c | 32

Re: [Mesa-dev] [PATCH 8/8] r600: add support for hw atomic counters. (v3)

On 8 November 2017 at 03:26, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > On 07.11.2017 07:31, Dave Airlie wrote: >> >> From: Dave Airlie <airl...@redhat.com> >> >> This adds support for the evergreen/cayman atomic counters. >> >> These are implem

[Mesa-dev] [PATCH 7/8] st/mesa: add support for hw atomics to glsl->tgsi. (v3)

From: Dave Airlie <airl...@redhat.com> This adds support for creating the hw atomic tgsi from the glsl codepaths. v2: drop the atomic index and move to backend. v3: drop buffer decls. (Marek) Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/mesa/state_tracker/st_glsl_to_tg

[Mesa-dev] [PATCH 3/8] gallium: add hw atomic buffer binding API.

From: Dave Airlie <airl...@redhat.com> This API binds atomic buffers for all bound shaders (as per the GL semantics). This is needed to support cross shader hw atomic counters. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/gallium/docs/source/context.rst | 8

[Mesa-dev] [PATCH 6/8] st/mesa: setup hw atomic limits. (v1.1)

From: Dave Airlie <airl...@redhat.com> HW atomics need to use caps to set some limits, and some other limits may also need limiting. This fixes things up to work for evergreen hw, it may need more changes in the future if other hw wants to use this path. v1.1: fix indent. Reviewed-by: N

[Mesa-dev] [PATCH 1/8] gallium: add CAPs to support HW atomic counters. (v3)

From: Dave Airlie <airl...@redhat.com> This looks like an evergreen specific feature, but with atomic counters AMD have hw specific counters they use instead of operating on buffers directly. These are separate to the buffer atomics, so require different limits and code paths. I've left t

[Mesa-dev] [PATCH 5/8] st/mesa: start adding support for hw atomics atom.

From: Dave Airlie <airl...@redhat.com> This adds a new atom that calls the new driver API to bind buffers containing hw atomics. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/mesa/state_tracker/st_atom_atomicbuf.c | 37 src/mesa/s

[Mesa-dev] [PATCH 2/8] gallium/tgsi: start adding hw atomics (v3)

From: Dave Airlie <airl...@redhat.com> This adds support for a hw atomic counters to TGSI. A new register file for storing atomic counters is added, along with a new atomic counter semantic, along with docs for both. v2: drop semantic, move hw counter to backend, Ilia pointed out SSO woul

[Mesa-dev] [PATCH 8/8] r600: add support for hw atomic counters. (v3)

From: Dave Airlie <airl...@redhat.com> This adds support for the evergreen/cayman atomic counters. These are implemented using GDS append/consume counters. The values for each counter are loaded before drawing and saved after each draw using special CP packets. v2: move hw atomic assi

[Mesa-dev] gallium/r600 hw atomic support (v3)

This is the 3rd submission of the gallium/r600 hw atomic counter support. This is fixes some rebase artifacts, removes the BUFFER decls from the TGSI, and fixes some indirect crashes in the r600 backend, Dave. ___ mesa-dev mailing list

[Mesa-dev] [PATCH 4/8] mesa/program: add hw atomic counter file

From: Dave Airlie <airl...@redhat.com> This is needed for the GLSL->TGSI translation for hw atomic counters. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/mesa/main/mtypes.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main

[Mesa-dev] [PATCH] [rfc] radv: optimise bo descriptor updates for non-local bos.

From: Dave Airlie <airl...@redhat.com> This might be a bit over optimising. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 9 +++--- src/amd/vulkan/radv_descriptor_set.c | 55 +++- src/amd/vulkan/ra

[Mesa-dev] [PATCH] radv: pre-calculate user_data_0 registers and store in pipeline

From: Dave Airlie <airl...@redhat.com> There's no point recalculating these the whole time on descriptor emission, just store them at pipeline creation. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 14 ++-- src/amd/vulkan/radv_pipel

Re: [Mesa-dev] [PATCH 1/9] gallium: add CAPs to support HW atomic counters. (v2)

On 4 November 2017 at 10:01, Marek Olšák wrote: > Not sure if the "HW" prefix everywhere makes sense since gallium > doesn't imply there is a hardware driver behind it, but I don't really > care much. Well it's more that the atomic's aren't normal ssbo atomics, and there is

Re: [Mesa-dev] [PATCH 2/9] gallium/tgsi: start adding hw atomics (v2)

>> +Hardware Atomic Register File >> +^ >> + >> +Hardware atomics are declared as a 2D array with an optional array id. >> + >> +The first member of the dimension is the buffer resource the atomic >> +is located in. >> +The second member is a range into the buffer

Re: [Mesa-dev] [PATCH 8/9] r600: add support for hw atomic counters. (v2)

radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); >> + radeon_emit(cs, reloc); >> + } >> + ++rctx->append_fence_id; >> + reloc = radeon_add_to_buffer_list(>b, >b.gfx, >> + >> r600_resource(rctx->append_fence), >> +

[Mesa-dev] [PATCH] radv: keep a stage mask per pipeline. (v2)

From: Dave Airlie <airl...@redhat.com> This should reduce some pointless loops. v2: fix missing check which causes crashes with compute shaders Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 53 +++- sr

[Mesa-dev] [PATCH] radv: keep a stage mask per pipeline.

From: Dave Airlie <airl...@redhat.com> This should reduce some pointless loops. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 51 ++-- src/amd/vulkan/radv_pipeline.c | 2 ++ src/amd/vulkan/radv_priva

[Mesa-dev] [PATCH 1/2] radv: wrap cs_add_buffer in an inline.

From: Dave Airlie <airl...@redhat.com> The next patch will try and avoid calling the indirect function. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 40 ++-- src/amd/vulkan/radv_descriptor_set.c | 6 +++

[Mesa-dev] [PATCH 2/2] radv: move is_local up to the winsys level.

From: Dave Airlie <airl...@redhat.com> We can avoid adding the buffer in the non-local case, this will avoid all the overhead of the indirect call. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_radeon_winsys.h | 4 src/amd/vulkan/w

[Mesa-dev] [PATCH] radv: when loading regs no need to add buffer

From: Dave Airlie <airl...@redhat.com> The function that calls us has just added the buffer to the list already, no need to try and add it again. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 2 -- 1 file changed, 2 deletions(-) diff --g

[Mesa-dev] [PATCH 1/2] radv: move calculating vs out info regs into pipeline.

From: Dave Airlie <airl...@redhat.com> This moves some calculations of register values into the pipeline construction, it saves looking at outinfo in the cmd buffer emit. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 29 --

[Mesa-dev] [PATCH 2/2] radv: emit esgs ring size in one place.

From: Dave Airlie <airl...@redhat.com> This register is the same on all gpus so far, so emit it in one place and also for the pre-gfx9 gpus set the value in the pipeline creation. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 14 +++

[Mesa-dev] [PATCH] radv: free attachments on end command buffer.

From: Dave Airlie <airl...@redhat.com> If we allocate attachments in the begin command buffer due to the render pass continue bit, we were leaking them. Since renderpasses inside a cmd buffer malloc/free these properly, and set to NULL, we just need to call free at end. Fixes a memor

[Mesa-dev] [PATCH 3/4] radv: add helper for setting a descriptor.

From: Dave Airlie <airl...@redhat.com> This is just a simple refactor. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 20 src/amd/vulkan/radv_meta.c | 3 +-- src/amd/vulkan/radv_private.h| 4 3 files

[Mesa-dev] [PATCH 1/4] radv: reorder cmd_state to remove a hole.

From: Dave Airlie <airl...@redhat.com> This just removes a hole in the cmd_state and packs some bools together. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv

[Mesa-dev] [PATCH 4/4] radv: move descriptor sets out of cmd_state.

From: Dave Airlie <airl...@redhat.com> Instead of storing all the pointers and zeroing them all out, just store a valid bitmask in the state. This also moves the CmdBindPipeline path down the cpu usage path for the multithreading demo as it no longer has to traverse MAX_SETS to find the

[Mesa-dev] [PATCH 2/4] radv: move vertex binding out of cmd state.

From: Dave Airlie <airl...@redhat.com> This isn't required to be cleared, since buffers are only linked by vertex elements, so if elements are clear then no buffers should be referenced. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_cmd_buffer.c | 6 +++

[Mesa-dev] [PATCH] radv: add initial copy descriptor support. (v2)

From: Dave Airlie <airl...@redhat.com> It appears the latest dota2 vulkan uses this, and we get a hang in VR mode without it. v2: remove finishme I left in after finishing. Cc: "17.2 17.3" <mesa-sta...@lists.freedesktop.org> Signed-off-by: Dave Airlie <airl...@redhat

Re: [Mesa-dev] [PATCH 8/9] r600: add support for hw atomic counters. (v2)

On 3 November 2017 at 23:59, Gert Wollny <gw.foss...@gmail.com> wrote: > Am Freitag, den 03.11.2017, 17:24 +1000 schrieb Dave Airlie: >> >> diff --git a/src/gallium/drivers/r600/r600_pipe.c >> b/src/gallium/drivers/r600/r600_pipe.c >> index d67a22b..434596b 100644

[Mesa-dev] [PATCH 6/9] st/mesa: setup hw atomic limits.

From: Dave Airlie <airl...@redhat.com> HW atomics need to use caps to set some limits, and some other limits may also need limiting. This fixes things up to work for evergreen hw, it may need more changes in the future if other hw wants to use this path. Signed-off-by: Dave Airlie

[Mesa-dev] [PATCH 9/9] docs: update r600 atomic counter status.

From: Dave Airlie <airl...@redhat.com> Signed-off-by: Dave Airlie <airl...@redhat.com> --- docs/features.txt | 6 +++--- docs/relnotes/17.4.0.html | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index d228a02..1d

[Mesa-dev] [PATCH 5/9] st/mesa: start adding support for hw atomics atom.

From: Dave Airlie <airl...@redhat.com> This adds a new atom that calls the new driver API to bind buffers containing hw atomics. Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/mesa/state_tracker/st_atom_atomicbuf.c | 37 src/mesa/s

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