On Jun 10, 2015 9:57 AM, "Neil Roberts" wrote:
>
> Kenneth Graunke writes:
>
> > _mesa_meta_fb_tex_blit_begin(ctx, &blit);
> > + ctx->Extensions.ARB_texture_stencil8 = true;
>
> Maybe you could put assert(ctx->Extensions.ARB_texture_stencil8==false)
> just before setting it to true so that
LGTM
Reviewed-by: Jason Ekstrand
On Jun 10, 2015 7:39 AM, "Francisco Jerez" wrote:
> Instead use fs_builder::null_reg_f() which has the correct register
> width. Avoids the assertion failure in fs_builder::emit() h
On Thu, Jun 11, 2015 at 8:12 AM, Connor Abbott wrote:
> The one thing this will hurt is that diff'ing shaders from before and
> after an optimization becomes harder, since just printing the shader
> will re-order the numbers and add spurious changes. If we want to make
> the result of doing INTEL_
On Thu, Jun 11, 2015 at 12:41 AM, Tapani Pälli wrote:
> This is based on Kenneth's patch to delete 'most of the IR'. Due to
> linker changes to clone variables, we can now free all of IR.
>
> Saves 58MB of memory when replaying a Dota 2 trace on Broadwell.
I think we've saved ~50 MB 3 times now o
On Fri, Jun 12, 2015 at 7:34 AM, Neil Roberts wrote:
> Previously when glTexImage* is called it would attempt to create a
> temporary PBO if the texture is busy in order to avoid blocking when
> mapping the texture. This doesn't make much sense for glTexImage
> because in that case we are complete
On Jun 16, 2015 11:15 AM, "Anuj Phogat" wrote:
>
> Without this patch, arb_color_buffer_float-readpixels test fails, when
> forced to use meta pbo path.
>
> Signed-off-by: Anuj Phogat
> Cc:
> ---
> src/mesa/drivers/common/meta_tex_subimage.c | 10 ++
> 1 file changed, 6 insertions(+), 4
Please note in the commit message exactly what is broken.
On Jun 16, 2015 11:15, "Anuj Phogat" wrote:
> Signed-off-by: Anuj Phogat
> Cc:
> ---
> src/mesa/main/readpix.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
> index caa2648.
On Jun 16, 2015 11:15, "Anuj Phogat" wrote:
>
> Without this patch, piglit test fbo_integer_readpixels_sint_uint fails,
when
> forced to use the meta pbo path.
>
> Signed-off-by: Anuj Phogat
> Cc:
> ---
> src/mesa/drivers/common/meta_tex_subimage.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>
Wow... Reviewed-by: Jason Ekstrand
On Thu, Jun 18, 2015 at 4:19 PM, Matt Turner wrote:
> Fixes a performance problem caused by commit b639ed2f.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90895
> ---
> src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 3 ++-
>
> Any testing reports (or general approval of the state of the branch)
> will be greatly appreciated.
>
>
> Trivial merge conflicts
> ---
> commit bb00457f49177d8d43417855f843887de3148e99
> Author: Jason Ekstrand
>
> i965/fs: Don't let the EOT send messa
Soon we will start using the builder to explicitly set all the execution
sizes. We could make a 32-wide builder, but the builder asserts that we
never grow it which is usually a reasonable assumption. Sinc this one
instruction is a bit of an odd-ball, we just set the exec_size explicitly.
---
sr
Previously, fs_inst::regs_read() fell back to depending on the register
width for the second source. This isn't really correct since it isn't a
SIMD8 value at all, but a SIMD4x2 value. This commit changes it to
explicitly be always one register.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index b00825e..8a43ec8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/s
This makes things a little simpler, more efficient, and quite a bit more
readable.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 45 ++--
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/b
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ce56657..4f98d63 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -76
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 30 ++
src/mesa/drivers/dri/i965/brw_fs_builder.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 --
src/mesa/drivers/dri/i965/brw_ir_fs.h | 9 +
4 files changed, 8 insertions(+), 39 deletions(
Previously, we were just depending on register widths to ensure that
various things were exec_size of 1 etc. Now, we do so explicitly using the
builder.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri
Now that all of the non-explicit constructors are gone, we don't need to
guess anymore.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 22 --
1 file changed, 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index cff27e7..d9
---
src/mesa/drivers/dri/i965/brw_fs_builder.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index 7d3c8ab..58519d7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
+++ b/s
There are a variety of places where we use dst.width / 8 to compute the
size of a single logical channel. Instead, we should be using exec_size.
---
src/mesa/drivers/dri/i965/brw_fs.cpp| 6 +++---
src/mesa/drivers/dri/i965/brw_fs_cse.cpp| 2 +-
src/mesa/drivers
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 61235d7..cff27e7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index d9b7f75..b889432 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965
We want to move these into the builder so that they know the current
builder's dispatch width. This will be needed by a later commit.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 52 ++
src/mesa/drivers/dri/i965/brw_fs_builder.h | 46 +
src/mesa/drivers/dri/i965/brw_fs_c
Previously we used dst.width but the two *should* be the same.
---
src/mesa/drivers/dri/i965/brw_fs_builder.h | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index 74f
This doesn't affect instructions allocated using the builder.
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index c1
As of now, the width field is no longer used for anything. The width field
"seemed like a good idea at the time" but is actually entirely redundant
with the instruction's execution size. Initially, it gave us the ability
to easily set the instructions execution size based entirely on register
wid
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 8eb3ace..2b66acf 100644
--- a/src/mesa/drivers/dri/i965/brw_f
On Jun 19, 2015 5:09 AM, "Iago Toral" wrote:
>
> On Thu, 2015-06-18 at 17:50 -0700, Jason Ekstrand wrote:
> > Soon we will start using the builder to explicitly set all the execution
> > sizes. We could make a 32-wide builder, but the builder asserts that we
> >
Soon we will start using the builder to explicitly set all the execution
sizes. We could make a 32-wide builder, but the builder asserts that we
never grow it which is usually a reasonable assumption. Sinc this one
instruction is a bit of an odd-ball, we just set the exec_size explicitly.
v2: Ex
Previously, fs_inst::regs_read() fell back to depending on the register
width for the second source. This isn't really correct since it isn't a
SIMD8 value at all, but a SIMD4x2 value. This commit changes it to
explicitly be always one register.
Reviewed-by: Iago Toral Quiroga
v2: Use mlen for
Previously, we were allocating the payload with different sizes per gen and
then figuring out the mlen in the generator based on gen. This meant,
among other things, that the higher level passes knew nothing about it.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 14 +-
src/mes
On Fri, Jun 19, 2015 at 1:40 PM, Anuj Phogat wrote:
> On Tue, Jun 16, 2015 at 9:21 PM, Jason Ekstrand wrote:
>>
>> On Jun 16, 2015 11:15, "Anuj Phogat" wrote:
>>>
>>> Without this patch, piglit test fbo_integer_readpixels_sint_uint fails,
&
On Fri, Jun 19, 2015 at 1:51 PM, Matt Turner wrote:
> On Fri, Jun 19, 2015 at 1:18 PM, Jason Ekstrand wrote:
>> Previously, fs_inst::regs_read() fell back to depending on the register
>> width for the second source. This isn't really correct since it isn't a
>> SI
I started working on this project some time ago to remove brw_context from
the backend compiler. I got a bunch of refactoring done but eventualy got
stuck up on shader_time and some debug logging stuff. I've finally gotten
around to finishing it and here it is.
Jason Ekstrand (15):
From: Kenneth Graunke
This will be useful for wrapper functions.
Signed-off-by: Kenneth Graunke
---
src/mesa/main/errors.c | 29 +
src/mesa/main/errors.h | 9 +
2 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/src/mesa/main/errors.c b/src/mes
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_cs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs.h| 4 +++-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 5 +++--
Previously, each shader took 3 shader time indices which were potentially
at arbirary points in the shader time buffer. Now, each shader gets a
single index which refers to 3 consecutive locations in the buffer. This
simplifies some of the logic at the cost of having a magic 3 a few places.
---
---
src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 92d1085..dcbd240 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++ b/src/
---
src/mesa/drivers/dri/i965/brw_cs.cpp | 8 +++-
src/mesa/drivers/dri/i965/brw_fs.cpp | 55 ---
src/mesa/drivers/dri/i965/brw_fs.h| 7 ++-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 7 ++-
src/mesa/drivers/dri/i965/brw_vec
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5563c5a..ac65202 100644
--- a/src/
Previously, these were pulled out of the GL context conditionally based on
whether we were running ff/ARB or a GLSL program. Now, we just pass them
in so that the visitor doesn't have to grab them itself.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 ++--
src/mesa/drivers/dri/i965/b
This creates the options at screen cration time and then we just copy them
into the context at context creation time. We also move is_scalar to the
brw_compiler structure.
We also end up manually setting some values that the core would have set by
default for us. Fortunately, there are only two
While we're at it, we'll drop the note about 10-20% performance loss.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index a9d9f37..40e2c44 1006
This way we can stop doing is_gles3 checks inside of the compiler.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp| 4 +++-
src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp | 9 +
src/mesa/drivers/dri/i965/brw_vs.h| 5 -
3 files changed, 12 insertions(+), 6 dele
v2 (Ken): Make shader_debug_log a printf-like function.
v3 (Jason): Add a void * to pass the brw_context through
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_cs.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++-
s
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 +
src/mesa/drivers/dri/i965/brw_shader.cpp | 26 ++
src/mesa/drivers/dri/i965/brw_shader.h | 1 +
3 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/me
---
src/mesa/drivers/dri/i965/brw_context.c | 10 +-
src/mesa/drivers/dri/i965/intel_debug.c | 13 ++---
src/mesa/drivers/dri/i965/intel_debug.h | 4 ++--
src/mesa/drivers/dri/i965/intel_screen.c | 2 ++
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/src/mesa
We never used the fact that it was variadic anyway.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 14 --
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.c
As of this commit, nothing actually needs the brw_context.
---
src/mesa/drivers/dri/i965/brw_cs.cpp| 6 --
src/mesa/drivers/dri/i965/brw_fs.cpp| 12 ++--
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_reg_a
Previously, we were pulling it from brw->do_rep_send
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
inde
On Tue, Jun 23, 2015 at 9:22 AM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> We want to move these into the builder so that they know the current
>> builder's dispatch width. This will be needed by a later commit.
>
> I very much like the idea of this se
On Tue, Jun 23, 2015 at 1:39 AM, Pohjolainen, Topi
wrote:
> On Thu, Jun 18, 2015 at 05:51:36PM -0700, Jason Ekstrand wrote:
>> We want to move these into the builder so that they know the current
>> builder's dispatch width. This will be needed by a later commit.
>> --
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index ea29341..9a4bad6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++
On Wed, Jun 24, 2015 at 6:44 AM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> On Jun 24, 2015 6:29 AM, "Francisco Jerez" wrote:
>>>
>>> Jason Ekstrand writes:
>>>
>>> > On Jun 24, 2015 4:29 AM, "Francisco Jerez"
On Wed, Jun 24, 2015 at 7:56 AM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> On Wed, Jun 24, 2015 at 6:44 AM, Francisco Jerez
>> wrote:
>>> Jason Ekstrand writes:
>>>
>>>> On Jun 24, 2015 6:29 AM, "Francisco Jerez" wrote:
&
On Sat, Jun 20, 2015 at 5:32 AM, Timothy Arceri wrote:
> Hi all,
>
> The restrictions in ES make the extension easier to implement so
> I thought I'd try get this stuff reviewed an committed before finishing
> up the full extension.
> The bits that I'm still working on for the desktop version are
On Jun 24, 2015 4:29 AM, "Francisco Jerez" wrote:
>
> Jason Ekstrand writes:
>
> > On Tue, Jun 23, 2015 at 9:22 AM, Francisco Jerez
wrote:
> >> Jason Ekstrand writes:
> >>
> >>> We want to move these into the builder so that they know th
to use the meta pbo path.
>
> v2: Make need_rgb_to_luminance_conversion() a static function. (Iago)
> Bump up the comment and the commit message. (Jason)
>
> Signed-off-by: Anuj Phogat
> Reviewed-by: Jason Ekstrand
> Cc: Iago Toral
> Cc:
> ---
>
From Muchnick's Advanced Compiler Design and Implementation:
"To determine which variables are live at each point in a flowgraph, we
perform a backward data-flow analysis"
Previously, we were walking the blocks forwards and updating the livein and
then the liveout. However, the livein calculatio
On Thu, Jun 25, 2015 at 1:19 AM, Timothy Arceri wrote:
> On Wed, 2015-06-24 at 11:17 -0700, Jason Ekstrand wrote:
>> On Sat, Jun 20, 2015 at 5:32 AM, Timothy Arceri <
>> t_arc...@yahoo.com.au> wrote:
>> > Hi all,
>> >
>> > The restrictions in ES
On Tue, Jun 23, 2015 at 2:09 AM, Pohjolainen, Topi
wrote:
> On Thu, Jun 18, 2015 at 05:51:37PM -0700, Jason Ekstrand wrote:
>> Previously, we were just depending on register widths to ensure that
>> various things were exec_size of 1 etc. Now, we do so explicitly using
Previously, fs_inst::regs_read() fell back to depending on the register
width for the second source. This isn't really correct since it isn't a
SIMD8 value at all, but a SIMD4x2 value. This commit changes it to
explicitly be always one register.
Reviewed-by: Iago Toral Quiroga
v2: Use mlen for
This doesn't affect instructions allocated using the builder.
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_e
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 8976c25..2341d02 1
ivial.
09: New. This is a complete replacement of patch 07 from the previous
series.
Cc: Topi Pohjolainen
Cc: Iago Toral Quiroga
Cc: Francisco Jerez
Cc: Neil Roberts
Jason Ekstrand (19):
i965/fs: Use a switch statement in fs_inst::regs_read()
i965/fs: Actually set/use the mlen for ge
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 30 ++
src/mesa/drivers/dri/i965/brw_fs_builder.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 --
src/mesa/drivers/dri/i965/brw_ir_fs.h | 9 +
4 files changed,
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 42
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 58 +--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 143
Shortly, offset() will depend on the builder so we need it moved to some
place where it has access to that.
---
src/mesa/drivers/dri/i965/brw_fs.h| 21 +
src/mesa/drivers/dri/i965/brw_ir_fs.h | 21 -
2 files changed, 21 insertions(+), 21 deletions(-)
di
Previously, we were allocating the payload with different sizes per gen and
then figuring out the mlen in the generator based on gen. This meant,
among other things, that the higher level passes knew nothing about it.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 19 ---
sr
Soon we will start using the builder to explicitly set all the execution
sizes. We could make a 32-wide builder, but the builder asserts that we
never grow it which is usually a reasonable assumption. Sinc this one
instruction is a bit of an odd-ball, we just set the exec_size explicitly.
Review
Previously, we were just depending on register widths to ensure that
various things were exec_size of 1 etc. Now, we do so explicitly using the
builder.
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
d
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index d1e253a..4f56865 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 589b74c..6cf9e96 100644
--- a/src/mesa/drivers/dri/i
This makes things a little simpler, more efficient, and quite a bit more
readable.
Reviewed-by: Iago Toral Quiroga
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 45 ++--
1 file changed, 23 insertions(+), 22 deletions(-)
diff --git a/sr
There are a variety of places where we use dst.width / 8 to compute the
size of a single logical channel. Instead, we should be using exec_size.
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs.cpp| 6 +++---
src/mesa/drivers/dri/i965/brw_fs_cse.cpp
Previously we used dst.width but the two *should* be the same.
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs_builder.h | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h
b/src/mesa/drivers/dri
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 6e45fa7..aeaa1c4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
As of now, the width field is no longer used for anything. The width field
"seemed like a good idea at the time" but is actually entirely redundant
with the instruction's execution size. Initially, it gave us the ability
to easily set the instructions execution size based entirely on register
wid
Now that all of the non-explicit constructors are gone, we don't need to
guess anymore.
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 22 --
1 file changed, 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 8d821ab..0a70bdc 100644
--- a/
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index d4cc43d..d94a842 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/d
l convert_everything);
I don't think "convert everything" is really what we want to call it.
A better idea might be to flip the bool and call it phi_webs_only.
With that changed,
Reviewed-by: Jason Ekstrand
>
> bool nir_opt_algebraic(nir_shader *shader);
> bool ni
Reviewed-by: Jason Ekstrand
On Thu, Jun 25, 2015 at 12:29 PM, Connor Abbott wrote:
> It's now unused.
>
> Signed-off-by: Connor Abbott
> ---
> src/glsl/nir/nir.h | 10 --
> 1 file changed, 10 deletions(-)
>
> diff --git a/src/glsl/nir/nir.h b/src/g
Yes, please! It was nice at the time, but it was always a hack.
Reviewed-by: Jason Ekstrand
On Thu, Jun 25, 2015 at 12:29 PM, Connor Abbott wrote:
> It's no longer used
>
> Signed-off-by: Connor Abbott
> ---
> src/glsl/nir/nir.c | 1 -
> src/glsl
->parent_instr->type == nir_instr_type_load_const);
> - nir_load_const_instr *load =
> nir_instr_as_load_const(src.ssa->parent_instr);
> - fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_D, src.ssa->num_components);
> -
> - for (unsigned i = 0; i < src.ssa->nu
And, you got some shader-db stats:
total instructions in shared programs: 6078991 -> 6073118 (-0.10%)
instructions in affected programs: 402221 -> 396348 (-1.46%)
helped:1527
HURT: 0
GAINED:8
LOST:
In C, if you partially initialize a structure, the rest of the struct gets
set to 0. C++, however, does not have this rule so GCC throws warnings
whenver NIR_SRC_INIT or NIR_DEST_INIT is used in C++. Since nir.h contains
a static inline that uses NIR_SRC_INIT, every C++ file that includes nir.h
c
On Fri, Jun 26, 2015 at 8:52 AM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> Reviewed-by: Topi Pohjolainen
>> ---
>> src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/driver
On Fri, Jun 26, 2015 at 12:08 PM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> In C, if you partially initialize a structure, the rest of the struct gets
>> set to 0. C++, however, does not have this rule so GCC throws warnings
>> whenver NIR_SRC_INIT or NI
On Fri, Jun 26, 2015 at 3:03 PM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> On Fri, Jun 26, 2015 at 12:08 PM, Francisco Jerez
>> wrote:
>>> Jason Ekstrand writes:
>>>
>>>> In C, if you partially initialize a structure, the rest of th
struct brw_vue_prog_key *) this->key;
>
> + /* Bail unless some sort of legacy clipping is enabled */
> + if (!key->userclip_active || prog->UsesClipDistanceOut)
> + return;
> +
Any reason why you changed this from a conditional call to
compute_clip_distance to a
On Fri, Jun 26, 2015 at 3:34 PM, Francisco Jerez wrote:
> Jason Ekstrand writes:
>
>> On Fri, Jun 26, 2015 at 3:03 PM, Francisco Jerez
>> wrote:
>>> Jason Ekstrand writes:
>>>
>>>> On Fri, Jun 26, 2015 at 12:08 PM, Francisco Jerez
>>>
Thanks!
R-B me
On Jun 27, 2015 7:57 AM, "Rob Clark" wrote:
> From: Rob Clark
>
> Signed-off-by: Rob Clark
> ---
> src/glsl/nir/nir_lower_alu_to_scalar.c | 2 +-
> src/glsl/nir/nir_lower_vec_to_movs.c | 2 +-
> src/glsl/nir/nir_search.c | 2 +-
> 3 files changed, 3 insertions(+)
On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev wrote:
> The NIR->vec4 pass will be activated if ALL the following conditions are met:
>
> * INTEL_USE_NIR environment variable is defined and is positive (1 or true)
> * The stage is vertex shader
> * The HW generation is either SandyBridge (gen
On Mon, Jun 29, 2015 at 2:49 PM, Eduardo Lima Mitev wrote:
> On 06/29/2015 11:22 PM, Jason Ekstrand wrote:
>> On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev wrote:
>>> The NIR->vec4 pass will be activated if ALL the following conditions are
>>> met:
>&
On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev wrote:
> This implementation sets up a map of input variable offsets to source
> registers
> that are already initialized with the corresponding register offset.
>
> This map will then be queried when processing load_input intrinsic operations,
On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev wrote:
> From: Iago Toral Quiroga
>
> This is based on similar code existing in vec4_visitor. It builds the
> uniform register file iterating through each uniform variable. It
> also stores the index of each register at the corresponding offset
On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev wrote:
> From: Alejandro Piñeiro
>
> The new virtual method is more flexible, it has a signature:
>
> dst_reg *make_reg_for_system_value(int location, const glsl_type *type);
>
> so the current method will be chained through this one.
I just gr
Good work guys! I've started reviewing but review will probably take
a few days so please be patient.
On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev wrote:
> Hello,
>
> This series adds a new vec4 backend for i965 based on NIR. It is the result
> of working on
> https://bugs.freedesktop.o
On Fri, Jun 26, 2015 at 1:06 AM, Eduardo Lima Mitev wrote:
> From: Alejandro Piñeiro
>
> Similar to other variable setups, system values will initialize the
> corresponding register inside a 'nir_system_values' map, which will then
> be queried later when processing the different system value int
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