[Mesa-dev] [RFC PATCH] get_reviewer.pl: Delete

I find this script *really* annoying. Getting Cc'd on a random sample of a series is doing it wrong. Cc lists of 14 people is doing it wrong. Let's start the negotiation with "delete this script" and see if anyone can come up with a way of making this not so stupid. --- scripts/get_reviewer.pl |

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

On Tue, Feb 27, 2018 at 2:26 AM, Thierry Reding <thierry.red...@gmail.com> wrote: > On Mon, Feb 26, 2018 at 11:14:05AM -0800, Matt Turner wrote: >> On Fri, Feb 23, 2018 at 5:18 AM, Thierry Reding >> <thierry.red...@gmail.com> wrote: >> > From: Thierry Reding <

Re: [Mesa-dev] [PATCH 12/17] intel/compiler/fs: Implement ddy without using align16 for Gen11+

On Fri, Feb 23, 2018 at 4:42 PM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Tuesday, February 20, 2018 9:15:19 PM PST Matt Turner wrote: >> Align16 is no more. We previously generated an align16 ADD instruction >> to calculate DDY: >> >>add(8) g11

Re: [Mesa-dev] [PATCH 11/17] intel/compiler/fs: Simplify ddx/ddy code generation

On Fri, Feb 23, 2018 at 4:37 PM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Tuesday, February 20, 2018 9:15:18 PM PST Matt Turner wrote: >> The brw_reg() constructor just obfuscates things here, in my opinion. >> --- >> src/intel/compile

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

slate > these operations into lock-free instructions and will instead rely on Here, and in the comment in meson.build, I think you mean "atomic" rather than "lock-free" instructions? It's at least confusing, since on x86 atomic instructions have a "lock" prefi

Re: [Mesa-dev] [PATCH] intel/ir: Fix invalid type aliasing with undefined behavior in test_eu_compact.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

On Wed, Feb 21, 2018 at 10:37 AM, Anuj Phogat wrote: > On Wed, Feb 21, 2018 at 9:22 AM, Rafael Antognolli > wrote: >> My understanding is that this commit is enough to make the driver try to >> initialize, at least for i965. If that's the case,

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

On Wed, Feb 21, 2018 at 9:22 AM, Rafael Antognolli wrote: > My understanding is that this commit is enough to make the driver try to > initialize, at least for i965. If that's the case, how about we add > something like what was removed by commit >

Re: [Mesa-dev] [PATCH 03/17] intel: Disable 64-bit extensions on platforms without 64-bit types

On Wed, Feb 21, 2018 at 2:05 AM, Iago Toral <ito...@igalia.com> wrote: > On Tue, 2018-02-20 at 21:15 -0800, Matt Turner wrote: >> Gen11 does not support DF, Q, UQ types in hardware. As a result, we >> have >> to disable some GL extensions until they can be reimplem

[Mesa-dev] [PATCH 16/17] intel/compiler: Disable Align16 tests on Gen11+

Align16 is no more. --- src/intel/compiler/test_eu_validate.cpp | 16 1 file changed, 16 insertions(+) diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index cb2fcd3d40f..f6c2b35625e 100644 ---

[Mesa-dev] [PATCH 17/17] intel/compiler: Add ICL to test_eu_validate.cpp

With the Align16 tests now disabled, we can run the rest of the tests in ICL mode (and see them pass!) --- src/intel/compiler/test_eu_validate.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp index

[Mesa-dev] [PATCH 08/17] intel/compiler/fs: Fix application of cmod and saturate to LINE/MAC pair

--- src/intel/compiler/brw_fs_generator.cpp | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 0854709b272..f2bdac7d731 100644 --- a/src/intel/compiler/brw_fs_generator.cpp

[Mesa-dev] [PATCH 13/17] intel/compiler: Lower flrp32 on Gen11+

The LRP instruction is no more. --- src/intel/compiler/brw_compiler.c | 35 + src/intel/compiler/brw_fs_builder.h | 2 +- src/intel/compiler/brw_fs_generator.cpp | 2 +- src/intel/compiler/brw_vec4_builder.h | 2 +-

[Mesa-dev] [PATCH 12/17] intel/compiler/fs: Implement ddy without using align16 for Gen11+

Align16 is no more. We previously generated an align16 ADD instruction to calculate DDY: add(8) g11<1>F -g10<4>.xyxyF g10<4>.zwzwF { align16 1Q }; Without align16, we now implement it as two align1 instructions: add(4) g11<2>F -g10<4,2,0>Fg10.2<4,2,0>F { align1 1N }; add(4)

[Mesa-dev] [PATCH 07/17] intel/compiler/fs: Return multiple_instructions_emitted from generate_linterp

If multiple instructions are emitted, special handling of things like conditional mod, saturate, and NoDDClr/NoDDChk need to be performed. I noticed that conditional mods were misapplied when adding support for Gen11 (in the previous patch). The next patch fixes the same bug in the Gen4 LINE/MAC

[Mesa-dev] [PATCH 11/17] intel/compiler/fs: Simplify ddx/ddy code generation

The brw_reg() constructor just obfuscates things here, in my opinion. --- src/intel/compiler/brw_fs_generator.cpp | 77 +++-- 1 file changed, 35 insertions(+), 42 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp

[Mesa-dev] [PATCH 14/17] intel/compiler: Mark line, pln, and lrp as removed on Gen11+

--- src/intel/compiler/brw_eu.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c index bc297a21b32..3646076a8e8 100644 --- a/src/intel/compiler/brw_eu.c +++ b/src/intel/compiler/brw_eu.c @@ -384,7 +384,8 @@

[Mesa-dev] [PATCH 10/17] intel/compiler/fs: Pass fs_inst to generate_ddx/ddy instead of opcode

In a future patch, generate_ddy will want to inspect inst->exec_size. Change generate_ddx as well for consistency. --- src/intel/compiler/brw_fs.h | 6 -- src/intel/compiler/brw_fs_generator.cpp | 12 ++-- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git

[Mesa-dev] [PATCH 09/17] intel/compiler/fs: Don't generate integer DWord multiply on Gen11

Like CHV et al., Gen11 does not support 32x32 -> 32/64-bit integer multiplies. --- src/intel/common/gen_device_info.c | 4 src/intel/common/gen_device_info.h | 1 + src/intel/compiler/brw_fs.cpp | 6 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH 15/17] intel/compiler: Add instruction compaction support on Gen11

Gen11 only differs from SKL+ in that it uses a new datatype index table. --- src/intel/compiler/brw_eu_compact.c | 42 + 1 file changed, 42 insertions(+) diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c index

[Mesa-dev] [PATCH 06/17] intel/compiler/fs: Implement FS_OPCODE_LINTERP with MADs on Gen11+

The PLN instruction is no more. Its functionality is now implemented using two MAD instructions with the new native-float type. Instead of pln(16) r20.0<1>:F r10.4<0;1,0>:F r4.0<8;8,1>:F we now have mad(8) acc0<1>:NF r10.7<0;1,0>:F r4.0<8;8,1>:F r10.4<0;1,0>:F mad(8) r20.0<1>:F

[Mesa-dev] [PATCH 00/17] intel/compiler: Ice Lake support

[PATCH 01/17] intel: Add a preliminary device for Ice Lake [PATCH 02/17] intel: Add icl pci id for INTEL_DEVID_OVERRIDE [PATCH 03/17] intel: Disable 64-bit extensions on platforms without [PATCH 04/17] intel/compiler: Add Gen11 register types [PATCH 05/17] intel/compiler: Add Gen11+ native float

[Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

From: Anuj Phogat Signed-off-by: Anuj Phogat --- include/pci_ids/i965_pci_ids.h | 9 ++ src/intel/common/gen_device_info.c | 56 +- 2 files changed, 64 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 04/17] intel/compiler: Add Gen11 register types

The hardware register types' encodings have changed on Gen11. Good thing we have that superfluous looking brw_reg_type abstraction lying around! --- src/intel/compiler/brw_reg_type.c | 73 ++- 1 file changed, 65 insertions(+), 8 deletions(-) diff --git

[Mesa-dev] [PATCH 05/17] intel/compiler: Add Gen11+ native float type

This new type exposes the additional precision offered by the accumulator register and will be used in the next patch to implement the functionality of the PLN instruction using a pair of MAD instructions. One weird thing to note: align1 ternary instructions may only have an accumulator in the

[Mesa-dev] [PATCH 03/17] intel: Disable 64-bit extensions on platforms without 64-bit types

Gen11 does not support DF, Q, UQ types in hardware. As a result, we have to disable some GL extensions until they can be reimplemented. --- src/intel/common/gen_device_info.c | 3 +++ src/intel/common/gen_device_info.h | 1 + src/mesa/drivers/dri/i965/intel_extensions.c | 9

[Mesa-dev] [PATCH 02/17] intel: Add icl pci id for INTEL_DEVID_OVERRIDE

From: Anuj Phogat <anuj.pho...@gmail.com> Reviewed-by: Matt Turner <matts...@gmail.com> Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- src/mesa/drivers/dri/i965/intel_screen.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c

Re: [Mesa-dev] [PATCH 14/17] i965: Fix compiler warning about write being undefined.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] nir: remove the abs call in is_neg_power_of_two

On Mon, Feb 5, 2018 at 7:16 PM, Vlad Golovkin wrote: > val->i32[swizzle[i]] is guaranteed to have non-positive value before the > __is_power_of_two call, so unary minus is equivalent to abs in this case. > --- > src/compiler/nir/nir_search_helpers.h | 2 +- > 1 file

Re: [Mesa-dev] [PATCH] i965: Trim

On Wed, Feb 7, 2018 at 11:41 AM, Chris Wilson wrote: >textdata bss dec hex filename > 8852169 388752 671064 9911985 973eb1 lib/i965_dri.so > 8852017 388752 671064 9911833 973e19 > --- > src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 48 >

Re: [Mesa-dev] [PATCH] mesa: fix incorrect type when allocating arrays

d fix the issue, if I'm interpreting > the coverity message correctly. Yep, that matches my understanding. Thanks! Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] mesa: remove usage of alloca in externalobjects.c v3

On Wed, Jan 31, 2018 at 11:03 AM, Andres Rodriguez wrote: > Don't want an overly large numBufferBarriers/numTextureBarriers to blow > up the stack. > > v2: handle malloc errors > v3: fix patch > > Suggested-by: Emil Velikov > Signed-off-by: Andres

Re: [Mesa-dev] [PATCH v2] i965/nir: do int64 lowering before optimization

has happened in > master since we sent the original patch. Originally, the tests would > just hang forever trying to compile. Seems like a step in the right direction. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965/nir: do int64 lowering before optimization

On Wed, Dec 13, 2017 at 11:21 PM, Iago Toral wrote: > On Tue, 2017-12-12 at 08:20 +0100, Iago Toral wrote: > > On Mon, 2017-12-11 at 08:01 -0800, Jason Ekstrand wrote: > > On Mon, Dec 11, 2017 at 12:55 AM, Iago Toral wrote: > > This didn't get any reviews

Re: [Mesa-dev] [PATCH shaderdb 1/3] run: split out helper to create contexts

in the current code. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH shaderdb 2/3] run: fallback to 3.1 core context

On Mon, Jan 29, 2018 at 12:08 PM, Rob Clark wrote: > On Mon, Jan 29, 2018 at 2:39 PM, Ilia Mirkin wrote: >> On Mon, Jan 29, 2018 at 2:26 PM, Rob Clark wrote: >>> If we can't create a 3.2 core context, fall back to a 3.1 context.

Re: [Mesa-dev] [PATCH shaderdb 1/2] run: fall back to v3.1 core ctx if v3.2 fails

On Sat, Jan 27, 2018 at 4:08 PM, Rob Clark <robdcl...@gmail.com> wrote: > On Sat, Jan 27, 2018 at 7:02 PM, Matt Turner <matts...@gmail.com> wrote: >> On Sat, Jan 27, 2018 at 10:06 AM, Rob Clark <robdcl...@gmail.com> wrote: >>> Signed-off-by: Rob Clark <robdc

Re: [Mesa-dev] [PATCH shaderdb 1/2] run: fall back to v3.1 core ctx if v3.2 fails

On Sat, Jan 27, 2018 at 4:02 PM, Matt Turner <matts...@gmail.com> wrote: > On Sat, Jan 27, 2018 at 10:06 AM, Rob Clark <robdcl...@gmail.com> wrote: >> Signed-off-by: Rob Clark <robdcl...@gmail.com> >> --- >> run.c | 12 >> 1 file changed

Re: [Mesa-dev] [PATCH shaderdb 1/2] run: fall back to v3.1 core ctx if v3.2 fails

On Sat, Jan 27, 2018 at 10:06 AM, Rob Clark wrote: > Signed-off-by: Rob Clark > --- > run.c | 12 > 1 file changed, 12 insertions(+) > > diff --git a/run.c b/run.c > index 69fe23d..20a0a6a 100644 > --- a/run.c > +++ b/run.c > @@ -520,6

Re: [Mesa-dev] [PATCH] i965/fs: Reset the register file to VGRF in lower_integer_multiplication

s.precision.uint.mediump_mul_fragment.snbm64 > ES3-CTS.functional.shaders.precision.uint.lowp_mul_fragment.snbm64 > > This commit remedies this problem by, instead of copying inst->dst and > overwriting nr, just make a new register and set the region to match > inst->dst. > > Cc: Matt Turner <matts..

Re: [Mesa-dev] [ANNOUNCE] mesa 18.0-0-rc1

On Tue, Jan 23, 2018 at 10:02 AM, Emil Velikov <emil.l.veli...@gmail.com> wrote: > On 23 January 2018 at 17:33, Matt Turner <matts...@gmail.com> wrote: >> On Tue, Jan 23, 2018 at 9:03 AM, Emil Velikov <emil.l.veli...@gmail.com> >> wrote: >>> The firs

Re: [Mesa-dev] [ANNOUNCE] mesa 18.0-0-rc1

Jon Turney > 43 Jordan Justen > 11 Jose Maria Casanova Crespo > 1 José Fonseca > 12 Juan A. Suarez Romero > 1 Julien Isorce > 1 Józef Kucia > 2 Kai Wasserbäch > 1 Karol Herbst > 72 Kenneth Graunke > 5 Kevin Rogovin >

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Use UW types when using V immediates

Bizarre. Hope we can get more info on what's going on, but if UW makes it work, let's do it. Both are: Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/li

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Add/use functions to convert to 3src_align1 vstride/hstride

On Mon, Jan 8, 2018 at 5:01 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: > >> Some cases weren't handled, such as stride 4 which is needed for 64-bit >> operations. Presumably fixes the assertion failure menti

[Mesa-dev] [PATCH 1/2] i965/fs: Add/use functions to convert to 3src_align1 vstride/hstride

Some cases weren't handled, such as stride 4 which is needed for 64-bit operations. Presumably fixes the assertion failure mentioned in commit 2d0457203871 (Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+") but who can really say since the commit neglected to list any of them!

[Mesa-dev] [PATCH 2/2] Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""

This reverts commit 2d0457203871c843ebfc90fb895b65a9b14cd9bb. --- src/intel/compiler/brw_fs_generator.cpp | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index

Re: [Mesa-dev] [PATCH] spirv: Loosten the validation for load/store type matching

The word is loosen. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] intel/fs: Optimize and simplify the copy propagation dataflow logic.

On Tue, Dec 19, 2017 at 9:19 PM, Francisco Jerez wrote: There's a comment near the top of the file describing the algorithm and referencing Muchnick. I think with your changes both of those are no longer accurate? ___ mesa-dev

Re: [Mesa-dev] [PATCH] intel/fs/bank_conflicts: Don't touch Gen7 MRF hack registers.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] intel/fs: Implement GRF bank conflict mitigation pass.

ATCH 3/2 I just sent > to make sure we keep regressions under control) if nobody else does in > the next two weeks. I'm really sorry I wasn't ever able to give this the proper review it deserved. It's a really impressive piece of work. You should feel free to commit it with my Acked-b

Re: [Mesa-dev] [PATCH 1/2] intel/fs: Implement GRF bank conflict mitigation pass.

On Thu, Jun 22, 2017 at 12:20 PM, Francisco Jerez wrote: > Unnecessary GRF bank conflicts increase the issue time of ternary > instructions (the overwhelmingly most common of which is MAD) by > roughly 50%, leading to reduced ALU throughput. This pass attempts to >

Re: [Mesa-dev] [PATCH] i965: Enable disk shader cache by default

On Tue, Dec 5, 2017 at 3:40 PM, Jordan Justen wrote: > On 2017-12-05 14:49:28, Mark Janes wrote: >> Jordan Justen writes: >> >> > On 2017-12-05 09:13:11, Mark Janes wrote: >> >> Jordan Justen writes: >> >> >> >> >

Re: [Mesa-dev] [PATCH] nir/opcodes: Fix constant-folding of bitfield_insert

> dst = 0; > } else { > unsigned mask = ((1ull << bits) - 1) << offset; > - dst = (base & ~mask) | ((insert << bits) & mask); > + dst = (base & ~mask) | ((insert << offset) & mask); > } > """) Reviewed-by: Matt

Re: [Mesa-dev] 答复: Re: screen blurred and glxgears segment fault on ubuntu17.10 for arm architecture server with amdgpu(AMD RADEON PRO WX7100)

On Tue, Dec 5, 2017 at 8:18 PM, Lvzhihong (ReJohn) wrote: > Hi Michel, > > We solve the glxgears segmentation fault problem by add the compile > flags: -fsigned-char. > In arm platform, char variant default to "unsigned-char", that makes > problem of

Re: [Mesa-dev] [PATCH 0/5] i965: ASTC5x5 workaround

On Fri, Dec 1, 2017 at 10:06 AM, Rogovin, Kevin wrote: > Hi, > > Yes ANV will need something like this as well. If the GPU samples from both > an ASTC5x5 texture and one with an aux buffer without a texture cache > invalidate between such accesses, then the GPU hangs,

[Mesa-dev] [PATCH 2/2] i965: Emit CS stall before MEDIA_VFE_STATE.

From: Kenneth Graunke <kenn...@whitecape.org> This fixes hangs on GFXBench 5's Aztec Ruins benchmark. Unfortunately, it regresses OglCSCloth performance by about 10%. There are some ideas for fixing that. The Vulkan driver already emits this stall. Reviewed-by: Matt Turner <matts...@

[Mesa-dev] [PATCH 1/2] i965: Move PIPE_CONTROL defines and prototypes to brw_pipe_control.h.

From: Kenneth Graunke <kenn...@whitecape.org> We need to be able to emit PIPE_CONTROLs from genX_state_upload.c, which can't safely include brw_defines.h because it conflicts with genxml. Move all the PIPE_CONTROL related stuff together into a separate header. Reviewed-by: Matt Turner

Re: [Mesa-dev] [PATCH] configure: avoid testing for negative compiler options

piler option > > Inverting the options fixes the tests. Thanks for figuring this out. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965/vec4: use a temp register to compute offsets for pull loads

et_nir_src(instr->src[1], nir_type_uint32, 1); > + offset_reg = src_reg(this, glsl_type::uint_type); > + emit(MOV(dst_reg(offset_reg), > + get_nir_src(instr->src[1], nir_type_uint32, 1))); >} > Nice find! Reviewed-by: Matt Turner <matt

Re: [Mesa-dev] [PATCH 01/12] i965/fs: Unpack count argument to 64-bit shift ops on Atom

On Tue, Nov 28, 2017 at 5:54 AM, Andres Gomez wrote: > Matt, this looks like a good candidate to nominate for inclusion in > the 17.2 stable queue. > > What do you think? Yes, I think so. I didn't realize that ARB_shader_ballot was in 17.2, but this is a bug fix for it so it

Re: [Mesa-dev] [PATCH 01/12] i965/fs: Unpack count argument to 64-bit shift ops on Atom

On Tue, Nov 28, 2017 at 12:35 PM, Ian Romanick wrote: > Also... it looks like only a few patches in this series got reviewed. > Did the whole thing actually land? Yes, I felt safe pushing the majority of it without review because of the extensive unit tests I wrote. I also

Re: [Mesa-dev] [PATCH] mesa/gles: adjust internal format in glTexSubImage2D error checks

Thanks Tapani. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] docs/llvmpipe.html: Add ppc64le as alternative architecture to x86.

On Mon, Nov 27, 2017 at 11:44 AM, Ben Crocker wrote: > Power8, Power8NV, and Power9 are supported on an equal footing > with X86. > > Cc: "17.2" "17.3" > Signed-off-by: Ben Crocker > --- > docs/llvmpipe.html | 20

Re: [Mesa-dev] i965: Kicking off fp16 glsl support

1-14, except 4 are Reviewed-by: Matt Turner <matts...@gmail.com> I started getting to things that made me realize I needed to review Igalia's work before I continued here. signature.asc Description: Digital signature ___ mesa-dev mailing lis

Re: [Mesa-dev] [PATCH 10/51] glsl: Allow 16-bit math

On 11/24, Topi Pohjolainen wrote: Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/ir_validate.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/compiler/glsl/ir_validate.cpp b/src/compiler/glsl/ir_validate.cpp index

Re: [Mesa-dev] [PATCH 09/51] glsl: Allow 16-bit neg() and dot()

On 11/24, Topi Pohjolainen wrote: Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/ir_validate.cpp | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/compiler/glsl/ir_validate.cpp b/src/compiler/glsl/ir_validate.cpp index

Re: [Mesa-dev] [PATCH 07/51] glsl: Add conversion ops to/from 16-bit floats

On 11/24, Topi Pohjolainen wrote: Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/glsl_to_nir.cpp| 2 ++ src/compiler/glsl/ir.cpp | 8 src/compiler/glsl/ir_expression_operation.py | 5 +

Re: [Mesa-dev] [PATCH 01/51] nir: Prepare constant folding for 16-bits

On 11/24, Topi Pohjolainen wrote: Signed-off-by: Topi Pohjolainen --- src/compiler/nir/nir_opt_constant_folding.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index

Re: [Mesa-dev] [PATCH 04/51] glsl: Print 16-bit constants

On 11/24, Topi Pohjolainen wrote: --- src/compiler/glsl/ir_print_visitor.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/glsl/ir_print_visitor.cpp b/src/compiler/glsl/ir_print_visitor.cpp index ea14cdeb6c..ab9a35d73f 100644 --- a/src/compiler/glsl/ir_print_visitor.cpp +++

Re: [Mesa-dev] [PATCH mesa 13/16] compiler: fix typo

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH mesa 12/16] compiler: use NDEBUG to guard asserts

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH mesa] util: add mesa-sha1 test to meson

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

On Mon, Nov 27, 2017 at 5:41 AM, Jon Turney <jon.tur...@dronecode.org.uk> wrote: > On 26/11/2017 00:46, Matt Turner wrote: >> >> I've committed what I hope is the final fix. > > > After this series, if we are building on a target unknown to u_endian.h, so > it can'

Re: [Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

On Sat, Nov 25, 2017 at 4:11 PM, Andres Gomez <ago...@igalia.com> wrote: > On Sat, 2017-11-25 at 16:00 -0800, Matt Turner wrote: >> On Sat, Nov 25, 2017 at 1:58 PM, Jon Turney <jon.tur...@dronecode.org.uk> >> wrote: >> > On 25/11/2017 04:24, Matt Turner wrote:

Re: [Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

On Sat, Nov 25, 2017 at 1:58 PM, Jon Turney <jon.tur...@dronecode.org.uk> wrote: > On 25/11/2017 04:24, Matt Turner wrote: >> >> diff --git a/src/util/u_endian.h b/src/util/u_endian.h >> index 7bbd7dc215..3d5c006f35 100644 >> --- a/src/util/u_endian.h >> +++

Re: [Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

On Fri, Nov 24, 2017 at 2:25 AM, Eric Engestrom <eric.engest...@imgtec.com> wrote: > On Thursday, 2017-11-23 11:08:04 -0800, Matt Turner wrote: >> The code defines a macro blk0(i) based on the preprocessor condition >> BYTE_ORDER == LITTLE_ENDIAN. If true, blk0(i) is d

Re: [Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

On Fri, Nov 24, 2017 at 8:51 AM, Andres Gomez <ago...@igalia.com> wrote: > On Fri, 2017-11-24 at 13:32 +, Emil Velikov wrote: >> On 24 November 2017 at 10:25, Eric Engestrom <eric.engest...@imgtec.com> >> wrote: >> > On Thursday, 2017-11-23 11:08:04 -0800

Re: [Mesa-dev] Mesa 17.2.6 release candidate

I would like to include the three patch series I sent today in 17.2.6. It fixes our SHA1 implementation on big endian, adds a test, and fixes another test. I hope it'll be reviewed and in master before the planned 17.2.6 release. ___ mesa-dev mailing

Re: [Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

Fixes: d1efa09d342b ("util: import sha1 implementation from OpenBSD") ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 3/3] util: Fix disk_cache index calculation on big endian

Fixes: 87ab26b2ab35 ("glsl: Add initial functions to implement an on-disk cache") ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 2/3] util: Add a SHA1 unit test program

--- src/util/Makefile.am | 3 ++- src/util/mesa-sha1_test.c | 65 +++ 2 files changed, 67 insertions(+), 1 deletion(-) create mode 100644 src/util/mesa-sha1_test.c diff --git a/src/util/Makefile.am b/src/util/Makefile.am index

[Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

The code defines a macro blk0(i) based on the preprocessor condition BYTE_ORDER == LITTLE_ENDIAN. If true, blk0(i) is defined as a byte swap operation. Unfortunately, if the preprocessor macros used in the test are no defined, then the comparison becomes 0 == 0 and it evaluates as true. ---

[Mesa-dev] [PATCH 3/3] util: Fix disk_cache index calculation on big endian

The cache-test test program attempts to create a collision (using key_a and key_a_collide) by making the first two bytes identical. The idea is fine -- the shader cache wants to use the first four characters of a SHA1 hex digest as the index. The following program unsigned char array[4]

Re: [Mesa-dev] [PATCH] i965/vec4: fix splitting of interleaved attributes

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Handle negating immediates on MADs when propagating saturates

On Mon, Nov 20, 2017 at 2:50 PM, Ian Romanick <i...@freedesktop.org> wrote: > On 11/20/2017 02:33 PM, Matt Turner wrote: >> MADs don't take immediate sources, but we allow them in the IR since it >> simplifies a lot of things. I neglected to consider that case. >> >&

[Mesa-dev] [PATCH 2/2] i965/fs: Check ADD/MAD with immediates in satprop unit test

The gen had to be changed from 4 to 6 so that we could test MAD, which is new on Gen6. mad_imm_float_neg_mov_sat tests the case fixed by the previous commit. --- .../compiler/test_fs_saturate_propagation.cpp | 126 - 1 file changed, 125 insertions(+), 1 deletion(-) diff

[Mesa-dev] [PATCH 1/2] i965/fs: Handle negating immediates on MADs when propagating saturates

MADs don't take immediate sources, but we allow them in the IR since it simplifies a lot of things. I neglected to consider that case. Fixes: 4009a9ead490 ("i965/fs: Allow saturate propagation to propagate negations into MADs.") Bugzilla:

Re: [Mesa-dev] [PATCH 1/4] meson: Enable SSE4.1 optimizations

On Mon, Nov 20, 2017 at 3:47 AM, Emil Velikov <emil.l.veli...@gmail.com> wrote: > On 17 November 2017 at 20:46, Matt Turner <matts...@gmail.com> wrote: >> On Fri, Nov 17, 2017 at 12:34 PM, Dylan Baker <dy...@pnwbakers.com> wrote: >>> Quoting Emil Velikov (2017

Re: [Mesa-dev] [PATCH] intel: fix diasm_info memory leaks

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 18/18] intel/tools: add command line GEN shader disassembler tool

end_offset, stdout, print_offsets); > + > + if (annotation[i].error) { > + fputs(annotation[i].error, stdout); > + } > + > + offset = end_offset; > + } > + > + if (offset < data_sz) { > + br

Re: [Mesa-dev] [PATCH] i965: Stop including brw_cfg.h in brw_disasm_info.h

p getting quite a bit > of our back-end compiler internals. Instead, make the couple of forward > declarations we need and make the header more stand-alone. This fixes > the meson build. > > Cc: Matt Turner <matts...@gmail.com> > Fixes: 4f82b17287194ca7d10816f6cfe4712a3e

Re: [Mesa-dev] [PATCH] i965: Correct disasm_info usage in eu_validate test

On Fri, Nov 17, 2017 at 4:48 PM, Andres Gomez <ago...@igalia.com> wrote: > Fixes: 4f82b1728719 ("i965: Rewrite disassembly annotation code") > > Cc: Matt Turner <matts...@gmail.com> > Signed-off-by: Andres Gomez <ago...@igalia.com> Damn it :) Reviewed-by:

Re: [Mesa-dev] [PATCH 1/4] meson: Enable SSE4.1 optimizations

On Fri, Nov 17, 2017 at 12:34 PM, Dylan Baker wrote: > Quoting Emil Velikov (2017-11-17 03:11:50) >> On 16 November 2017 at 22:21, Dylan Baker wrote: >> > Quoting Emil Velikov (2017-11-16 03:35:17) >> >> Hi Dylan, >> >> >> >> On 16 November 2017 at

Re: [Mesa-dev] [PATCH 3/4] i965: Rewrite disassembly annotation code

On Fri, Nov 17, 2017 at 11:16 AM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Thursday, November 16, 2017 8:47:33 PM PST Matt Turner wrote: >> diff --git a/src/intel/compiler/intel_asm_annotation.c >> b/src/intel/compiler/intel_asm_annotation.c >> index 26

Re: [Mesa-dev] [PATCH 07/18] intel/compiler: fix for memmove argument on annotating error

On Wed, Nov 15, 2017 at 12:13 AM, Rogovin, Kevin wrote: > I have just seen that I have had an epic brain lapse on this. > > The code is pretty clear, the correct value of count should be ann_count - i. > This is because: > a. The value of ann_count is the value of the

[Mesa-dev] [PATCH 2/4] i965: Simplify annotation_insert_error()

--- src/intel/compiler/intel_asm_annotation.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/src/intel/compiler/intel_asm_annotation.c b/src/intel/compiler/intel_asm_annotation.c index b07a545a12..26ab4b9818 100644 ---

[Mesa-dev] [PATCH 3/4] i965: Rewrite disassembly annotation code

The old code used an array to store each "instruction group" (the new, better name than the old overloaded "annotation"), and required a memmove() to shift elements over in the array when we needed to split a group so that we could add an error message. This was confusing and difficult to get

[Mesa-dev] [PATCH 4/4] i965: Rename intel_asm_annotation -> brw_disasm_info

It was the only file named intel_* in the compiler. --- src/intel/Makefile.sources | 6 +++--- src/intel/compiler/{intel_asm_annotation.c => brw_disasm_info.c} | 2 +- src/intel/compiler/{intel_asm_annotation.h => brw_disasm_info.h} | 0

[Mesa-dev] [PATCH 1/4] i965: Move common code out of #ifdef

I'm going to change the call in a later patch and with the difference in indentation level it wasn't immediately obvious that the calls were identical. --- src/intel/compiler/brw_fs_generator.cpp | 7 ++- src/intel/compiler/brw_vec4_generator.cpp | 6 ++ 2 files changed, 4

Re: [Mesa-dev] [PATCH v2] meson: Enable SSE4.1 optimizations

On Thu, Nov 16, 2017 at 2:46 PM, Dylan Baker wrote: > This patch checks for an and then enables sse4.1 optimizations if the > host machine will be x86/x86_64. > > v2: - Don't compile code, it's unnecessary since we require a compiler > which always has SSE4.1 (Matt) > >

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