[Mesa-dev] [PATCH 07/13] intel/isl: Remove 'inline' keywords

Unless you have data, the compiler knows better than you whether a function should be inlined. --- src/intel/isl/isl_emit_depth_stencil.c | 2 +- src/intel/isl/isl_format.c | 2 +- src/intel/isl/isl_surface_state.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff

[Mesa-dev] [PATCH 02/13] nir/spirv: Use unreachable("...") rather than assert(!"...")

Quiets a number of uninitialized variable warnings in clang. --- src/compiler/spirv/spirv_to_nir.c | 24 src/compiler/spirv/vtn_variables.c | 10 +- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c

[Mesa-dev] [PATCH 03/13] mesa: Don't compare unsigned for < 0

The INTEL_performance_query spec says "Performance counter id 0 is reserved as an invalid counter." GLuint counterid_to_index(GLuint counterid) just returns counterid - 1, so with unsigned overflow rules, it will generate 0x given an input of 0. 0x will trigger the

[Mesa-dev] [PATCH 01/13] egl: Fix inclusion of egl.h+mesa_glinterop.h

Previously clang would warn about redefinition of typedef EGLDisplay. Avoid this by adding preprocessor guards to mesa_glinterop.h and including it after EGL.h is indirectly included. --- include/GL/mesa_glinterop.h | 4 src/egl/drivers/dri2/egl_dri2.c | 2 +- src/egl/main/eglapi.c

[Mesa-dev] [PATCH 00/13] clang warning fixes

Just a simple series cleaning up various bits of code that clang warns about. The only real change is to "i965/vec4: Return float from spill_cost_for_type()" which fixes an obvious mistake. The rest just cleans things up like marking internal functions static.

Re: [Mesa-dev] [PATCH 14/25] i965: Use a common table to translate logical to hardware types

On Mon, Aug 7, 2017 at 3:43 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: >> --- >> src/intel/compiler/brw_reg_type.c | 65 >> +-- >> 1 file changed, 29 insertions(+),

Re: [Mesa-dev] [PATCH 09/25] i965: Reorder brw_reg_type enum values

On Tue, Aug 8, 2017 at 4:21 PM, Scott D Phillips <scott.d.phill...@intel.com> wrote: > Matt Turner <matts...@gmail.com> writes: >> These vaguely corresponded to the hardware encodings, but that is purely >> historical at this point. Reorder them so we stop making t

Re: [Mesa-dev] [PATCH] configure: remove trailing "-a" in swr architecture test

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] build: Fix up spirv_info.Plo

spirv_info.c existed as a static file until commit 2dd4e2ece32f began generating it as part of the build process. autotools is incapable of coping, and so a build-tree from before this commit would then fail with it: [4]: *** No rule to make target

Re: [Mesa-dev] [PATCH 10/25] i965: Use separate enums for register vs immediate types

On Tue, Aug 8, 2017 at 4:25 PM, Scott D Phillips wrote: >> + [BRW_HW_IMM_TYPE_UV] = 2, >> + [BRW_HW_IMM_TYPE_VF] = 4, >> + [BRW_HW_IMM_TYPE_V] = 2, > > Is this right? I see it was there before, and perhaps I'm being dense, > but it seems

[Mesa-dev] [PATCH 24/25] i965: Mark brw_hw_type_to_reg_type() as a pure function

textdata bss dec hex filename 7816886 346248 420496 8583630 82f9ce i965_dri.so before 7816214 346248 420496 8582958 82f72e i965_dri.so after --- src/intel/compiler/brw_reg_type.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 22/25] i965: Stop using hardware register types directly

--- src/intel/compiler/brw_disasm.c | 47 - src/intel/compiler/brw_eu_validate.c | 196 --- src/intel/compiler/brw_reg_type.c| 17 +-- src/intel/compiler/brw_reg_type.h| 11 +- 4 files changed, 113 insertions(+), 158 deletions(-) diff --git

[Mesa-dev] [PATCH 25/25] i965: Optimize reading the destination type

brw_hw_type_to_reg_type() needs to know only whether the file is BRW_IMMEDIATE_VALUE or not, which is not a valid file for the destination. gcc and clang will evaluate __builtin_strcmp() at compile time, so we can use it to pass a constant file for the destination. textdata bss dec

[Mesa-dev] [PATCH 23/25] i965: Hide the register type hardware encodings

So we stop mixing them with the logical enum. --- src/intel/compiler/brw_eu_defines.h | 31 --- src/intel/compiler/brw_reg_type.c | 31 +++ 2 files changed, 31 insertions(+), 31 deletions(-) diff --git

[Mesa-dev] [PATCH 20/25] i965: Move brw_reg_type_letters() as well

And add "to_" to the name for consistency with the other functions in this file. --- src/intel/compiler/brw_eu.c | 28 src/intel/compiler/brw_fs.cpp | 4 ++-- src/intel/compiler/brw_reg.h | 1 - src/intel/compiler/brw_reg_type.c | 30

[Mesa-dev] [PATCH 21/25] i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.c

--- src/intel/compiler/brw_disasm.c | 72 ++- src/intel/compiler/brw_reg_type.c | 8 + src/intel/compiler/brw_reg_type.h | 4 +++ 3 files changed, 45 insertions(+), 39 deletions(-) diff --git a/src/intel/compiler/brw_disasm.c

[Mesa-dev] [PATCH 19/25] i965: Switch to using the logical register types

--- src/intel/compiler/brw_eu_compact.c | 27 --- src/intel/compiler/brw_eu_emit.c| 13 +++-- 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c index

[Mesa-dev] [PATCH 17/25] i965: Rename brw_inst's functions that access the register type

Put hw_ in the name so that it's clear these are the hardware encodings. --- src/intel/compiler/brw_disasm.c | 22 src/intel/compiler/brw_eu_compact.c | 22 src/intel/compiler/brw_eu_emit.c| 18 +++ src/intel/compiler/brw_eu_validate.c| 28 +-

[Mesa-dev] [PATCH 18/25] i965: Add functions to abstract access to register types

Previously the brw_inst{,_set}_{dst,src0,src1}_reg_type() functions provided access to the hardware encodings for the register types. We often mixed these with the logical BRW_REGISTER_TYPE_* enums (which themselves used to be the hardware format!) with bad results. With that functionality now

[Mesa-dev] [PATCH 15/25] i965: Add a brw_hw_type_to_reg_type() function

Will be used in later commits. --- src/intel/compiler/brw_reg_type.c | 25 + src/intel/compiler/brw_reg_type.h | 4 2 files changed, 29 insertions(+) diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index b0696570e5..8da93ae1cb

[Mesa-dev] [PATCH 16/25] i965: Index brw_hw_reg_type_to_size()'s table by logical type

I'll be transitioning everything to use the logical types. --- src/intel/compiler/brw_reg_type.c | 58 +-- 1 file changed, 19 insertions(+), 39 deletions(-) diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index

[Mesa-dev] [PATCH 13/25] i965: Extract functions dealing with register types to separate file

I'm going to encapsulate all of the logic dealing with register types in this file. Rename the parameters for the hardware encodings from type -> hw_type at the same time. --- src/intel/Makefile.sources| 2 + src/intel/compiler/brw_eu_emit.c | 102 --

[Mesa-dev] [PATCH 14/25] i965: Use a common table to translate logical to hardware types

--- src/intel/compiler/brw_reg_type.c | 65 +-- 1 file changed, 29 insertions(+), 36 deletions(-) diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index 8aac0ca009..b0696570e5 100644 --- a/src/intel/compiler/brw_reg_type.c

[Mesa-dev] [PATCH 12/25] i965: Reverse file/type arguments to register type functions

I think of the initial arguments as "state" and the last as the actual subject. --- src/intel/compiler/brw_disasm.c | 4 ++-- src/intel/compiler/brw_eu_emit.c | 14 -- src/intel/compiler/brw_eu_validate.c | 2 +- src/intel/compiler/brw_reg.h | 8 4 files

[Mesa-dev] [PATCH 11/25] i965: Add support for disassembling 64-bit integer immediates

After the last patch converted things into enums, I helpfully got a compiler warning about these missing from the switch statement. --- src/intel/compiler/brw_disasm.c | 6 ++ src/intel/compiler/brw_inst.h | 7 +++ 2 files changed, 13 insertions(+) diff --git

[Mesa-dev] [PATCH 07/25] i965: Don't let raw-move check be tricked by immediate vector types

UB and B type encodings are the same as UV and VF. Noticed when writing the following patch. --- src/intel/compiler/brw_eu_validate.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c

[Mesa-dev] [PATCH 10/25] i965: Use separate enums for register vs immediate types

The hardware encodings often mean different things depending on whether the source is an immediate. --- src/intel/compiler/brw_disasm.c | 46 --- src/intel/compiler/brw_eu_compact.c | 8 +-- src/intel/compiler/brw_eu_defines.h | 48 +--

[Mesa-dev] [PATCH 09/25] i965: Reorder brw_reg_type enum values

These vaguely corresponded to the hardware encodings, but that is purely historical at this point. Reorder them so we stop making things "almost work" when mixing enums. The ordering has been closen so that no enum value is the same as a compatible hardware encoding. ---

[Mesa-dev] [PATCH 06/25] i965: Only change type of 0.0f to VF if destination stride == 1

The destination stride must be equivalent to a dword if VF is used. Also, since the only compaction table entires with "i:vf" have the destination as "r:f" specifically check that the destination is of type float. --- src/intel/compiler/brw_eu_compact.c | 3 ++- 1 file changed, 2 insertions(+),

[Mesa-dev] [PATCH 05/25] i965: Remove CONT/BREAK from instruction compaction test

These cannot be compacted. A similar mistake was fixed in commit 90eaf01616a8 --- src/intel/compiler/test_eu_compact.cpp | 4 1 file changed, 4 deletions(-) diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp index 668a972bfa..1532e3b984 100644 ---

[Mesa-dev] [PATCH 08/25] i965: Validate destination restrictions with vector immediates

--- src/intel/compiler/brw_eu_emit.c| 13 +- src/intel/compiler/brw_eu_validate.c| 61 + src/intel/compiler/test_eu_validate.cpp | 79 + 3 files changed, 141 insertions(+), 12 deletions(-) diff --git

[Mesa-dev] [PATCH 04/25] i965: Test instruction compaction on all supported Gens

Note that there's no point in testing on G45, since its compaction is the same as Gen5. Same logic applies to Gen7 variants and low-power parts. --- src/intel/compiler/test_eu_compact.cpp | 50 -- 1 file changed, 42 insertions(+), 8 deletions(-) diff --git

[Mesa-dev] [PATCH 01/25] i965: Mark src inst pointer const in compaction code

--- src/intel/compiler/brw_eu.h | 2 +- src/intel/compiler/brw_eu_compact.c | 23 --- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index a3a9c63239..8e597b212a 100644 ---

[Mesa-dev] [PATCH 00/25] i965: Switch to always using logical register types

The mixture of hardware encodings and logical types has caused lots of confusion. It's time to fix that. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH 03/25] i965: Silence signed/unsigned comparison warning

--- src/intel/compiler/test_eu_compact.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp index 39e7f1a27c..1ef7e5ae7f 100644 --- a/src/intel/compiler/test_eu_compact.cpp +++

[Mesa-dev] [PATCH 02/25] i965: Move compaction "prepass" into brw_eu_compact.c

--- src/intel/compiler/brw_eu_compact.c | 82 - src/intel/compiler/brw_eu_emit.c| 72 +--- 2 files changed, 82 insertions(+), 72 deletions(-) diff --git a/src/intel/compiler/brw_eu_compact.c

Re: [Mesa-dev] [PATCH 09/12] egl/x11: pass NULL instead of XCB_WINDOW_NONE as native_surface

Thanks. I wrote the same patch some time ago, but never had a chance to send it out. I'll send you another patch that I wrote to clear up some of this confusion. I put it in my series immediately before this patch. Feel free to add it to yours. Reviewed-by: Matt Turner <matts...@gmail.

[Mesa-dev] [PATCH] egl: Clean up native_type vs drawable mess

The next patch is going to stop passing XCB_WINDOW_NONE (of type xcb_window_enum_t) as an argument where these functions expect a void *, which clang does not appreciate. This patch cleans things up to better convince me and reviewers that it's safe to do that. ---

Re: [Mesa-dev] [PATCH 03/11] i965/blit: Stop asserting linear row_pitches are 64B-aligned

Ken committed this as 595a47b8293 earlier today. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 1/4] nir: add new convergent, uniform-control, and cross-thread attributes

On Mon, Jul 31, 2017 at 7:02 PM, Connor Abbott wrote: > From: Connor Abbott > > These are properties of the instruction that must be respected when > moving it around, in addition to the usual SSA dominance guarantee. > Previously, we only had

Re: [Mesa-dev] [PATCH 1/3] nir: fix algebraic optimizations

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] mesa: fix bad cast conversions in viewport()

On Mon, Jul 31, 2017 at 12:43 PM, Samuel Pitoiset wrote: > Fixes: ddc32537d6 ("mesa: clamp viewport values only once when using > glViewport()") > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101981 > Bugzilla:

Re: [Mesa-dev] [PATCH] i965: Prefer using streaming reads from WC mmaps

Yep, seems like a good idea. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/2] i965: simplify intel_image_format_lookup()

Both are Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] docs: Update feature list for GL 4.6

On Mon, Jul 31, 2017 at 9:43 AM, Adam Jackson wrote: > ARB_polygon_offset_clamp and ARB_texture_filter_anisotropic look like > they'd be pretty trivial to wire up. > > Signed-off-by: Adam Jackson > --- > docs/features.txt | 22 ++ > 1 file

Re: [Mesa-dev] [PATCH] i965: Support the mesa_no_error driconf option.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH V3] i965 : Optimize atom state flag checks

On 07/21, aravindan.muthuku...@intel.com wrote: From: Aravindan Muthukumar This patch improves CPI Rate(Cycles per Instruction) and branch miss predict for i965. The function check_state() was showing CPI retired rate. Performance stats with android: - CPI

Re: [Mesa-dev] [PATCH 03/20] nir: Support lowering vote intrinsics

On Tue, Jul 18, 2017 at 1:34 PM, Connor Abbott <cwabbo...@gmail.com> wrote: > On Mon, Jul 10, 2017 at 10:18 AM, Matt Turner <matts...@gmail.com> wrote: >> On Thu, Jul 6, 2017 at 8:04 PM, Connor Abbott <cwabbo...@gmail.com> wrote: >>> On Thu, Jul 6, 2017 at 4:48

Re: [Mesa-dev] [PATCH] egl/wayland: Fix linking libEGL_common.la

On Thu, Jul 20, 2017 at 1:25 PM, Mike Lothian wrote: > Because libmesautil.la includes string_to_uint_map.o, -lstdc++ is > required for linking to succeed > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101851 > > Signed-off-by: Mike Lothian >

Re: [Mesa-dev] [PATCH 20/20] nir: Narrow unnecessary 64-bit operations to 32-bits

On Mon, Jul 17, 2017 at 8:14 PM, Connor Abbott <cwabbo...@gmail.com> wrote: > On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner <matts...@gmail.com> wrote: >> If we know the high bits are zero, we can just do a 32-bit comparison on >> the low bytes instead.

Re: [Mesa-dev] [PATCH] nir: Use nir_src_copy instead of direct assignments.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 20/20] nir: Narrow unnecessary 64-bit operations to 32-bits

On Mon, Jul 17, 2017 at 5:57 PM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Thursday, July 6, 2017 4:48:30 PM PDT Matt Turner wrote: >> If we know the high bits are zero, we can just do a 32-bit comparison on >> the low bytes instead. >> --- >> src/compi

Re: [Mesa-dev] [PATCH 10/20] nir: Add pass to scalarize read_invocation/read_first_invocation

On Mon, Jul 17, 2017 at 5:10 PM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Thursday, July 6, 2017 4:48:20 PM PDT Matt Turner wrote: >> i965 will want these to be scalar operations. >> --- >> src/compiler/Makefile.sources | 1 +

Re: [Mesa-dev] [PATCH 06/20] i965/fs: Implement ARB_shader_group_vote operations

On Mon, Jul 17, 2017 at 4:44 PM, Kenneth Graunke <kenn...@whitecape.org> wrote: > On Thursday, July 6, 2017 4:48:16 PM PDT Matt Turner wrote: >> --- >> src/intel/compiler/brw_fs_nir.cpp | 36 >> 1 file changed, 36 insertions(+) &

Re: [Mesa-dev] [PATCH 01/20] nir: Add intrinsics from ARB_shader_group_vote

I've force pushed this series with all suggested changes to the ballot branch of my tree git://people.freedesktop.org/~mattst88/mesa ballot The only two reviews I have so far are my own, after changing the authorship on two patches to Curro. With the branchpoint coming up this week, I'd

Re: [Mesa-dev] [PATCH 05/20] i965/fs: Handle explicit flag destinations in flags_written()

On Fri, Jul 14, 2017 at 3:23 PM, Francisco Jerez <curroje...@riseup.net> wrote: > Matt Turner <matts...@gmail.com> writes: > >> The implementations of the ARB_shader_group_vote intrinsics will >> explicitly write the flag as the destination register. >> --- &g

Re: [Mesa-dev] [PATCH 12/20] i965/fs: Handle explicit flag sources in flags_read()

On Fri, Jul 14, 2017 at 5:52 PM, Francisco Jerez <curroje...@riseup.net> wrote: > Matt Turner <matts...@gmail.com> writes: > >> The implementations of the ARB_shader_ballot intrinsics will explicitly >> read the flag as a source register. >> --- &g

Re: [Mesa-dev] [PATCH 11/20] i965/fs: Allow emit_uniformize() to broadcast a specific channel

On Fri, Jul 14, 2017 at 5:48 PM, Francisco Jerez wrote: > I don't like re-using emit_uniformize() (which is supposed to give you > the value of a channel of the input it can prove live as the doxygen > comment explains), as a "fetch me the i-th channel of the source" >

Re: [Mesa-dev] [PATCH] i965: Compile with -msse3

On Fri, Jul 14, 2017 at 6:36 PM, Ian Romanick <i...@freedesktop.org> wrote: > On 07/14/2017 06:35 PM, Ian Romanick wrote: >> On 07/14/2017 12:19 PM, Matt Turner wrote: >>> All CPUs that can be paired with a GPU supported by i965_dri.so supports >>> SSE3. T

Re: [Mesa-dev] [PATCH] dri: Make classic drivers allow __DRI_CTX_FLAG_NO_ERROR.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: Use a ZERO() macro to initialize GENX_* structs.

On Fri, Jul 14, 2017 at 12:27 PM, Rafael Antognolli <rafael.antogno...@intel.com> wrote: > On Fri, Jul 14, 2017 at 12:13:59PM -0700, Matt Turner wrote: >> On Fri, Jul 14, 2017 at 11:15 AM, Rafael Antognolli >> <rafael.antogno...@intel.com> wrote: >>

[Mesa-dev] [PATCH] i965: Compile with -msse3

All CPUs that can be paired with a GPU supported by i965_dri.so supports SSE3. This allows us to ensure that some vectorized version of the tiled memcpy path is enabled on 32-bit systems. This also ensures that __builtin_ia32_clflush is always usable. Bugzilla:

Re: [Mesa-dev] [PATCH] i965: Use a ZERO() macro to initialize GENX_* structs.

; - for (struct cmd name = { 0, }, \ > + for (struct cmd name = ZERO(struct cmd),\ Why don't we just use the GNU C extension {}? Clang supports it. That would get my Reviewed-by: Matt Turner <matts...@gmail.com>

Re: [Mesa-dev] [PATCH] anv/pipeline: use BITFIELD64_BIT() to check enable vertex inputs

+ if (inputs_read & BITFIELD64_BIT(VERT_ATTRIB_GENERIC0 + > desc->location)) The BITFIELD64_BIT macro exists just for MSVC support (See commit 5fc5820cbc0faf57a48154466b4792294841a690) Since this code will never be compiled with MSVC, it's safe to use 1ull. I'm not really sure how mt

Re: [Mesa-dev] [PATCH 09/20] nir: Add system values from ARB_shader_ballot

On Mon, Jul 10, 2017 at 4:05 PM, Connor Abbott <cwabbo...@gmail.com> wrote: > On Mon, Jul 10, 2017 at 3:50 PM, Matt Turner <matts...@gmail.com> wrote: >> On Mon, Jul 10, 2017 at 1:10 PM, Connor Abbott <cwabbo...@gmail.com> wrote: >>> On Thu, Jul 6, 2017 at 4:48

Re: [Mesa-dev] [PATCH 09/20] nir: Add system values from ARB_shader_ballot

On Mon, Jul 10, 2017 at 1:10 PM, Connor Abbott <cwabbo...@gmail.com> wrote: > On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner <matts...@gmail.com> wrote: >> We already had a channel_num system value, which I'm renaming to >> subgroup_invocation to match the rest of the ne

Re: [Mesa-dev] [PATCH 00/11] i965: UBO pushing for fun and profit?

ss... > > I figured I'd at least send it out for an initial review, and we can > continue collecting benchmark data... The series looks good to me. I'm not the ideal person to review state upload changes, so take that review for what its worth. Reviewed-by: Matt Turner <matts...@gmail.com>

Re: [Mesa-dev] [PATCH 11/11] i965: Use pushed UBO data in the scalar backend.

On Thu, Jul 6, 2017 at 5:22 PM, Kenneth Graunke wrote: > This actually takes advantage of the newly pushed UBO data, avoiding > pull loads. > > XXX: quote performance numbers > --- > src/intel/compiler/brw_fs.cpp | 35 ++- >

Re: [Mesa-dev] [PATCH 03/11] i965: Select ranges of UBO data to be uploaded as push constants.

On Thu, Jul 6, 2017 at 5:22 PM, Kenneth Graunke wrote: > This adds a NIR pass that decides which portions of UBOS we should > upload as push constants, rather than pull constants. > --- > src/intel/Makefile.sources | 1 + >

[Mesa-dev] [PATCH 18/20] i965/fs: Match destination type to size for ballot

No use in taking a 64-bit value when we know the high 32-bits are zero. --- v2: Update for v2 of 16/20 (Connor) src/intel/compiler/brw_compiler.c | 2 +- src/intel/compiler/brw_fs_nir.cpp | 6 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_compiler.c

[Mesa-dev] [PATCH 16/20] nir: Reduce destination size of ballot intrinsic when possible

Some hardware, like i965, doesn't support group sizes greater than 32. In that case, we can reduce the destination size of the ballot intrinsic, which will simplify our code generation. --- v2: Just change the intrinsic size, and don't add a new intrinsic (Connor) src/compiler/nir/nir.h

Re: [Mesa-dev] [PATCH 16/20] nir: Add a ballot32 intrinsic

On Thu, Jul 6, 2017 at 7:39 PM, Connor Abbott wrote: > I've thought about this a little bit, and I think we'd rather just > decrease the bitsize of the intrinsic rather than add a whole new one. > The separate intrinsic isn't really buying you anything, I don't think > it's

Re: [Mesa-dev] [PATCH 03/20] nir: Support lowering vote intrinsics

On Thu, Jul 6, 2017 at 8:04 PM, Connor Abbott <cwabbo...@gmail.com> wrote: > On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner <matts...@gmail.com> wrote: >> ... trivially (as allowed by the spec!) by reusing the existing >> nir_opt_intrinsics code. >> --- >> sr

Re: [Mesa-dev] [PATCH 1/2] mesa/marshal: extract ClearBuffer helpers

On Sun, Jul 9, 2017 at 9:21 AM, Grigori Goronzy wrote: > Extract clear buffer helper functions in preparation for adding > marshal/unmarshal functions for the various glClearBuffer variants. > --- > src/mesa/main/marshal.c | 74 >

Re: [Mesa-dev] [PATCH] anv: Stop setting domains to RENDER on EXEC_OBJECT_WRITE

On Sat, Jul 8, 2017 at 11:05 AM, Jason Ekstrand wrote: > On July 7, 2017 1:52:54 PM Chris Wilson wrote: > >> Quoting Jason Ekstrand (2017-07-07 21:37:29) >>> >>> The reason we were doing this was to ensure that the kernel did the >>> appropriate

Re: [Mesa-dev] [PATCH 01/20] nir: Add intrinsics from ARB_shader_group_vote

On Thu, Jul 6, 2017 at 5:07 PM, Connor Abbott wrote: > FYI, I already have another series which adds ARB_shader_ballot and > ARB_shader_group_vote intrinsics, in addition to adding some more > precise semantics to represent the restrictions on ballotARB() and > similar things

[Mesa-dev] [PATCH 20/20] nir: Narrow unnecessary 64-bit operations to 32-bits

If we know the high bits are zero, we can just do a 32-bit comparison on the low bytes instead. --- src/compiler/nir/nir_opt_algebraic.py | 14 +- src/compiler/nir/nir_search_helpers.h | 48 +++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 18/20] i965/fs: Add support for ballot32

No use in taking a 64-bit value when we know the high 32-bits are zero. --- src/intel/compiler/brw_compiler.c | 2 +- src/intel/compiler/brw_fs_nir.cpp | 9 +++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_compiler.c

[Mesa-dev] [PATCH 17/20] i965: Normalize types for FBL, FBH, etc

Allows the instructions to be compacted. The documentation claims that some of these only accept UD types, even though the type doesn't change the operation performed. Just normalize the types to ensure we get instruction compaction. The only functional changes are for FBL and CBIT (always use UD

[Mesa-dev] [PATCH 15/20] i965: Enable ARB_shader_ballot on Gen8+

--- docs/features.txt| 2 +- docs/relnotes/17.2.0.html| 1 + src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/features.txt b/docs/features.txt index ec78447e88..1f628e1c03 100644

[Mesa-dev] [PATCH 19/20] nir: Optimize find_lsb/imsb/umsb error checks

Two of the ARB_shader_ballot piglit tests hit the find_lsb case, removing some of the noise allowed me to better debug the test when it was failing. --- src/compiler/nir/nir_opt_algebraic.py | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/compiler/nir/nir_opt_algebraic.py

[Mesa-dev] [PATCH 12/20] i965/fs: Handle explicit flag sources in flags_read()

The implementations of the ARB_shader_ballot intrinsics will explicitly read the flag as a source register. --- src/intel/compiler/brw_fs.cpp | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index

[Mesa-dev] [PATCH 14/20] i965/fs: Implement ARB_shader_ballot operations

--- src/intel/compiler/brw_fs_nir.cpp | 41 +++ src/intel/compiler/brw_nir.c | 1 + 2 files changed, 42 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 17f35e081d..25e9b703eb 100644 ---

[Mesa-dev] [PATCH 16/20] nir: Add a ballot32 intrinsic

Some hardware, like i965, doesn't support group sizes greater than 32. In that case, we can use the ballot32 intrinsic instead, which will simplify our code generation. --- src/compiler/nir/nir.h| 2 ++ src/compiler/nir/nir_intrinsics.h | 3 +++

[Mesa-dev] [PATCH 13/20] i965/fs: Do not move MOVs writing the flag outside of control flow

The implementation of ballotARB() will start by zeroing the flags register. So, a doing something like if (gl_SubGroupInvocationARB % 2u == 0u) { ... = ballotARB(true); [...] } else { ... = ballotARB(true); [...]

[Mesa-dev] [PATCH 07/20] i965: Enable ARB_shader_group_vote

--- docs/features.txt| 2 +- docs/relnotes/17.2.0.html| 1 + src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/features.txt b/docs/features.txt index 79b71de543..ec78447e88 100644

[Mesa-dev] [PATCH 09/20] nir: Add system values from ARB_shader_ballot

We already had a channel_num system value, which I'm renaming to subgroup_invocation to match the rest of the new system values. Note that while ballotARB(true) will return zeros in the high 32-bits on systems where gl_SubGroupSizeARB <= 32, the gl_SubGroup??MaskARB variables do not consider

[Mesa-dev] [PATCH 08/20] nir: Add intrinsics from ARB_shader_ballot

--- src/compiler/glsl/glsl_to_nir.cpp | 45 +++ src/compiler/nir/nir_intrinsics.h | 13 +++ 2 files changed, 58 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 43d7e07042..23632f27c2 100644 ---

[Mesa-dev] [PATCH 06/20] i965/fs: Implement ARB_shader_group_vote operations

--- src/intel/compiler/brw_fs_nir.cpp | 36 1 file changed, 36 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index a9dce42c38..264398f38e 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH 11/20] i965/fs: Allow emit_uniformize() to broadcast a specific channel

This function will be used to implement read_invocation (by specifying a specific channel) and read_first_invocation (by not specifying a channel). --- src/intel/compiler/brw_fs_builder.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 10/20] nir: Add pass to scalarize read_invocation/read_first_invocation

i965 will want these to be scalar operations. --- src/compiler/Makefile.sources | 1 + src/compiler/nir/nir.h | 2 +- .../nir/nir_lower_read_invocation_to_scalar.c | 112 + 3 files changed, 114 insertions(+), 1

[Mesa-dev] [PATCH 05/20] i965/fs: Handle explicit flag destinations in flags_written()

The implementations of the ARB_shader_group_vote intrinsics will explicitly write the flag as the destination register. --- src/intel/compiler/brw_fs.cpp | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp

[Mesa-dev] [PATCH 02/20] nir: Add pass to optimize intrinsics

Specifically, constant fold intrinsics from ARB_shader_group_vote, but I suspect it'll be useful for other things in the future. --- src/compiler/Makefile.sources | 1 + src/compiler/nir/nir.h| 2 + src/compiler/nir/nir_opt_intrinsics.c | 102

[Mesa-dev] [PATCH 04/20] i965/vec4: Lower ARB_shader_group_vote intrinsics

I don't expect anyone is going to care about using this in vec4 programs (vertex/tessellation/geometry on Gen6/7), no one has come up with a good way to implement it much less test it. --- src/intel/compiler/brw_compiler.c | 3 +++ 1 file changed, 3 insertions(+) diff --git

[Mesa-dev] [PATCH 03/20] nir: Support lowering vote intrinsics

... trivially (as allowed by the spec!) by reusing the existing nir_opt_intrinsics code. --- src/compiler/nir/nir.h| 4 src/compiler/nir/nir_opt_intrinsics.c | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir.h

[Mesa-dev] [PATCH 01/20] nir: Add intrinsics from ARB_shader_group_vote

These are intrinsics rather than opcodes, because they operate across channels. --- src/compiler/glsl/glsl_to_nir.cpp | 22 ++ src/compiler/nir/nir_intrinsics.h | 5 + 2 files changed, 27 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.cpp

Re: [Mesa-dev] [PATCH 1/3] intel/drm: Pull in the i916 fence array API

s/i916/i965/ in title. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 1/3] util: Add util_strncpy

On Sun, Jul 2, 2017 at 8:49 PM, Robert Foss wrote: > Add strncpy wrapper that makes sure that the string is always ends > with a null byte. Otherwise known as strlcpy()? ___ mesa-dev mailing list

Re: [Mesa-dev] [PATCH] i965: Print access flags in INTEL_DEBUG=buf output.

Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH mesa] build systems: uniformize git_sha1.h generation

Right you are. Thanks. Reviewed-by: Matt Turner <matts...@gmail.com> ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

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