Re: [Mesa-dev] Mesa Library questions

, function install_vtxfmt SET_Begin(tab, vfmt-Begin); SET_Begin calls a macro (SET_by_offset) mapping the vbo_exec_Begin to glBegin. The macro is located in dispatch.h Hope it helps you, Pierre Moreau On 27 juil. 2013, at 03:18, ZhiLi ditto_zh...@hotmail.com wrote: Hello everyone, I am

Re: [Mesa-dev] [Nouveau] [PATCH] nv50/ir: only enable mul saturate on G200+

Tested-by: Pierre Moreau pierre.mor...@free.fr - Mail original - Commit 44673512a84 enabled support for saturating fmul. However experimentally this does not seem to work on the older chips. Restrict the feature to G200 (NVA0) and later. Reported-by: Pierre Moreau pierre.mor

Re: [Mesa-dev] [PATCH v2 3/4] nv50: move HW queries to nv50_query_hw.c/h files

Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> On 06:24 PM - Oct 28 2015, Samuel Pitoiset wrote: > Changes since v2: > - remove unused 'nv50_hw_query_funcs' struct > > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- > src/gallium/drivers/nouvea

Re: [Mesa-dev] [PATCH 2/4] nv50: move nva0_so_target_save_offset() to its correct location

Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> On 11:30 PM - Oct 18 2015, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- > src/gallium/drivers/nouveau/nv50/nv50_query.c | 18 -- > src/gallium/drivers/nouvea

Re: [Mesa-dev] [PATCH v3 0/6] gallium: allow drivers to report debug info to st

On 01:15 AM - Oct 31 2015, Ilia Mirkin wrote: > I've switched the st/mesa impl around to be set in the manager, based > on whether it's a debug context. I've also added a st/clover impl > (entirely untested beyond compilation) as the OpenCL API appears to Tested on a Tesla card using the

Re: [Mesa-dev] [PATCH 4/4] nv50: do not create an invalid HW query type

Hi Samuel, (some comments below) On 11:36 PM - Oct 18 2015, Samuel Pitoiset wrote: > While we are at it, store the rotate offset for occlusion queries to > nv50_hw_query like on nvc0. > > Signed-off-by: Samuel Pitoiset > --- >

Re: [Mesa-dev] [PATCH 1/4] nv50: add a header file for nv50_query

Hi Samuel, (some comments further down) On 11:30 PM - Oct 18 2015, Samuel Pitoiset wrote: > Like for nvc0, this will allow to split different types of queries and > to prepare the way for both global performance counters and MP counters. > > While we are at it, make use of nv50_query struct

Re: [Mesa-dev] [PATCH 4/4] nv50: do not create an invalid HW query type

On 11:06 AM - Oct 19 2015, Samuel Pitoiset wrote: > > > On 10/19/2015 11:01 AM, Pierre Moreau wrote: > >Hi Samuel, > > > >(some comments below) > > > >On 11:36 PM - Oct 18 2015, Samuel Pitoiset wrote: > >>While we are at it, store the rotate offset

Re: [Mesa-dev] [PATCH 13/16] nvc0: enable compute support by default on Fermi

uot;. The former has actually been around for > >>> years, > >>> Samuel just fixed up a few fermi-specific bits. > >> > >> Can't we use LLVM IR-> TGSI -> nv IR for that? > > > > Sure, there's no LLVM IR -> TGSI conversion though. > > BTW, Pierre

Re: [Mesa-dev] [PATCH 5/5] nouveau: remove logically dead code in nouveau_vpe_mb_mv_header()

On 11:14 AM - Dec 14 2015, Samuel Pitoiset wrote: > frame cannot be NULL in that branch. Spotted by Coverity. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/nouveau_video.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH v2 2/3] nvc0: check return value of nvc0_program_validate()

On 11:56 AM - Dec 14 2015, Ilia Mirkin wrote: > No, gp->code_size is set by the validation. You need to put that last. IIRC, you can't assume in which order the compiler will decide to evaluate the different expressions being AND'ed. > > On Mon, Dec 14, 2015 at 11:51 AM, Samuel Pitoiset >

[Mesa-dev] [PATCH] nv50/ir: Fix scratch allocation size and file

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cpp | 4 ++-- src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/c

Re: [Mesa-dev] [PATCH] mesa: Enable LTO compilation

Ok, I found the answer to my question regarding the `-fno-lto`. IMHO that should be in the commit message, since the patch only checks for availability and disables LTO in one case, never enabling it explicitely. Please ignore my previous mail. Pierre On 11:06 AM - May 30 2016, Matt Turner

Re: [Mesa-dev] [PATCH] mesa: Enable LTO compilation

On 07:28 PM - May 30 2016, ⚛ wrote: > This patch enables compilation with -flto. > > The performance benefits of LTO (GCC 4.9 & 6.1) are about 1% for glxgears. > Performance changes in OpenGL games haven't been measured yet, my feeling > is that they are negligible. > diff --git a/configure.ac

Re: [Mesa-dev] [PATCH 3/3] nvc0: rework nvc0_compute_validate_program()

Hi Samuel, On 06:44 PM - Feb 24 2016, Samuel Pitoiset wrote: > Reduce the amount of duplicated code by re-using > nvc0_program_validate(). While we are at it, change the prototype > to return void and remove nvc0_compute.h which is now useless. Why don't you want to know whether the validation

Re: [Mesa-dev] [PATCH 1/3] nvc0: move nvc0_validate_global_residents() to nvc0_compute.c

idents?`, I would probably keep it in `nvc0_compute_validate_global_residents()`. Other than that, Acked-by: Pierre Moreau <pierre.mor...@free.fr> Pierre > +++i) { > + struct pipe_resource *res = *util_dynarray_element( > + >global_residents, s

Re: [Mesa-dev] [PATCH 2/3] nvc0: make sure to validate compute global buffers on Fermi

Acked-by: Pierre Moreau <pierre.mor...@free.fr> On 06:44 PM - Feb 24 2016, Samuel Pitoiset wrote: > No reason to not validate those global buffers and this might avoid > fails if someone try to use the global memory from compute programs. > > Signed-off-by: Samuel Pito

Re: [Mesa-dev] [PATCH 3/3] nvc0: rework nvc0_compute_validate_program()

On 08:44 PM - Feb 24 2016, Samuel Pitoiset wrote: > > > On 02/24/2016 08:30 PM, Pierre Moreau wrote: > >Hi Samuel, > > > >On 06:44 PM - Feb 24 2016, Samuel Pitoiset wrote: > >>Reduce the amount of duplicated code by re-using > >>nvc0_program_validat

[Mesa-dev] [PATCH] nv50/ir: Check for valid insn instead of defs size

to an instruction. Fixes a nullptr dereference in the register allocation pass, while running compute kernels that do not use $r0. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 del

Re: [Mesa-dev] [PATCH] nv50: do not advertise about compute shaders

Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> On 08:25 PM - Feb 19 2016, Samuel Pitoiset wrote: > Compute shaders are totally unsupported. This avoids Clover to > report that OpenCL is supported on Tesla because it's a lie. > > Signed-off-by: Samuel Pitoiset <samu

Re: [Mesa-dev] [Nouveau] [PATCH mesa 3/3] nouveau: Add support for clover / OpenCL kernel input parameters

On 11:05 AM - Mar 10 2016, Ilia Mirkin wrote: > On Thu, Mar 10, 2016 at 11:03 AM, Pierre Moreau <pierre.mor...@free.fr> wrote: > > You might want to increment the address by at least > > `info->prop.cp.inputOffset`, and if inputs still end up in shared on Tesla, > >

Re: [Mesa-dev] [Nouveau] [PATCH mesa 3/3] nouveau: Add support for clover / OpenCL kernel input parameters

On 04:27 PM - Mar 10 2016, Samuel Pitoiset wrote: > > > On 03/10/2016 04:23 PM, Ilia Mirkin wrote: > >On Thu, Mar 10, 2016 at 10:14 AM, Hans de Goede wrote: > >>Add support for clover / OpenCL kernel input parameters. > >> > >>Signed-off-by: Hans de Goede

Re: [Mesa-dev] [PATCH 4/5] nvc0: avoid using magic numbers for the uniform_bo offsets

NFO 0x180 /* FP */ > +#define NVC0_CB_AUX_SAMPLE_SIZE (8 * 4 * 2) > +/* draw parameters (index bais, base instance, drawid) */ > +#define NVC0_CB_AUX_DRAW_INFO 0x180 /* VP */ What is the status of this one? Is the region from 0x180 and after considered as the `AU

[Mesa-dev] [PATCH] nv50/ra: `isinf()` is in namespace `std` since C++11

This fixes a compile error while building Nouveau with C++11 enabled (and glibc >= 2.23). This happens if SWR is enabled, as it forces C++11. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 4 1 file changed, 4 i

[Mesa-dev] [PATCH] nv50, nvc0: Set only NEW_CP_GLOBALS upon binding

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/nv50/nv50_state.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state.c b/src/gallium/d

[Mesa-dev] [PATCH] nv50: Mark compute states as dirty on context switch

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/nv50/nv50_state_validate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c index 5

Re: [Mesa-dev] [PATCH] nouveau: Fix clang reserved-user-defined-literal error.

I did hit that issue as well, but I have C++11 forced on my SPIR-V branch. I guess adding the whitespace will still result in code that works with older C++ version, so the fix can still be accepted even if we do not plan to switch to C++11 by default. Pierre On 11:16 AM - Mar 09 2016, Samuel

[Mesa-dev] [PATCH 01/11] nv50/ir: Check for valid insn instead of def size

to an instruction. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/c

Re: [Mesa-dev] [PATCH 01/11] nv50/ir: Check for valid insn instead of def size

Hum… Something went wrong, sorry. This is the same as the previous patch and not the updated version… Pierre On 02:16 PM - Mar 13 2016, Pierre Moreau wrote: > On Tesla cards, the first register $r0 contains the thread id; later > generations use a specialised register for it. In order to p

[Mesa-dev] [PATCH v2] nv50/ir: Check for valid insn instead of def size

dereference during the register allocation pass, if a function had unused arguments. v2: Rewrite commit message based on Ilia Mirkin's comment Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 4 ++-- 1 file changed, 2 insertions

Re: [Mesa-dev] [PATCH v2] math: Import isinf and others to global namespace

:-( I'll have another look this evening. Which version of glibc did it failed with? (I saw your reply to the other patch, I'll dig deeper this evening.) Thanks! Pierre > On 13 Apr 2016, at 08:22, Jose Fonseca <jfons...@vmware.com> wrote: > >> On 01/04/16 13:18, Pierre Morea

[Mesa-dev] [PATCH v3] nv50/ir: Check for valid insn instead of def size

during the register allocation pass, if a function had unused arguments. v2: Rewrite commit message based on Ilia Mirkin's comment v3: Rewrite an incorrect statement in the commit message that was pointed out by Ilia Mirkin Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/g

Re: [Mesa-dev] [PATCH] nv50,nvc0: Fix invalid constant.

On 06:34 PM - Mar 18 2016, Vinson Lee wrote: > Fix clang build error. > > CXX codegen/nv50_ir_lowering_nvc0.lo > codegen/nv50_ir_lowering_nvc0.cpp:1783:42: error: invalid suffix 'd' on > floating constant > Value *zero = bld.loadImm(NULL, 0.0d); >

Re: [Mesa-dev] [PATCH 1/5] nv50, nvc0: replace resInfoCBSlot by auxCBSlot

Acked-by: Pierre Moreau <pierre.mor...@free.fr> On 09:55 PM - Mar 15 2016, Samuel Pitoiset wrote: > Having two different variables for the driver constant buffer slot > is confusing and really useless. > > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> >

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

6 at 5:56 PM, Pierre Moreau <pierre.mor...@free.fr> wrote: > > Generating a `cvt u32 $r0 u64 $r1d` or a `cvt u64 $r0d u32 $r2` makes the > > GPU > > unhappy. Instead, manually handle the conversion between 64-bit and 32-bit > > values, and use `cvt` to convert between the

[Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

Two 32-bit MAD or MUL operations are generated in place of the original 64-bit operation. All operands can either be signed or unsigned, but they have to be integers. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cp

[Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 59 ++ .../nouveau/codegen/nv50_ir_lowering_nvc0.h| 1 + 2 files changed, 60 insertions(+) diff --git a/src/gallium/drivers/nouveau/c

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

On 06:24 PM - Mar 19 2016, Ilia Mirkin wrote: > On Sat, Mar 19, 2016 at 6:15 PM, Pierre Moreau <pierre.mor...@free.fr> wrote: > > On 06:05 PM - Mar 19 2016, Ilia Mirkin wrote: > >> Not 100% sure, but pretty sure this is wrong. Can you provide the > >> generated seq

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

On 06:26 PM - Mar 19 2016, Ilia Mirkin wrote: > On Sat, Mar 19, 2016 at 6:26 PM, Pierre Moreau <pierre.mor...@free.fr> wrote: > > However, you could have some `long bar; char foo = convert_char_sat(bar);` > > in > > the OpenCL kernel. > > Sure, but the

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

On 06:41 PM - Mar 19 2016, Ilia Mirkin wrote: > On Sat, Mar 19, 2016 at 6:36 PM, Pierre Moreau <pierre.mor...@free.fr> wrote: > > On 06:26 PM - Mar 19 2016, Ilia Mirkin wrote: > >> On Sat, Mar 19, 2016 at 6:26 PM, Pierre Moreau <pierre.mor...@free.fr> > >>

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

ting each of my mads to mul + add… > > On Sat, Mar 19, 2016 at 5:56 PM, Pierre Moreau <pierre.mor...@free.fr> wrote: > > Two 32-bit MAD or MUL operations are generated in place of the original > > 64-bit > > operation. All operands can either be signed or unsigned

Re: [Mesa-dev] [PATCH 2/5] nv50/ir: make use of auxCBSlot instead of magic numbers

he slot remains needed for Tesla. (Tesla will keep hunting you! :-p) Global and const memory are not completely the same, so I'm somewhat reluctant to reuse the same variable slot for both of them. But, I'm just giving my 2cents here, so feel free to keep as is. Regardless of your pick, this i

[Mesa-dev] [PATCH] nvc0/ir: Use double constant in `handleSQRT()`

Fixes: commit a100d89d09981d2ebb42a7e4643a48e78db8dfe3 Author: Vinson Lee <v...@freedesktop.org> Date: Fri Mar 18 18:28:28 2016 -0700 nv50,nvc0: Fix invalid constant. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nou

[Mesa-dev] [PATCH v2] nvc0/ir: Use double constant in `handleSQRT()`

v2: Use "Fixes: sha1 (subject)" format for the fixes section, as pointed out by Ilia Mirin Fixes: a100d89d0998 ("nv50,nvc0: Fix invalid constant.") Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp

Re: [Mesa-dev] [PATCH 0/7] nv50: rework compute/3d validation path

This serie is: Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> Tested-by: Pierre Moreau <pierre.mor...@free.fr> Pierre On 08:54 PM - Mar 15 2016, Samuel Pitoiset wrote: > From: Samuel Pitoiset <samuel.pitoi...@gmail.com> > > Hi, > > This is loosely based on

Re: [Mesa-dev] [PATCH] nv50/ra: `isinf()` is in namespace `std` since C++11

0, Ilia Mirkin wrote: >>>>>> >>>>>> >>>>>> >>>>>> On Mar 17, 2016 8:27 PM, "Matt Turner" <matts...@gmail.com >>>>>> <mailto:matts...@gmail.com>> wrote: >>&g

Re: [Mesa-dev] [PATCH] nv50/ir: Check for valid insn instead of defs size

to do with $r0, but it does have something > to do with the fact that nv50 compute makes use of function arguments > for compute programs. That's what I meant to write, but reading it again, it is confusing. I'll rewrite it. Pierre > > -ilia > > On Wed, Feb 24, 2016 at 8

[Mesa-dev] [PATCH v2] math: Import isinf and others to global namespace

the fix outside of Nouveau, as suggested by Jose Fonseca, since anyone might need it when GCC switches to C++14 by default with GCC 6.0. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- include/cpp11_math.h| 61 + src/gallium/aux

Re: [Mesa-dev] [PATCH v2] math: Import isinf and others to global namespace

On 01:11 PM - Apr 01 2016, Jose Fonseca wrote: > On 31/03/16 23:08, Pierre Moreau wrote: > >Starting from C++11, several math functions, like isinf, moved into the std > >namespace. Since cmath undefines those functions before redefining them > >inside > >the namesp

Re: [Mesa-dev] [PATCH 1/2] nvc0: clear out surfaces bufctx before rebinding everything

On 09:28 PM - May 18 2016, Ilia Mirkin wrote: > Otherwise we can end up in a situation where that bin just grows and > grows. > > Signed-off-by: Ilia Mirkin > --- > src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git

[Mesa-dev] [PATCH] nv50/ir: Add missing handling of U64/S64 in inlines

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- U64/S64 support is missing in other places of codegen (like in nv50_ir_peephole.cpp for example), however its absence will result in code not being as optimised as it could have. Adding that support is not as straight forward as this

[Mesa-dev] [PATCH v3] math: Import isinf and others to global namespace

checks, as only glibc > =2.23 defines isinf & co. as functions, as suggested by Jose Fonseca. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- include/c99_math.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/include/c99_math.h b/include/c99

Re: [Mesa-dev] [RFC 04/24] nvc0: bind images on 3D shaders for Kepler

On 01:56 AM - Apr 13 2016, Samuel Pitoiset wrote: > Similar to surfaces validation for compute shaders. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +++- > src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 26 >

Re: [Mesa-dev] [PATCH v3] math: Import isinf and others to global namespace

eck logic and pushed. > > Jose > > On 14/04/16 19:43, Pierre Moreau wrote: > >Starting from C++11, several math functions, like isinf, moved into the std > >namespace. Since cmath undefines those functions before redefining them > >inside > >the namespace

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

On 11:21 AM - Apr 18 2016, Hans de Goede wrote: > Hi, > > On 17-04-16 22:27, Pierre Moreau wrote: > >On 04:17 PM - Apr 17 2016, Ilia Mirkin wrote: > >>On Sun, Apr 17, 2016 at 4:07 PM, Pierre Moreau <pierre.mor...@free.fr> > >>wrote: > >>>Pi

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

On 04:17 PM - Apr 17 2016, Ilia Mirkin wrote: > On Sun, Apr 17, 2016 at 4:07 PM, Pierre Moreau <pierre.mor...@free.fr> wrote: > > Ping :-) > > > > On 10:56 PM - Mar 19 2016, Pierre Moreau wrote: > >> Generating a `cvt u32 $r0 u64 $r1d` or a `cvt u64 $r0d u32 $

Re: [Mesa-dev] [PATCH] nvc0/lowering: Handle conversions to U64/S64 manually

Ping :-) On 10:56 PM - Mar 19 2016, Pierre Moreau wrote: > Generating a `cvt u32 $r0 u64 $r1d` or a `cvt u64 $r0d u32 $r2` makes the GPU > unhappy. Instead, manually handle the conversion between 64-bit and 32-bit > values, and use `cvt` to convert between the original target (res

Re: [Mesa-dev] [RFC 01/24] nvc0: add preliminary support for images

On 01:56 AM - Apr 13 2016, Samuel Pitoiset wrote: > This implements set_shader_images() and resource invalidation for > images. As OpenGL requires at least 8 images, we are going to expose > this minimum value even if this might be raised for Kepler, but this > limit is mainly for Fermi because

Re: [Mesa-dev] [RFC 1/3] tgsi: Add WORK_DIM System Value

On 05:43 PM - Apr 27 2016, Samuel Pitoiset wrote: > > > On 04/27/2016 05:24 PM, Ilia Mirkin wrote: > >On Wed, Apr 27, 2016 at 11:19 AM, Hans de Goede wrote: > >>Hi, > >> > >>On 27-04-16 16:49, Ilia Mirkin wrote: > >>> > >>>Please add this semantic to src/gallium/docs and

Re: [Mesa-dev] [PATCH] nv50/ir: always return 0 when trying to read thread id along unit dim

Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> On 10:20 pm - Jan 25 2017, Ilia Mirkin wrote: > Many many many compute shaders only define a 1- or 2-dimensional block, > but then continue to use system values that take the full 3d into > account (like gl_LocalInvocation

[Mesa-dev] [PATCH] nv50/ir: check for origin insn in findOriginForTestWithZero

Function arguments do not have an "origin" instruction, causing a NULL-pointer dereference without this check. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --g

Re: [Mesa-dev] [PATCH] nvc0: allow TK1 (NVEA) queries to work

On 07:13 pm - Jan 15 2017, Samuel Pitoiset wrote: > > > On 01/14/2017 02:35 AM, Ilia Mirkin wrote: > > The NVEA 3D class is numerically larger than the NVF0 3D class. The TK1 > > chip uses the SM35 ISA and likely has the same hw counters. Allow these > > to be used like on all the other

Re: [Mesa-dev] [PATCH] nv50/ir: optimize sub(a, 0) to a

Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> On 12:36 am - Oct 06 2016, Karol Herbst wrote: > helped some ue4 demos and divinity OS shaders > > total instructions in shared programs : 2818674 -> 2818606 (-0.00%) > total gprs used in shared programs: 379273 ->

[Mesa-dev] Where to place the SPIR-V headers

Hello everyone, I have been working on translating SPIR-V to NV50 IR inside Nouveau in order to run OpenCL kernels, received as SPIR-V binaries, on Nouveau. I have some patches for clover as well as gallium, but before sending those for review, I would like to know how to handle the SPIR-V header

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit integer MAD/MUL operations

6 03:24 PM, Pierre Moreau wrote: > > Hardware does not support 64-bit integers MAD and MUL operations, so we need > > to transform them in 32-bit operations. > > > > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> > > --- > &g

Re: [Mesa-dev] [PATCH v4] clover: restore support for LLVM <= 3.9

Mesa master builds again against LLVM 3.6. Tested-by: Pierre Moreau <pierre.mor...@free.fr> On 07:57 pm - Nov 18 2016, Vedran Miletić wrote: > The commit 8e430ff8b060b4e8e922bae24b3c57837da6ea77 support for LLVM > 3.9 and older versionsin Clover. This patch restores it a

[Mesa-dev] [PATCH v3] nv50/ir: Split 64-bit integer MAD/MUL operations

Hardware does not support 64-bit integers MAD and MUL operations, so we need to transform them in 32-bit operations. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 116 + 1 file changed, 116 insertions(+)

Re: [Mesa-dev] [PATCH] nvc0: do not duplicate similar performance metrics

Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> On 02:54 pm - Oct 31 2016, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> > --- > .../drivers/nouveau/nvc0/nvc0_query_hw_metric.c| 50 > +++--- > 1 file c

Re: [Mesa-dev] [PATCH] gm107/ir: emit RED instead of ATOM when no dst

Are reduction doable on shared atomics as well? Pierre On 08:08 pm - Nov 04 2016, Samuel Pitoiset wrote: > This is similar to NVC0 and GK110 emitters where we emit > reduction operations instead of atomic operations when the > destination is not used. > > Found after writing some tests which

[Mesa-dev] [PATCH] nv50/ir: Split 64-bit integer MAD/MUL operations

Hardware does not support 64-bit integers MAD and MUL operations, so we need to transform them in 32-bit operations. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 121 + 1 file changed, 121 insertions(+)

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit integer MAD/MUL operations

Sorry, there should have been a v2 next to PATCH in the subject… Pierre On 12:24 am - Oct 16 2016, Pierre Moreau wrote: > Hardware does not support 64-bit integers MAD and MUL operations, so we need > to transform them in 32-bit operations. > > Signed-off-by: Pierre Moreau

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit integer MAD/MUL operations

On 06:38 pm - Oct 15 2016, Ilia Mirkin wrote: > On Sat, Oct 15, 2016 at 6:24 PM, Pierre Moreau <pierre.mor...@free.fr> wrote: > > Hardware does not support 64-bit integers MAD and MUL operations, so we need > > to transform them in 32-bit operations. > > >

[Mesa-dev] [PATCH] clover: Check for executables before enqueueing a kernel

Without this check, the kernel::bind() method would fail with a std::out_of_range exception, letting an exception escape from the library into the client, rather than returning the corresponding error code CL_INVALID_PROGRAM_EXECUTABLE. Signed-off-by: Pierre Moreau <pierre.mor...@free

[Mesa-dev] Leaked hardware event if kernel launch fails?

Hello, I noticed that, if trying to enqueue a kernel which had no `module::section::text_executable` attached to its clover module, I would get a `std::out_of_range` exception, instead of the expected CL_INVALID_PROGRAM_EXECUTABLE (see [0]; I tried enqueueing using `clEnqueueNDRangeKernel). I

Re: [Mesa-dev] Leaked hardware event if kernel launch fails?

Hello Francisco! Thank you for your quick reply! On 02:33 pm - Dec 25 2016, Francisco Jerez wrote: > Pierre Moreau <pierre.mor...@free.fr> writes: > > > Hello, > > > Hi Pierre! > > > I noticed that, if trying to enqueue a kernel which had no > > `

Re: [Mesa-dev] [PATCH] nv50/ir: Change chipset constants to ISA constants.

I would agree with Ilia on making it an enum (maybe even an enum class?), rather than a define. If keeping it as a define, maybe we should also change the value while at it, and have NVISA_SM30 equal 0x1d or 0x30 (or by numbering from 0 and on), rather than keeping it linked to a chipset. Pierre

Re: [Mesa-dev] [PATCH 4/5] clover/llvm: Use -cl-std and device version to select language defaults

Hi Aaron, On 2017-07-21 — 23:19, Aaron Watry wrote: > According to section 5.8.4.5 of the 2.0 spec, the CL C version is chosen by: > 1) If you have -cl-std=CL1.1+ use the version specified > 2) If not, use the highest 1.x version that the device supports According to that same part of the

Re: [Mesa-dev] A few clover fixes for both CTS and eventual 1.2 support

With the comments in patch 4 taken care of, this series is Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> On 2017-07-21 — 23:19, Aaron Watry wrote: > The first patch is one I've been sitting on for a few weeks while > I've tried to chase down other issues with clover/llvm/libclc

[Mesa-dev] [RFC PATCH 01/17] auxiliary: Introduce utilities for SPIR-V binaries

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/auxiliary/Makefile.am | 1 + src/gallium/auxiliary/Makefile.sources| 4 ++ src/gallium/auxiliary/spirv/spirv_utils.c | 75 +++ src/gallium/auxiliary/spirv/spirv_utils.

[Mesa-dev] [RFC PATCH 05/17] include/CL: Add clCreateProgramWithIL from OpenCL 2.1

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- include/CL/cl.h | 6 ++ include/CL/cl_platform.h | 1 + 2 files changed, 7 insertions(+) diff --git a/include/CL/cl.h b/include/CL/cl.h index 316565d6e4..44d7aedc3e 100644 --- a/include/CL/cl.h +++ b/include/CL/cl.h @@

[Mesa-dev] [RFC PATCH 02/17] auxiliary: Implement a linker for SPIR-V binaries

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/auxiliary/Makefile.sources |4 +- src/gallium/auxiliary/spirv/spirv_linker.c | 1324 src/gallium/auxiliary/spirv/spirv_linker.h | 67 ++ 3 files changed, 1394 insertions(+), 1 de

[Mesa-dev] [RFC PATCH 07/17] configure.ac: Check for SPIRV-Tools header and library

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- configure.ac | 16 1 file changed, 16 insertions(+) diff --git a/configure.ac b/configure.ac index ba042791ad..602aeb279d 100644 --- a/configure.ac +++ b/configure.ac @@ -2064,6 +2064,11 @@ AC_ARG_WITH([clang-

[Mesa-dev] [RFC PATCH 06/17] include/CL: Add new option to clGetProgramInfo from OpenCL 2.1

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- include/CL/cl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/CL/cl.h b/include/CL/cl.h index 44d7aedc3e..cc8d7ddf60 100644 --- a/include/CL/cl.h +++ b/include/CL/cl.h @@ -455,6 +455,7 @@ typedef struct _cl_buffer_

[Mesa-dev] [RFC PATCH 00/17] Introducing SPIR-V support to clover

, as I am not that comfortable at writing too much C code: I’ll try to learn from your comments. Thank you in advance for reviewing/commenting, Pierre [1]: https://github.com/KhronosGroup/SPIRV-Tools/ Pierre Moreau (17): auxiliary: Introduce utilities for SPIR-V binaries auxiliary: Implement

[Mesa-dev] [RFC PATCH 03/17] include/pipe: Define SPIRV as an IR

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/include/pipe/p_defines.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/include/pipe/p_defines.h b/src/gallium/include/pipe/p_defines.h index ce2cfd1d88..71991383c2 100644 --- a/src/gallium/includ

[Mesa-dev] [RFC PATCH 04/17] include/pipe: Store the byte-size of a SPIR-V binary

Besides parsing all the opcodes until reaching the EOF character, there is no way to compute the size of a SPIR-V binary. Therefore, it is easier to pass it along the SPIR-V binary in pipe_compute_state. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/include/pipe/p_s

[Mesa-dev] [PATCH] nv50/ir: Report wrong prog types using proper var

e") Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp index a000bcbd32..21

Re: [Mesa-dev] [RFC PATCH 02/17] auxiliary: Implement a linker for SPIR-V binaries

, and remove from the import table all builtins, right before generating the linking table. Other comments are welcomed (on this patch, and on the others as well). :-) Pierre On 11:56 pm - May 03 2017, Pierre Moreau wrote: > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> > --- &g

[Mesa-dev] [PATCH] nv50/ir: Properly fold constants in SPLIT operation

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/c

Re: [Mesa-dev] [PATCH] nv50/ir: Properly fold constants in SPLIT operation

tic code and add > a Fixes: tag? > > Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu> > Cc: mesa-sta...@lists.freedesktop.org > > On Mon, Jun 12, 2017 at 4:53 PM, Pierre Moreau <pierre.mor...@free.fr> wrote: > > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr>

Re: [Mesa-dev] [PATCH 1/2] nv50/ir: move POW lowering into BuildUtil

Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> On 09:28 pm - Jun 22 2017, Karol Herbst wrote: > It's the same for all supported chipsets. > > Signed-off-by: Karol Herbst <karolher...@gmail.com> > --- > .../drivers/nouveau/codegen/nv5

Re: [Mesa-dev] [RFC PATCH 00/17] Introducing SPIR-V support to clover

them in this series, or should I leave them be for later? (Point b), if deemed useful, should be part of this series as it would rewrite a decent chunk of the code.) If you have any other comments, feel free to share it. :-) Best regards, Pierre On 11:56 pm - May 03 2017, Pierre Moreau wrote

Re: [Mesa-dev] [RFC PATCH 00/17] Introducing SPIR-V support to clover

> hopefully this[1] will eventually happen, which would make this less > of an issue :-) > > [1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112538.html Indeed! I have seen that thread and made sure to subscribe to the ML not to miss anything there.

Re: [Mesa-dev] [RFC PATCH 04/17] include/pipe: Store the byte-size of a SPIR-V binary

This seems like a good idea. I changed the code locally to use `pipe_llvm_program_header` instead; it does not seem worth it to create a `pipe_spirv_program_header`, since it would only contain a `num_bytes` attributes for now. signature.asc Description: PGP signature

[Mesa-dev] [PATCH 2/4] nv50/ir: Free target if we failed to create a program

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp index 1f64

[Mesa-dev] [PATCH 4/4] nv50/ir: Replace NV50_PROGRAM_IR_* by PIPE_SHADER_IR_*

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 7 +-- src/gallium/drivers/nouveau/nouveau_compiler.c | 2 +- src/gallium/drivers/nouveau/nv50/nv50_pro

[Mesa-dev] [PATCH 1/4] nv50/ir: Fail if encountering unknown shader type

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp index b67a

[Mesa-dev] [PATCH 3/4] nv50/ir: Remove unused translation methods

This code was merged commented out, and has stayed that way ever since. Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/codegen/nv50_ir.cpp | 12 +++- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 - 2 files changed, 3 insertions(

[Mesa-dev] [RFC PATCH 11/17] clover/spirv: Add functions for parsing arguments, linking programs, etc.

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/state_trackers/clover/Makefile.am | 10 +- src/gallium/state_trackers/clover/Makefile.sources | 4 + .../state_trackers/clover/spirv/invocation.cpp | 481 + .../state_trackers/clover

[Mesa-dev] [RFC PATCH 10/17] clover/spirv: Import spirv.hpp11 version 1.0 (rev 10)

Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- .../state_trackers/clover/spirv/spirv.hpp11| 952 + 1 file changed, 952 insertions(+) create mode 100644 src/gallium/state_trackers/clover/spirv/spirv.hpp11 diff --git a/src/gallium/state_trackers/clover

  1   2   3   4   >