[Mesa-dev] [PATCH 11/16] i965/blorp: Do more fine grained flushing/syncing

for texture uploads which require excess flushing to be omitted in order to perform properly. Now that clears and blits make the decision independently that also becomes easier. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c

[Mesa-dev] [PATCH 09/16] i965/miptree: Add color resolve end-of-pipe-sync before sharing

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 7

[Mesa-dev] [PATCH 08/16] i965/dri2: Add end-of-pipe-sync after color resolves

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index bb84102..75d4920

[Mesa-dev] [PATCH 14/16] i965: Consider surface resolves and sync after blorp ops

ble on gen < 6. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_compute.c | 2 ++ src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_draw.c | 2

[Mesa-dev] [PATCH 13/16] i965/blorp: Use conditional end-of-pipe-sync

instead of unconditional render cache flush. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 23 --- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/sr

[Mesa-dev] [PATCH 10/16] i965: Add end-of-pipe sync before non-gpu read of color resolves

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 src/mesa/drivers/dri/i965/intel_tex_image.c| 10 -- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 11 +-- 3 files changed, 21 insertions

[Mesa-dev] [PATCH 06/16] i965: Consider layered rt resolves along with other

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.c | 15 +++ src/mesa/drivers/dri/i965/brw_draw.c| 34 - 2 files changed, 15 insertions(+), 34 deletions(-) diff --git a/src/mesa/drivers/dr

[Mesa-dev] [PATCH 07/16] i965: Add color resolve end-of-pipe-sync before switch to blit ring

This ensures that all rendering is finished and gpu caches are flushed out. These are paths trying to switch to blit engine. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_blit.c | 16 src/mesa/drivers/dr

[Mesa-dev] [PATCH 05/16] i965: Hook end-of-pipe-sync after framebuffer resolves

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.c | 101 1 file changed, 51 insertions(+), 50 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c

[Mesa-dev] i965: On-demand render target flushing

to be rather careful with it - performance gets decreased noticeably when used unneeded. I don't really know if we want to go this way myself even. Current logic - while not ideal - is rather simple. Topi Pohjolainen (16): i965/miptree: Tell if anything got resolved i965/gen6+: Implement end-of-pipe

[Mesa-dev] [PATCH 01/16] i965/miptree: Tell if anything got resolved

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 ++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 03/16] i965: Hook end-of-pipe-sync after texture resolves

without the driver necessarily knowing. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.c | 113 1 file changed, 99 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c

[Mesa-dev] [PATCH 02/16] i965/gen6+: Implement end-of-pipe sync

Implementation for gen < 6 is taken as copy-paste from brw_emit_mi_flush() in order to preserve the behavior in later patches. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_pipe_contr

[Mesa-dev] [PATCH 04/16] i965: Hook end-of-pipe-sync after image resolves

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.c | 80 +++-- 1 file changed, 47 insertions(+), 33 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c

[Mesa-dev] [v2 4/9] i965: Estimate batch space per shader stage

with blorp tex uploads (HSW with piglit test max-samplers). One runs out of space while batch wrapping isn't allowed. v2: Rebase on top of current upstream Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> CC: Kenneth Graunke <kenn...@whitecape.org> CC: Jason Ekstrand <ja...

[Mesa-dev] [v2 6/9] i965: Add support for tex upload using gpu

, it is handled by _mesa_image_offset() automatically (Ken). - Support 1D_ARRAY by flipping depth, width and y, z (Ken). CC: Kenneth Graunke <kenn...@whitecape.org> CC: Anuj Phogat <anuj.pho...@gmail.com> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mes

[Mesa-dev] [PATCH] i965/blorp: Add also depth buffer to render cache

CC: Francisco Jerez <curroje...@riseup.net> CC: Kenneth Graunke <kenn...@whitecape.org> CC: Jason Ekstrand <ja...@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 3 +++ 1 file changed, 3 inserti

[Mesa-dev] [v2 1/4] i965/blorp: Use the render cache mechanism instead of explicit flushing

LIDATE | PIPE_CONTROL_CS_STALL; } brw_emit_pipe_control_flush(brw, flags); v2 (Jason): Check that destination exists before trying to add to render cache. Depth clears and resolves don't have it. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/driv

[Mesa-dev] [v2 2/4] i965: Make depth clear flushing more explicit

the stalls and flushes mandated by the spec and gets rid of those hangs. v2 (Jason, Ken): Document the rational for separating depth cache flush and stall on Gen7. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_cle

[Mesa-dev] i965/blorp: Rework flushes to better match the spec

that the current unconditional flushing is hiding the need for these. CC: Kenneth Graunke <kenn...@whitecape.org> CC: Jason Ekstrand <ja...@jlekstrand.net> CC: Mark Janes <mark.a.ja...@intel.com> Topi Pohjolainen (4): i965/blorp: Do pre-draw flush with two pipe-control writes

[Mesa-dev] [PATCH 2/4] i965: Make depth clear flushing more explicit

the stalls and flushes mandated by the spec and gets rid of those hangs. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_clear.c| 38 ++-- src/mesa/drivers/dri/i965/gen8_depth_state.c | 16 2 files changed, 46

[Mesa-dev] [PATCH 1/4] i965/blorp: Do pre-draw flush with two pipe-control writes

LIDATE | PIPE_CONTROL_CS_STALL; } brw_emit_pipe_control_flush(brw, flags); Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/genX_blo

[Mesa-dev] [PATCH 3/4] i965/gen6: Issue direct depth stall and flush after depth clear

); brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE); Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_clear.c | 7 ++-

[Mesa-dev] [PATCH 4/4] i965/blorp: Make post draw flush more explicit

ache flush with command stream stall should be sufficient. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 22 ++ src/mesa/drivers/dri/i965/genX_blorp_exec.c | 5 - 2 files changed, 22 insertions(+), 5 de

[Mesa-dev] [1.5/27] i965/miptree: Tell when brw_miptree_layout() fails

In addition, let intel_miptree_create_layout() release the miptree - it is the allocator. CC: Jason Ekstrand <ja...@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_tex_layout.c| 10 +- src/mesa/driv

[Mesa-dev] [PATCH 25/27] i965/miptree/gen7+: Use ISL for HIZ layouts

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c| 6 +- src/mesa/drivers/dri/i965/brw_misc_state.c | 4 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 +- src/mesa/drivers/dri/i965/gen6_depth_state.c

[Mesa-dev] [PATCH 21/27] intel/isl/gen7: Add CCS alignment restrictions

Gen8 and Gen9 are already more heavily constrained as one applies arrayed/mipmapped alignment even for non-arrayed and non-mipmapped. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/isl/isl_gen7.c | 39 +++ 1 file chang

[Mesa-dev] [PATCH 27/27] i965: Use stored hiz surface instead of creating copy

Now the last user of intel_miptree_get_aux_isl_surf() is gone. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 77 src/mesa/drivers/dr

[Mesa-dev] [PATCH 15/27] i965/gen6: Drop miptrees in depth/stencil offset resolvers

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 8 src/mesa/drivers/dri/i965/brw_tex_layout.c| 19 +-- src/mesa/drivers/dri/i965/gen6_depth_state.c | 4 ++-- src/mesa/drivers/dr

[Mesa-dev] [PATCH 10/27] i965/blorp/gen6: Drop unnecessary stencil/hiz surf dimension adjust

Hardware state setup only needs offset and pitch and ignores the rest. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 57 --- 1 file changed, 20 insertions(+), 37 deletions(-) diff --git a/src/mesa/d

[Mesa-dev] [PATCH 22/27] intel/isl: Apply render target alignment constraints for MCS

plied on Gen9 for consistency sake. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/isl/isl_gen7.c | 16 src/intel/isl/isl_gen8.c | 16 src/intel/isl/isl_gen9.c | 16 3 files changed, 48 insertions(+) diff --git a/src/int

[Mesa-dev] [PATCH 09/27] i965/gen6: Remove dead code in hiz surface setup

In intel_hiz_miptree_buf_create() the miptree is unconditionally created with MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/gen6_depth_state.c | 13 ++--- 1 file changed, 6 insertions(+), 7 del

[Mesa-dev] [PATCH 14/27] i965/blorp/gen6: Use on-demand stencil/hiz offset resolvers

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 21 - 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 2001cf3..6

[Mesa-dev] [PATCH 07/27] i965/gen6: Simplify hiz surface setup

In intel_hiz_miptree_buf_create() intel_miptree_aux_buffer::bo is unconditionally initialised to point to the same buffer object as hiz_mt does. The same goes for intel_miptree_aux_buffer::pitch/qpitch. This will make following patches simpler to read. Signed-off-by: Topi Pohjolainen

[Mesa-dev] [PATCH 26/27] i965/blorp: Use hiz surface instead of creating copy

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 25 - src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 ++ 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dr

[Mesa-dev] [PATCH 20/27] i965/miptree: Refactor ISL aux usage resolver

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c| 4 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 47 +++- src/mesa/drivers/dr

[Mesa-dev] [PATCH 24/27] i965/miptree: Drop MIPTREE_LAYOUT_ACCELERATED_UPLOAD in mcs init

because buffers get unconditionally initialised by cpu writing. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_

[Mesa-dev] [PATCH 23/27] i965/miptree: Use ISL for MCS layouts

This changes the size of the auxiliary buffer on gen7 and gen8 for arrayed surfaces. Current i965 logic uses qpitch height per slice whereas ISL knows that msaa is never mipmapped and more compact layout is sufficient. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- sr

[Mesa-dev] [PATCH 18/27] i965/gen6: Allocate hiz directly without miptree

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 13 +--- src/mesa/drivers/dri/i965/gen6_depth_state.c | 8 - src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 43 +-- src/mesa/drivers/dr

[Mesa-dev] [PATCH 17/27] i965/gen6/hiz: Add direct buffer size resolver

The apparent hack adding unconditionally two lines into cube maps is taken directly from align_cube(). Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_tex_layout.c| 39 +++ src/mesa/drivers/dri/i965/intel_mipmap_

[Mesa-dev] [PATCH 16/27] i965/blorp/gen6: Set aux pitch directly

dropping dependency to intel_miptree_get_aux_isl_surf(). Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/sr

[Mesa-dev] [PATCH 19/27] i965/miptree: Refactor aux surface allocation

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 67 --- 1 file changed, 41 insertions(+), 26 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dr

[Mesa-dev] [PATCH 06/27] i965/blorp/gen6: Simplify hiz surface setup

-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 8d58616..9c4b8fa 100644 --- a/src/mesa/d

[Mesa-dev] [PATCH 12/27] i965/gen6: Calculate stencil offset on demand

This is kept on purpose in i965. It can be moved to ISL if it is needed in vulkan. Pointers to miptrees are given solely for verification purposes. These will be dropped in following patches. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dr

[Mesa-dev] [PATCH 08/27] i965/blorp/gen6: Remove dead code in hiz setup

Such as comment states for intel_miptree_hiz_buffer::mt, hiz_mt only exists for gen6. In addition, intel_hiz_miptree_buf_create() uses MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD unconditionally. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_b

[Mesa-dev] [PATCH 04/27] i965/gen6: Remove check for stencil format

There are is no alternative. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/gen6_depth_state.c | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa/d

[Mesa-dev] i965: Use ISL for auxiliary buffer layout

something of that sort. Patch 23 starts using ISL for MCS and the rest for HIZ. I tried to make individual steps as small as possible adding temporary asserts checking that newly added calculations matched the current. Topi Pohjolainen (27): i965/meta: Remove unused brw_get_rb_for_slice() i9

[Mesa-dev] [PATCH 02/27] i965/miptree: Remove redundant check for null texture

There exact same check earlier in brw_miptree_layout() which intel_miptree_create_layout() in turn calls unconditionally. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 +-- 1 file changed, 1 insertion(+), 6 del

[Mesa-dev] [PATCH 03/27] i965: Remove check for hiz on earlier gens than SNB

Only caller, brw_workaround_depthstencil_alignment(), returns early for gen6+. While at it, reduce scope for brw_get_depthstencil_tile_masks() as well. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h| 6 -- src/mesa/drive

[Mesa-dev] [PATCH 01/27] i965/meta: Remove unused brw_get_rb_for_slice()

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_meta_util.c | 44 --- src/mesa/drivers/dri/i965/brw_meta_util.h | 5 2 files changed, 49 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c

[Mesa-dev] [PATCH 13/27] i965/gen6: Calculate hiz offset on demand

This is kept on purpose in i965. It can be moved to ISL if it is needed in vulkan. Pointers to miptrees are given solely for verification purposes. These will be dropped in following patches. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dr

[Mesa-dev] [PATCH 11/27] i965/hiz/gen6: Stop setting false qpitch

which is not applicable for "all slices at each lod". Current logic makes one to believe it has some purpose. When miptree layout is calculated brw_miptree_layout_texture_array() sets the qpitch unconditionally but later on ignores it altogether for ALL_SLICES_AT_EACH_LOD. Signed-of

[Mesa-dev] [PATCH 05/27] i965: Replace open coded with intel_miptree_get_image_offset()

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_pixel_read.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c

[Mesa-dev] i965/gen6+: Yet another blorp path - tex_(sub)image2d

ast there aren't any jenkins regressions. Topi Pohjolainen (9): i965: Refactor surface resolves prior to draw call i965: Consider surface resolves just before draw intel/blorp/dbg: Name blit shaders for easy recognition in dumps i965: Estimate batch space per shader stage meta: Refactor text

[Mesa-dev] [PATCH 6/9] i965: Add support for tex upload using gpu

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_tex.h | 8 + src/mesa/drivers/dri/i965/intel_tex_subimage.c | 194 + 2 files changed, 202 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex.h

[Mesa-dev] [PATCH 2/9] i965: Consider surface resolves just before draw

but only the internal driver state. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> CC: Kenneth Graunke <kenn...@whitecape.org> CC: Jason Ekstrand <ja...@jlekstrand.net> CC: Ben Widawsky <b...@bwidawsk.net> --- src/mesa/drivers/dri/i965/brw_compute.c | 1 + s

[Mesa-dev] [PATCH 4/9] i965: Estimate batch space per shader stage

with blorp tex uploads (HSW with piglit test max-samplers). One runs out of space while batch wrapping isn't allowed. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> CC: Kenneth Graunke <kenn...@whitecape.org> CC: Jason Ekstrand <ja...@jlekstrand.net> --- src/mes

[Mesa-dev] [PATCH 9/9] i965: Drop _mesa_meta_pbo_TexSubImage() even for gen < 6

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_tex_image.c| 24 +++- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 19 +-- 2 files changed, 12 insertions(+), 31 deletions(-) diff --git a/src/mesa/d

[Mesa-dev] [PATCH 5/9] meta: Refactor texture format translation

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/common/meta_tex_subimage.c | 9 +++-- src/mesa/main/glformats.c | 15 +++ src/mesa/main/glformats.h | 4 3 files changed, 22 insertions(+), 6 del

[Mesa-dev] [PATCH 3/9] intel/blorp/dbg: Name blit shaders for easy recognition in dumps

Blorp clears already have an equivalent. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/blorp/blorp_blit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index 8abe3a8..9dcd33f 100644 --- a/src

[Mesa-dev] [PATCH 7/9] i965/gen6+: Use blorp for tex_image_2d

to _mesa_store_teximage() as well. This, however, leads to performance regressions in few benchmarks, especially with Synmark OglDrvRes. Therefore intel_texsubimage_gpu_copy is only used to replace the meta path for now. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drive

[Mesa-dev] [PATCH 8/9] i965/gen6+: Use for tex_subimage_2d

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_tex_subimage.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index f999a93..7

[Mesa-dev] [PATCH 1/9] i965: Refactor surface resolves prior to draw call

and move it to brw_draw.c where it will be eventually used. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.c | 174 +-- src/mesa/drivers/dri/i965/brw_draw.c| 178 sr

[Mesa-dev] [PATCH] i965: Release aux buffer when disabling ccs

Otherwise subsequent render cycles keep on using compression and/or fast clear. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> CC: Kalyan Kondapally <kalyan.kondapa...@intel.com> CC: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/intel

[Mesa-dev] [v3 08/17] i965: Add plumbing for fast clear layer/level details

on when the actual functionality is enabled. v2: Rebased on top current master setting the state in blorp_surf_for_miptree(). v3: Replace open-coded resolved check in surface state emission with intel_miptree_has_color_unresolved(). Signed-off-by: Topi Pohjolainen <topi.pohjo

[Mesa-dev] [v3 11/17] i965: Track fast color clear state in level/layer granularity

unnecessary intel_miptree_set_fast_clear_state() call in brw_blorp_resolve_color() preventing intel_miptree_set_fast_clear_state() from asserting against RESOLVED. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Jason Ek

[Mesa-dev] [v3 14/17] i965: Use ISL for CCS layouts

One can now also delete intel_get_non_msrt_mcs_alignment(). v2 (Jason): Do not leak aux buf but allocate only after getting ISL surfaces. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [v3 04/17] i965: Provide slice details to color resolver

v2: Make intel_miptree_resolve_color() take start layer and layer count. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 13 ++- src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++- src/mesa/drivers/dr

[Mesa-dev] [v2 04/17] i965: Provide slice details to color resolver

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 15 +-- src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++- src/mesa/drivers/dri/i965/brw_context.c | 14 +- src/mesa/drivers/dri/i965/intel_

[Mesa-dev] [v2 13/17] i965: Resolve non-compressed fast clears prior layered rendering

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/brw_draw.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/driv

[Mesa-dev] [v2 12/17] i965: Restrict fast color clear on first slice only

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/brw_blorp.c | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965

[Mesa-dev] [v2 09/17] i965: Refactor check if color resolve is needed

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 43 +-- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/src/mesa/driv

[Mesa-dev] [v2 07/17] i965: Add interface for checking multiple slices if any is unresolved

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 + 2 files changed, 13 insertions(+) diff --git a/src/

[Mesa-dev] [v2 17/17] i965: Enable fast clears for multi-lod

ON BDW: Manhattan 3.0: 1.37079% +/- 0.571208% Manhattan 3.0 off: 1.74029% +/- 0.267499% v2 (Ben, Matt): Fix rebase error by removing the perf warning v3 (Topi): Rebased on top of revised eligibility logic Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Ja

[Mesa-dev] [v2 15/17] i965/gen8: Relax asserts prohibiting arrayed/mipmapped fast clears

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 4 ++-- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 +-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++- 3 files changed, 17 insertions(

[Mesa-dev] [v2 16/17] i965: Allow single-sampled miptree to be resolved and shared

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 1c8ce0d..d

[Mesa-dev] [v2 14/17] i965: Use ISL for CCS layouts

One can now also delete intel_get_non_msrt_mcs_alignment(). Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 138 +++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 - 2 files changed, 38 inse

[Mesa-dev] [v2 02/17] i965/blorp: Skip redundant re-fast clear for non-compressed

Originally re-clears where skipped but when lossless compression was introduced the re-clears where errorneously enabled also for non-compressed fast clears. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> CC: Ben Widawsky <benjamin.widaw...@intel.com> CC: Kenneth G

[Mesa-dev] [v2 06/17] i965: Provide slice details to renderbuffer fast clear state tracker

This patch also introduces getter and setter for fast clear state preparing for tracking the state per slice. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 3 +- src/mesa/drivers/dri/i965/brw_draw.c | 10 +++--

[Mesa-dev] [v2 08/17] i965: Add plumbing for fast clear layer/level details

on when the actual functionality is enabled. v2: Rebased on top current master setting the state in blorp_surf_for_miptree(). Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> (v1) --- src/mesa/drivers/dri/i965

[Mesa-dev] [v2 11/17] i965: Track fast color clear state in level/layer granularity

v2: Added intel_resolve_map_clear() into intel_miptree_release() Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> (v1) --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 64 +++ src/mesa/driv

[Mesa-dev] [v2 10/17] i965: Move fast clear state enumeration into resolve map

Status is still tracked per miptree. Next patch will switch to resolve map per slice/level. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 58

[Mesa-dev] [v2 01/17] i965: Refactor lossless compression state tracking

setting the state in blorp_surf_for_miptree(). Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> (v1) --- src/mesa/drivers/dri/i965/brw_blorp.c| 8 ++-- src/mesa/drivers/dri/i965/brw_draw.c |

[Mesa-dev] [v2 05/17] i965: Split per miptree and per slice/level fast clear bits

own boolean. Possible follow-up work is to combine disable_aux_buffers and no_ccs into single enum. v2 (Jason): Changed no_msrt_mcs to no_ccs and updated comment Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 2 +- src/mesa/d

[Mesa-dev] [v2 03/17] i965: Add new interface for full color resolves

Upcoming patches will introduce fast clear in level/layer granularity like the driver does already for depth/hiz. This patch introduces equivalent full resolve option. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.c| 6 +++--

[Mesa-dev] [v2] i965: Fast color clear for mipmapped and arrayed

This is a rebase on top recent changes by Jason and Lionel. While things have changed quite a bit in some of the patches they have mostly become clearer. Ben Widawsky (1): i965: Enable fast clears for multi-lod Topi Pohjolainen (16): i965: Refactor lossless compression state tracking i965

[Mesa-dev] [PATCH 2/2] intel/blorp: Fix rectangle size for level-not-zero resolves

Needed to prevent gpu hangs when mip-mapped compression gets enabled. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> CC: Jason Ekstrand <ja...@jlekstrand.net> --- src/intel/blorp/blorp_clear.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 1/2] i965/miptree: Don't shrink textures when augmenting for more levels

l, and therefore such is created. Generation for level one in turn finds right base level size but only one level when two is needed. And the same goes on for all eight levels. This patch prevents the shrink maintaining the NPOT size of 293x277. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@i

[Mesa-dev] [v2 22.1/26] i965: Apply non-msrt mcs array/mipmap horizontal alignment rules

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> CC: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 35 --- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_m

[Mesa-dev] [v2 22/26] i965: Apply non-msrt mcs array/mipmap vertical alignment rules

and the latter for qpitch. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> CC: Jason Ekstrand <ja...@jlekstrand.net> --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 68 +++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- src/mesa/driv

[Mesa-dev] [v3 26/26] i965: Enable fast clears for multi-lod

ON BDW: Manhattan 3.0: 1.37079% +/- 0.571208% Manhattan 3.0 off: 1.74029% +/- 0.267499% v2 (Ben, Matt): Fix rebase error by removing the perf warning v3 (Topi): Rebased on top of revised eligibility logic Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> Reviewed-by: Ja

[Mesa-dev] [v2 23/26] i965: Restructure fast clear eligibility decision

From: Ben Widawsky <b...@bwidawsk.net> v2 (Jason): - Use PRM citation for SKL now that it is available - Also return false for gen < 8 mipmapped/arrayed Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mip

[Mesa-dev] [v2 26/26] i965: Enable fast clears for multi-lod

From: Ben Widawsky On SKL (also fast clear is used for level 0, layer 0): Manhattan 3.0: 3.88434% +/- 0.814659% Manhattan 3.0 off: 3.25542% +/- 0.101149% Trex: 3.43501% +/- 0.31223% Trex off: 4.13781% +/- 0.0993569% ON BDW:

[Mesa-dev] [v2 19/26] i965: Restrict fast color clear on first slice only

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 526c8ec..452efef 100644 --- a/src/mesa/d

[Mesa-dev] [PATCH 12/26] i965: Add plumbing for fast clear layer/level details

on when the actual functionality is enabled. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_blorp.c| 32 +- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 34 2 files changed, 42 inse

[Mesa-dev] [PATCH 24/26] i965: Disable aux buffers with non-compatible copies

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/blorp/blorp.h | 2 ++ src/intel/blorp/blorp_blit.c | 6 ++ src/mesa/drivers/dri/i965/brw_blorp.c | 25 - 3 files changed, 28 insertions(+), 5 deletions(-) diff

[Mesa-dev] [PATCH 22/26] i965: Add non-msrt mcs array/mipmap alignment restrictions

and the latter for qpitch. Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 68 +++- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 25/26] i965/gen8: Relax asserts prohibiting arrayed/mipmapped fast clears

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/intel/isl/isl.c | 3 +-- src/mesa/drivers/dri/i965/brw_blorp.c | 6 +++--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 +-- src/mesa/drivers/dr

[Mesa-dev] [PATCH 11/26] i965: Add interface for checking multiple slices if any is unresolved

Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 + 2 files changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/d

[Mesa-dev] [PATCH 23/26] i965: Restructure fast clear eligibility decision

From: Ben Widawsky Signed-off-by: Ben Widawsky --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 51 ++- 1 file changed, 34 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

<    1   2   3   4   5   6   7   8   9   10   >