Ping. I see that a v4 has been sent out without these comments being addressed.
-Nanley
On Tue, Dec 7, 2021 at 6:51 PM Nanley Chery wrote:
>
> Hi Ramalingam,
>
> On Wed, Oct 27, 2021 at 5:22 PM Ramalingam C wrote:
> >
> > From: Matt Roper
> >
> > DG2
Hi Ramalingam,
On Wed, Oct 27, 2021 at 5:22 PM Ramalingam C wrote:
>
> From: Matt Roper
>
> DG2 unifies render compression and media compression into a single
> format for the first time. The programming and buffer layout is
> supposed to match compression on older gen12 platforms, but the
>
On Sat, Jun 29, 2019 at 4:40 PM Eric Engestrom wrote:
>
> On Saturday, 2019-06-29 22:59:21 +0200, apinheiro wrote:
> >
> > On 29/6/19 2:30, Rob Clark wrote:
> > > I had interpreted it as literally the "block the gitlab merge button"
> > > option, ie. "I want to get feedback but it is not ready to
Thanks for reaching out to the HW team. Given that the internal
documentation was updated to set the Project field of this restriction
to HSW:GT3, what do you think about shortening the comment to mention
that? I'd like to give this a RB as is, but there are a lot of truth
claims I'd have to
Thanks. Landed.
On Thu, May 30, 2019 at 7:02 AM Jason Ekstrand wrote:
>
> Feel free to land
>
> On Wed, May 29, 2019 at 4:50 PM Nanley Chery wrote:
>>
>> On Wed, Feb 14, 2018 at 12:19 PM Jason Ekstrand wrote:
>> >
>> > Cannonlake hardware ad
ing it manually. This was tested with a full Vulkan CTS
> run on Cannonlake.
> ---
> src/intel/blorp/blorp_clear.c | 12 +++-
> src/intel/blorp/blorp_genX_exec.h | 6 ++
> 2 files changed, 17 insertions(+), 1 deletion(-)
>
This patch is
Reviewed-by: Nanley Chery
On Thu, Apr 18, 2019 at 08:19:38AM -0700, Kenneth Graunke wrote:
> On Wednesday, April 17, 2019 1:31:28 PM PDT Nanley Chery wrote:
> > On Wed, Apr 17, 2019 at 11:34:15AM -0700, Rafael Antognolli wrote:
> > > On Wed, Apr 17, 2019 at 09:04:09AM -0700, Kenneth Graunke wrote:
&g
On Wed, Apr 17, 2019 at 11:34:15AM -0700, Rafael Antognolli wrote:
> On Wed, Apr 17, 2019 at 09:04:09AM -0700, Kenneth Graunke wrote:
> > On Wednesday, April 17, 2019 7:16:28 AM PDT Topi Pohjolainen wrote:
> > > From: Rafael Antognolli
> > >
> > > Fixes MCS fast clear gpu hangs with Vulkan CTS
On Tue, Mar 12, 2019 at 10:56:27PM -0500, Jason Ekstrand wrote:
> Cc: mesa-sta...@lists.freedesktop.org
> Cc: Nanley Chery
> ---
> src/intel/vulkan/anv_pass.c | 18 +-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/vulkan/a
On Mon, Feb 25, 2019 at 03:40:24PM -0800, Nanley Chery wrote:
> On Mon, Feb 25, 2019 at 03:14:10PM -0800, Dylan Baker wrote:
> > Quoting Eleni Maria Stea (2019-02-22 13:02:30)
> > > Calculating the scissor rectangle fields with the y flipped (0 on top)
> > > c
; >shouldn't have changed the ScissorRectangleYMax calculation. As the
> >fixed code is equivalent with using CLAMP instead of MAX2 at the top of
> >the function when bbox[2] and bbox[3] are calculated, and the 2nd is more
> >clear, I replaced it. (Nanley Cher
t with using CLAMP instead of MAX2 at the top of
>the function when bbox[2] and bbox[3] are calculated, and the 2nd is more
>clear, I replaced it. (Nanley Chery)
>
> v3:
>- Reversed the CLAMP change in bbox[3] as the API guarantees that the
>viewport height is positive. (Nanley Ch
bbox[2] and bbox[3] are calculated, and the 2nd is more
>clear, I replaced it. (Nanley Chery)
> ---
> src/mesa/drivers/dri/i965/genX_state_upload.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
>
On Mon, Dec 10, 2018 at 12:42:40PM +0200, Eleni Maria Stea wrote:
> Calculating the scissor rectangle fields with the y flipped (0 on top)
> can generate negative values that will cause assertion failure later on
> as the scissor fields are all unsigned. We must clamp the bbox values
> again to
s written with compressed data, we decompress them to RGB and update the
> shadow. Then we use the shadow for rendering.
>
> v2:
>- Fixes in the commit message (Nanley Chery)
>- Reversed the changes in brw_get_texture_swizzle and swapped the b, g
>values at the
s using two miptrees.
> i965: Fixed the CopyImageSubData for ETC2 on Gen < 8
> i965: Enabled the OES_copy_image extension on Gen 7 GPUs
> i965: Removed the field etc_format from the struct intel_mipmap_tree
>
These patches are
Reviewed-by: Nanley Chery
I like how thi
e we
> update the texture surface. (Nanley Chery)
>
> v3:
> - As we now update the tree before the rendering we don't need to copy
> the data during the unmap anymore. Removed the unnecessary update from
> the intel_miptree_unmap in intel_mipmap_tree.c (Nanley Chery)
> ---
>
s written with compressed data, we decompress them to RGB and update the
> shadow. Then we use the shadow for rendering.
>
> v2:
>- Fixes in the commit message (Nanley Chery)
>- Reversed the changes in brw_get_texture_swizzle and swapped the b, g
>values at the
s written with compressed data, we decompress them to RGB and update the
> shadow. Then we use the shadow for rendering.
>
> v2:
>- Fixes in the commit message (Nanley Chery)
>- Reversed the changes in brw_get_texture_swizzle and swapped the b, g
>values at the
s written with compressed data, we decompress them to RGB and update the
> shadow. Then we use the shadow for rendering.
>
> v2:
>- Fixes in the commit message (Nanley Chery)
>- Reversed the changes in brw_get_texture_swizzle and swapped the b, g
>values at the
s written with compressed data, we decompress them to RGB and update the
> shadow. Then we use the shadow for rendering.
>
> v2:
>- Fixes in the commit message (Nanley Chery)
>- Reversed the changes in brw_get_texture_swizzle and swapped the b, g
>values at the
On Fri, Feb 08, 2019 at 12:55:20PM +0200, Eleni Maria Stea wrote:
> Hi Nanley,
>
> On Thu, 7 Feb 2019 15:46:29 -0800
> Nanley Chery wrote:
> >
> > > @@ -3825,10 +3849,20 @@ intel_miptree_unmap(struct brw_context *brw,
> > > DBG("%s:
On Thu, Feb 07, 2019 at 07:17:32PM +0200, Eleni Maria Stea wrote:
> On Thu, 7 Feb 2019 11:18:59 -0500
> Ilia Mirkin wrote:
>
> > On Thu, Feb 7, 2019 at 2:49 AM Eleni Maria Stea
> > wrote:
> > >
> > > On Wed, 6 Feb 2019 1
s written with compressed data, we decompress them to RGB and update the
> shadow. Then we use the shadow for rendering.
>
> v2:
>- Fixes in the commit message (Nanley Chery)
>- Reversed the changes in brw_get_texture_swizzle and swapped the b, g
>values at the
On Sun, Feb 03, 2019 at 03:07:36PM +0200, Eleni Maria Stea wrote:
> OES_copy_image extension was disabled on Gen7 due to the lack of support
> for ETC2 images. Enabled it back. (Kenneth Graunke)
> ---
> src/mesa/drivers/dri/i965/intel_extensions.c | 18 ++
> 1 file changed, 14
On Sun, Feb 03, 2019 at 03:07:33PM +0200, Eleni Maria Stea wrote:
> The assertions that the GL_MAP_WRITE_BIT and GL_MAP_INVALIDATE_RANGE_BIT
> in intel_miptree_map_etc will fail when the ETC miptree is mapped for
> reading. As we are about to fix the GetCompressed* functions in the
> following
On Sun, Feb 03, 2019 at 03:59:42PM +0200, Eleni Maria Stea wrote:
> On Fri, 18 Jan 2019 17:09:03 -0800
> Nanley Chery wrote:
>
> > On Mon, Nov 19, 2018 at 10:54:08AM +0200, Eleni Maria Stea wrote:
> [...]
> > > + int img_d = smt->surf.logical_level0_px.depth;
s written with compressed data, we decompress them to RGB and update the
> shadow. Then we use the shadow for rendering.
>
> v2:
>- Fixes in the commit message (Nanley Chery)
>- Reversed the changes in brw_get_texture_swizzle and swapped the b, g
>values at the
gt; src/intel/isl/isl_surface_state.c | 2 ++
> 5 files changed, 28 insertions(+), 5 deletions(-)
>
This patch is
Reviewed-by: Nanley Chery
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index 392c15ca3fb..3ffc6f627b2 100644
> --- a/src/intel/isl/isl.c
> +++ b/src
On Wed, Jan 23, 2019 at 02:25:14PM -0800, Nanley Chery wrote:
> On Fri, Oct 12, 2018 at 01:46:37PM -0500, Jason Ekstrand wrote:
> > The Yf and Ys tilings change a bit between gen9 and gen10 so we have to
> > be able to distinguish between them.
> > ---
> > src/intel/i
On Fri, Oct 12, 2018 at 01:46:35PM -0500, Jason Ekstrand wrote:
> With Yf and Ys tiling, everything is actually four dimensional because
> we can have multiple depth or multisampled array slices in the same
> tile. This commit just enhances the calculations so they can handle it.
>
>
On Fri, Oct 12, 2018 at 01:46:34PM -0500, Jason Ekstrand wrote:
> Reviewed-by: Topi Pohjolainen
> ---
> src/intel/isl/isl.c | 36
> src/intel/isl/isl.h | 2 +-
> 2 files changed, 25 insertions(+), 13 deletions(-)
>
> diff --git a/src/intel/isl/isl.c
On Sat, Jan 26, 2019 at 05:22:06PM +0200, Eleni Maria Stea wrote:
> Hi Nanley,
>
> On Fri, 18 Jan 2019 15:32:02 -0800
> Nanley Chery wrote:
>
>
> > > diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> > > b/src/mesa/drivers/dri/i965/brw_wm_su
On Fri, Oct 12, 2018 at 01:46:32PM -0500, Jason Ekstrand wrote:
> Reviewed-by: Topi Pohjolainen
> ---
> src/intel/blorp/blorp_clear.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(-)
>
Patches 1 and 2 are:
Reviewed-by: Nanley Chery
> diff --git a/src/intel/b
t; if (isl_surf_usage_is_depth(info->usage)) {
>/* Depth requires Y. */
> diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c
> index e5d0f95402a..8e460430a1c 100644
> --- a/src/intel/isl/isl_gen9.c
> +++ b/src/intel/isl/isl_gen9.c
> @@ -41,7 +41,7 @@ gen9_calc_
On Tue, Jan 22, 2019 at 01:15:25PM +0200, Eleni Maria Stea wrote:
> On 1/22/19 12:46 PM, Eleni Maria Stea wrote:
> >>> + /**
> >>> +* \brief Indicates that we fake the ETC2 compression support
> >>> +*
> >>> +* GPUs Gen < 8 don't support sampling and rendering of ETC2
> >>> formats
On Tue, Jan 22, 2019 at 02:17:16PM +0200, Eleni Maria Stea wrote:
> On 1/19/19 1:32 AM, Nanley Chery wrote:
> >> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> >> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> >> index e214fae140..4d1eafa
On Mon, Nov 19, 2018 at 10:54:10AM +0200, Eleni Maria Stea wrote:
> Extended the intel_update_decompress_shadow to update all the mipmap
> tree levels so that we can display and run Get functions on mipmaps.
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 48 +++
> 1 file
On Mon, Nov 19, 2018 at 10:54:08AM +0200, Eleni Maria Stea wrote:
> On GPUs gen < 8 that don't support ETC2 sampling/rendering we now fake
> the support using 2 mipmap trees: one (the main) that stores the
> compressed data for the Get* functions to work and one (the shadow) that
> stores the same
On Mon, Nov 19, 2018 at 10:54:11AM +0200, Eleni Maria Stea wrote:
> Modified the calculation of the number of slices in the
> intel_update_decompressed_shadow function to take the array length into
> account to support arrays.
> ---
At this point, we can delete map_etc and unmap_etc, right?
On Mon, Nov 19, 2018 at 10:54:07AM +0200, Eleni Maria Stea wrote:
> GPUs Gen < 8 cannot render ETC2 formats. So far, they converted the
> compressed EAC/ETC2 images to non-compressed RGB format images that they
> can render. When GetCompressed* functions were called, the pixels were
> returned in
On Mon, Nov 19, 2018 at 10:54:06AM +0200, Eleni Maria Stea wrote:
> Renamed the r8stencil_mt and r8stencil_needs_update to shadow_mt and
> shadow_needs_update respectively to allow reusing the shadow_mt as a
> generic purpose secondary mipmap tree.
The series I pointed you to earlier has a patch
On Mon, Nov 19, 2018 at 10:54:05AM +0200, Eleni Maria Stea wrote:
> The assertions that the GL_MAP_WRITE_BIT and GL_MAP_INVALIDATE_RANGE_BIT
> in intel_miptree_map_etc should be removed since they will fail when the
^
missing "bits are set"?
> ETC miptree is mapped for reading.
>
The
On Fri, Oct 12, 2018 at 01:46:53PM -0500, Jason Ekstrand wrote:
> They are both implemented in ISL now. Instead of disabling them in ISL,
> we disable them in the two dirvers.
"drivers" is misspelled.
>
> Reviewed-by: Topi Pohjolainen
> ---
> src/intel/isl/isl_gen7.c | 8
On Mon, Oct 29, 2018 at 12:48:50PM +0100, Juan A. Suarez Romero wrote:
> On Thu, 2018-10-25 at 16:25 -0700, nanleych...@gmail.com wrote:
> > From: Nanley Chery
> >
> > Follow the restriction of making sure the clear value is between the min
> > and max values def
s tag should be
enough. Did I miss something here?
-Nanley
> On October 29, 2018 06:49:47 "Juan A. Suarez Romero"
> wrote:
>
> > On Thu, 2018-10-25 at 16:25 -0700, nanleych...@gmail.com wrote:
> > > From: Nanley Chery
> > >
> > > Follow t
On Fri, Oct 26, 2018 at 12:02:58PM -0500, Jason Ekstrand wrote:
> On Thu, Oct 25, 2018 at 6:25 PM wrote:
>
> > From: Nanley Chery
> >
> > Follow the restriction of making sure the clear value is between the min
> > and max values defined in CC_VIEWPORT. Avoids a
On Fri, Oct 19, 2018 at 10:51:36AM -0700, Kenneth Graunke wrote:
> Usually when making a new file, people copy some random other file
> to get the copyright header comments. Unfortunately, some of them
> are commented in a decades-old style, are word wrapped poorly, or
> worse, have a few subtle
On Mon, Oct 15, 2018 at 01:07:12PM -0500, Jason Ekstrand wrote:
> ---
> src/intel/vulkan/anv_formats.c | 8
> 1 file changed, 8 insertions(+)
>
This patch is
Reviewed-by: Nanley Chery
> diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
>
pth.c| 6 --
> 2 files changed, 9 insertions(+), 18 deletions(-)
>
Thank you for the changes. This patch is
Reviewed-by: Nanley Chery
I'll push it later today.
> diff --git a/src/mesa/main/format_pack.py b/src/mesa/main/format_pack.py
> index 0b9e0d424d..9fa4f412d4
This is basically a port of commit,
3ade766684933ac84e41634429fb693f85353c11
("i965: Disable 3DSTATE_WM_HZ_OP fields.")
The BDW+ docs describe how to use the 3DSTATE_WM_HZ_OP instruction in
the section titled, "Optimized Depth Buffer Clear and/or Stencil Buffer
Clear." It mentions that the packet
On Tue, Oct 02, 2018 at 04:59:17PM -0700, Nanley Chery wrote:
> On Wed, Sep 26, 2018 at 04:31:02PM -0700, Nanley Chery wrote:
> > The current workaround has two issues. It causes significant slow-downs [1]
> > in
> > application startup times and uses the modified ASTC bl
nction pack_uint_Z_FLOAT32_X24S8.
> Edited case in "_mesa_get_pack_uint_z_func".
> Now it looks like "_mesa_get_pack_float_z_func".
Please insert an empty line here.
> v2: by Nanley Chery
> -add coments
> -remove _mesa_problem call, which was added for debuging this issue
I didn't su
On Wed, Sep 26, 2018 at 04:31:11PM -0700, Nanley Chery wrote:
> Effectively revert 710b1d2e665ed654fb8d52b146fa22469e1dc3a7.
>
> This function was created to perform the ASTC void-extent workaround.
> Now that the workaround is handled prior to sampling, this function is
> no l
On Wed, Sep 26, 2018 at 04:31:02PM -0700, Nanley Chery wrote:
> The current workaround has two issues. It causes significant slow-downs [1] in
> application startup times and uses the modified ASTC blocks for non-sampling
> operations. This can result in incorrect texture
The Vulkan API was recently clarified to allow image views of different
formats to be used for rendering to the same image. Due to certain
incompatible clear-color encodings on gen7-8, we must be more careful
about which fast-clear values we allow.
Makes the following crucible test pass pre-SKL:
When sampling from an ASTC texture in a shader, make sure to use the
miptree which has had the gen9 void-extent workaround applied to it.
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
Don't access the pointers x and y if they're NULL. Nothing hits this
path currently.
---
src/intel/blorp/blorp_blit.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index ae3e3c50930..7c4e569e44c 100644
---
shadow_mt will hold a miptree with ASTC LDR void extent blocks that are
modified to workaround a sampler bug.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 1 +
2 files changed, 26 insertions(+)
diff --git
We've been using intel_mipmap_tree::surf instead. The tmp_surfs param
hasn't been used since commit: bf24c3539e4b6989512968cae12da2f88d2c53e9
("i965/miptree: Clean-up unused").
---
src/mesa/drivers/dri/i965/brw_blorp.c | 36 +--
1 file changed, 12 insertions(+), 24
Track whether or not the ASTC shadow miptree will need to be updated
prior to sampling.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git
Effectively revert 710b1d2e665ed654fb8d52b146fa22469e1dc3a7.
This function was created to perform the ASTC void-extent workaround.
Now that the workaround is handled prior to sampling, this function is
no longer necessary.
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 87
it in commit:
3e56e4642fb5875b3f5c4eb34798ba9f3d827705
Nanley Chery (9):
i965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*
i965/miptree: Allocate a shadow_mt for an ASTC WA
i965/miptree: Track the staleness of the ASTC shadow
intel/blorp_blit: Fix ptr deref in convert_to_uncompres
Use more generic field names. We'll reuse these fields for a workaround
with ASTC miptrees.
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8
src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 16
src/mesa/drivers/dri/i965/intel_mipmap_tree.h| 14
Perform a workaround blit prior to sampling from the ASTC miptree.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 20
src/mesa/drivers/dri/i965/brw_blorp.h | 6 ++
src/mesa/drivers/dri/i965/brw_draw.c | 16
3 files changed, 42 insertions(+)
diff --git
Add a function which copies blocks from one ASTC surface to another,
patching them up as necessary.
---
src/intel/blorp/blorp.h | 6 ++
src/intel/blorp/blorp_blit.c | 153 +++
src/intel/blorp/blorp_priv.h | 1 +
3 files changed, 160 insertions(+)
diff
On Tue, Sep 25, 2018 at 04:26:57PM -0700, Jordan Justen wrote:
> Signed-off-by: Jordan Justen
> Cc: Jason Ekstrand
> ---
> src/intel/vulkan/anv_device.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
This series is
Reviewed-by: Nanley Chery
> diff --g
On Tue, Sep 25, 2018 at 03:22:11PM -0700, Jordan Justen wrote:
> Signed-off-by: Jordan Justen
> Cc: Nanley Chery
> ---
> src/intel/vulkan/anv_device.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan
rameters
* renames row_pitch_tiles -> row_pitch_tl
Perhaps update the title to reflect this? Not a big deal though.
With or without an updated title, this patch is
Reviewed-by: Nanley Chery
> diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
> index 60cb32641
essing we should drop this patch... I'll send you more details.
-Nanley
> On September 21, 2018 19:12:28 Nanley Chery wrote:
>
> > Avoid an ICL fulsim failure. Makes 336 crucible tests under
> > func.depthstencil.stencil-triangles.clear-0x17.ref-0x17.* go from fail
> &
Avoid an ICL fulsim failure. Makes 336 crucible tests under
func.depthstencil.stencil-triangles.clear-0x17.ref-0x17.* go from fail
to pass with the simulator.
Fixes: 2cc3445eb24af469537911277f7bc4e73a6c5670
("anv/cmd_buffer: Decide whether or not to HiZ clear up-front")
---
(+), 1 deletion(-)
>
This patch is
Reviewed-by: Nanley Chery
> diff --git a/src/intel/vulkan/genX_gpu_memcpy.c
> b/src/intel/vulkan/genX_gpu_memcpy.c
> index 57abd8cd5c1..cba820a1866 100644
> --- a/src/intel/vulkan/genX_gpu_memcpy.c
> +++ b/src/intel/vulkan/genX_gpu_me
lace it with something like the following?
the GPU appears to also need this to avoid
occasional hangs when doing a clear with
WM_HZ_OP.
We could discuss it more on IRC if you prefer.
With that changed, this patch is
Reviewed-b
On Fri, Aug 31, 2018 at 04:04:22PM -0500, Jason Ekstrand wrote:
> We had the flush/stall after the clear but missed the one that needs to
> go before the clear.
>
Does this fix the GPU Hang in DiRT 3?
> Cc: mesa-sta...@lists.freedesktop.org
> Bugzilla:
On Thu, Aug 30, 2018 at 02:37:40PM -0700, Kenneth Graunke wrote:
> On Wednesday, August 29, 2018 1:38:51 PM PDT Nanley Chery wrote:
> > According to internal docs, some gen9 platforms have a pixel shader push
> > constant synchronization issue. Although not listed among sai
According to internal docs, some gen9 platforms have a pixel shader push
constant synchronization issue. Although not listed among said
platforms, this issue seems to be present on the GeminiLake 2x6's we've
tested.
We consider the available workarounds to be too detrimental on
performance.
On Mon, Aug 27, 2018 at 03:25:37PM -0700, Kenneth Graunke wrote:
> On Monday, August 27, 2018 11:03:33 AM PDT Nanley Chery wrote:
> > On Fri, Aug 24, 2018 at 05:46:44PM -0700, Nanley Chery wrote:
> > > According to internal docs, some gen9 platforms have a pixel shader p
On Fri, Aug 24, 2018 at 05:46:44PM -0700, Nanley Chery wrote:
> According to internal docs, some gen9 platforms have a pixel shader push
> constant synchronization issue. Although not listed among said
> platforms, this issue seems to be present on the GeminiLake 2x6's we've
> tes
On Fri, Aug 24, 2018 at 09:17:03PM -0400, Ilia Mirkin wrote:
> On Fri, Aug 24, 2018 at 8:46 PM, Nanley Chery wrote:
> > According to internal docs, some gen9 platforms have a pixel shader push
> > constant synchronization issue. Although not listed among said
> > platfo
According to internal docs, some gen9 platforms have a pixel shader push
constant synchronization issue. Although not listed among said
platforms, this issue seems to be present on the GeminiLake 2x6's we've
tested.
We consider the available workarounds to be too detrimental on
performance.
Check the destination's row pitch against the BLT engine's row pitch
limitation as well.
Fixes: 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
("i965/miptree: Use the correct BLT pitch")
v2: Fix the Fixes tag (Dylan).
Check the destination row pitch (Chris).
Cc:
Reported-by: Dylan Baker
---
I
Fix rendering issues on BDW and SKL.
Fixes: 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
("i965/miptree: Use the correct BLT pitch")
Fixes the following regressions seen
exclusively on SKL:
* KHR-GL46.texture_barrier_ARB.disjoint-texels
* KHR-GL46.texture_barrier_ARB.overlapping-texels
*
This struct contains all the data of interest. can_blit_slice() will use
it in the next patch to calculate the correct pitch.
Suggested-by: Chris Wilson
Cc:
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git
On Fri, Aug 10, 2018 at 02:12:55PM -0700, Dylan Baker wrote:
> Quoting Nanley Chery (2018-08-10 10:23:34)
> > Satisfy the BLT engine's row pitch limitation on the destination
> > miptree. The destination miptree is untiled, so its row_pitch will be
> > slightly less than o
Fix rendering issues on BDW and SKL.
Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
("i965/miptree: Use the correct BLT pitch")
Fixes the following regressions seen
exclusively on SKL:
* KHR-GL46.texture_barrier_ARB.disjoint-texels
* KHR-GL46.texture_barrier_ARB.overlapping-texels
*
Satisfy the BLT engine's row pitch limitation on the destination
miptree. The destination miptree is untiled, so its row_pitch will be
slightly less than or equal to the source miptree's row_pitch. Use the
source miptree's row_pitch in can_blit_slice instead of its blt_pitch.
Fixes
buffer_different_sizes
> GTF-GL46.gtf30.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit
>
>
Sorry about that, I must not have tested this in CI. I'll send out a
better tested v2.
-Nanley
> On Mon, 2018-07-30 at 19:25 +0300, Andres Gomez wrote:
> > That was quick! ☺
> >
> > On Fri, 2018-07-27 at 16:02
checks, simplify some existing checks and fix
> glCopyTexImage2D check (Nanley Chery)
>
> add SHORT and BYTE support in read_pixels_es3_error_check
>
> Signed-off-by: Tapani Pälli
> ---
> src/mesa/main/extensions_table.h | 1 +
> src/mesa/main/fbobject.c
Fix rendering issues on BDW and SKL.
Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
("i965/miptree: Use the correct BLT pitch")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107359
Cc:
---
We could probably add an assert when filling out the surface state, but
I think BLORP would need
i?id=107359
>
Hi Andres,
Thank you for the bug report. It turned out to be a HW issue. I'll send
a fix soon.
-Nanley
> On Mon, 2018-07-23 at 10:17 -0700, Nanley Chery wrote:
> > Satisfy the BLT engine's row pitch limitation on the destination
> > miptree. The destination
g a EGLImage to a texture
>
> Mauro Rossi (2):
> radv: winsys/amdgpu: include missing pthread.h header
> android: util/disk_cache: fix building errors in gallium drivers
>
> Michel Dänzer (1):
> gallium: Check pipe_screen::resource_changed before dereferencing it
>
+++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
Shouldn't we also update is_format_color_renderable?
Nonetheless, this series is an improvement and is
Reviewed-by: Nanley Chery
> diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
> index fa7a9361df.
On Mon, Jul 23, 2018 at 08:20:15PM +0100, Chris Wilson wrote:
> Quoting Nanley Chery (2018-07-23 18:17:15)
> > Satisfy the BLT engine's row pitch limitation on the destination
> > miptree. The destination miptree is untiled, so its row_pitch will be
> > slightly less than o
Satisfy the BLT engine's row pitch limitation on the destination
miptree. The destination miptree is untiled, so its row_pitch will be
slightly less than or equal to the source miptree's row_pitch. Use the
source miptree's row_pitch in can_blit_slice instead of its blt_pitch.
Fixes
and am running the fix
through jenkins (rebuild of the job above and a mesa_master build).
-Nanley
> Dylan
>
> Quoting Nanley Chery (2018-07-12 10:28:16)
> > Retile miptrees to a linear tiling less often. Retiling can cause issues
> > with imported BOs.
> >
> >
On Thu, Jul 19, 2018 at 10:16:47AM -0700, Kenneth Graunke wrote:
> On Tuesday, July 17, 2018 10:45:28 AM PDT Nanley Chery wrote:
> > On Tue, Jul 17, 2018 at 08:19:30AM -0700, Kenneth Graunke wrote:
> > > Personally, I'd be inclined to simply make this
> > >
> >
On Wed, Jul 18, 2018 at 05:34:13PM +0300, Eleni Maria Stea wrote:
> On 07/10/2018 03:10 AM, Nanley Chery wrote:
> > On Thu, Jun 14, 2018 at 10:50:57PM +0300, Eleni Maria Stea wrote:
> >> On 06/14/2018 10:27 PM, Nanley Chery wrote:
> >>
> >>> +Jason, Ken
&g
On Tue, Jul 17, 2018 at 01:29:26PM -0700, Kenneth Graunke wrote:
> On Tuesday, July 17, 2018 10:45:28 AM PDT Nanley Chery wrote:
> > On Tue, Jul 17, 2018 at 08:19:30AM -0700, Kenneth Graunke wrote:
> > > Wow, I had no idea we were actually using linear depth buffers.
> >
On Tue, Jul 17, 2018 at 08:19:30AM -0700, Kenneth Graunke wrote:
> On Monday, July 16, 2018 4:57:40 PM PDT Nanley Chery wrote:
> > Rendering to a linear depth buffer on gen4 is causing a GPU hang in the
> > CI system. Until a better explanation is found, assume that errata is
> &
Make the 3D engine aware of the depth/stencil surface's tiling before
doing any render operations.
Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").
Reported-by: Mark Janes
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 4 +++-
1 file
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