From: Kevin Rogovin
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 7b96947c60..48a7b030ce 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
From: Kevin Rogovin
Adds suppport for INTEL_fragment_shader_ordering. We achieve
the fragment ordering by using the same instruction as for
beginInvocationInterlockARB() which is by issuing a memory
fence via sendc.
Signed-off-by: Kevin Rogovin
---
docs/relnotes/18.3.0.html
From: Kevin Rogovin
This extension provides new GLSL built-in function
beginFragmentShaderOrderingIntel() that guarantees
(taking wording of GL_INTEL_fragment_shader_ordering
extension) that any memory transactions issued by
shader invocations from previous primitives mapped
From: Kevin Rogovin
INTEL_fragment_shader_ordering provides the ability for shaders
to issue a call to gaurnantee memory write operation ordering
of overlapping pixels or samples. In contrast to
ARB_fragment_shader_interlock, INTEL_fragment_shader_ordering
instead of defining a critical region
From: Kevin Rogovin
---
docs/relnotes/18.3.0.html | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
index 594b0624a5..afcb044817 100644
--- a/docs/relnotes/18.3.0.html
+++ b/docs/relnotes/18.3.0.html
@@ -59,6 +59,7 @@ Note: some of the new
From: Kevin Rogovin
---
docs/relnotes/18.3.0.html | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
index 594b0624a5..afcb044817 100644
--- a/docs/relnotes/18.3.0.html
+++ b/docs/relnotes/18.3.0.html
@@ -59,6 +59,7 @@ Note: some of the new
Thankyou for pushing; I will post the one liner for the release notes
shortly.
Best Regards,
-Kevin Rogovin
On Fri, 24 Aug 2018 at 3.44, Jason Ekstrand wrote:
> Your first version has already landed; Ken pushed it:
>
>
> https://cgit.freedesktop.org/mesa/mesa/c
From: Kevin Rogovin
The main purpose for having NV_fragment_shader_interlock
extension is because that extension is also for GLES31 while
the ARB extension is for GL only.
v2: Add to review notes (requested by Emil Velikov)
Reviewed-by: Plamena Manolova
---
docs/relnotes/18.3.0.html
Hi,
My request for an account was NAK'd by the i965 maintainer. As such, I
will post a v2 with the update to release notes requested and I hope
Plamena can push that for me.
Best Regards,
-Kevin Rogovin
On Tue, Aug 21, 2018 at 12:39 PM Emil Velikov
wrote:
> Hi Kevin,
>
> On 20 Au
nolova
>
> On Wed, Aug 15, 2018 at 2:29 PM, wrote:
>
>> From: Kevin Rogovin
>>
>> The main purpose for having NV_fragment_shader_interlock
>> extension is because that extension is also for GLES31 while
>> the ARB extension is for GL only.
at 2:29 PM, wrote:
>
>> From: Kevin Rogovin
>>
>> The main purpose for having NV_fragment_shader_interlock
>> extension is because that extension is also for GLES31 while
>> the ARB extension is for GL only.
>> ---
>> src/compiler/glsl/built
From: Kevin Rogovin
The main purpose for having NV_fragment_shader_interlock
extension is because that extension is also for GLES31 while
the ARB extension is for GL only.
---
src/compiler/glsl/builtin_functions.cpp | 18 ++
src/compiler/glsl/glsl_parser.yy | 6
From: Kevin Rogovin <kevin.rogo...@intel.com>
If ASTC5x5 textures are present, resolve all textures that the sampler
accesses so that auxilary buffer is unneeded when the astc5x5 workaround
is needed and also program the sampler state to not use the auxilary
buffer as well.
Signed-off-by:
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series implements a needed workaround for Gen9 for ASTC5x5
sampler reads. The crux of the work around is to make sure that the
sampler does not read an ASTC5x5 texture and a surface with an auxilary
buffer without having a texture
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/blorp/blorp.c | 16
src/intel/blorp/blorp.h | 6 ++
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 9 ++
From: Kevin Rogovin <kevin.rogo...@intel.com>
Gen9 GPU's suffer from a HW bug where the GPU will hang if
the GPU accesses a texture with a an auxilary buffer and
an ASTC5x5 texture without having a pipeline cs stall (and
texture cache flush) between such accesses. This patch
c
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_compute.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_com
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/intel_tex_validate.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c
b/src/mesa/driv
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_draw.c | 9 ++---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 5 +++--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++-
3 f
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series implements a needed workaround for Gen9 for ASTC5x5
sampler reads. The crux of the work around is to make sure that the
sampler does not read an ASTC5x5 texture and a surface with an auxilary
buffer without having a texture
From: Kevin Rogovin <kevin.rogo...@intel.com>
Gen9 GPU's suffer from a HW bug where the GPU will hang if
the GPU accesses a texture with a an auxilary buffer and
an ASTC5x5 texture without having a pipeline cs stall (and
texture cache flush) between such accesses. This patch
c
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_draw.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
i
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_draw.c | 20 ++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 7 +--
2 files changed, 23 insertions(+),
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 5 +
src/mesa/drivers/dri/i965/intel_tex_image.c | 16
2 files changed, 17 insertions(+), 4 deletions(-)
diff
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuf
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_d
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 101 -
src/mesa/drivers/dri/i965/brw_bufmgr.h | 13 +
2 files changed, 113 insertions(+), 1 delet
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series adds a new debug option to pad each GEM BO allocated
by the brw_bufmgr with (weak) pseudo-random noise values which are then
checked after each batchbuffer dispatch to the kernel. This can be quite
valuable to find diffucult to
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuf
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_d
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series adds a new debug option to pad each GEM BO
allocated by the brw_bufmgr with (weak) pseudo-random noise values
which are then checked after each batchbuffer dispatch to the kernel.
This can be quite valuable to find diffucult to
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 115 -
src/mesa/drivers/dri/i965/brw_bufmgr.h |
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuf
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 115 -
src/mesa/drivers/dri/i965/brw_bufmgr.h | 13
2 files changed, 127 insertions(+), 1 delet
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_d
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series adds a new debug option to pad each GEM BO
allocated by the brw_bufmgr with pseudo-(weak) random noise values
which are then checked after each batchbuffer dispatch to the kernel.
This can be quite valuable to find diffucult to
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/intel_tex_validate.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c
b/src/mesa/driv
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +
src/mesa/drivers/dri/i965/brw_context.c | 6 +
src/mesa/drivers/dri/i965/brw_context.h | 24
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_compute.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_compute.c
b/src/mesa/drivers/dri/i965/brw_com
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_draw.c | 16 ++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +
2 files changed, 19 insertions(+), 2 deleti
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 5 +
src/mesa/drivers/dri/i965/intel_tex_image.c | 16
2 files changed, 17 insertions(+), 4 deletions(-)
diff
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series implements a needed workaround for Gen9 for ASTC5x5
sampler reads. The crux of the work around is to make sure that the
sampler does not read an ASTC5x5 texture and a surface with an auxilary
buffer without having a texture
From: Kevin Rogovin <kevin.rogo...@intel.com>
v2:
Comments indicating that brw_bo_padding_is_good() will do the required
waiting for GPU commands to finish
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 19 +++
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_d
From: Kevin Rogovin <kevin.rogo...@intel.com>
v2:
Change from using rand() to using internal generating function
(requested/suggested by Jason Ekstrand)
Avoid having extra pointers in brw_bo struct via using the internal
function and allocating buffer for pread at brw_bo_padding_i
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series adds a new debug option to pad each GEM BO
allocated by the brw_bufmgr with pseudo-(weak) random noise values
which are then checked after each batchbuffer dispatch to the kernel.
This can be quite valuable to find diffucult to
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 105 -
src/mesa/drivers/dri/i965/brw_bufmgr.h | 8 +++
2 files changed, 112 insertions(+), 1 deletion(-)
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series adds a new debug option to pad each GEM BO
allocated by the brw_bufmgr with pseudo-(weak) random noise values
which are then checked after each batchbuffer dispatch to the kernel.
This can be quite valuable to find diffucult to
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_d
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_program.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/driv
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch is purely for readability improvements when programming
the MEDIA_VFE_STATE.
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 19 +--
1 file changed, 1
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series offers a readability improvement for programming
MEDIA_VFE_STATE and fixes a scratch space sizing bug for Gen9.
Together with the ASTC5x5 fixes posted before, carchase on GLES
works on my SKL GT4.
v2:
correctly state that
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upl
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series fixes 2 issues for scratch space
on compute shaders for GEN. Together with the ASTC5x5
fixes posted before, carchase on GLES works on my SKL
GT4.
Kevin Rogovin (2):
i965: correctly program MEDIA_VFE_STATE for compute s
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_program.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/driv
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
meson_options.txt | 6
src/intel/tools/meson.build | 71 +
2 files changed, 77 insertions(+)
diff --git a/meson_o
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am | 21 ++-
src/intel/tools/.gitignore| 1 +
src/intel/tools/gen_shader_disassembler.c | 213 +++
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am| 6 +-
src/intel/tools/.gitignore | 1 +
.../tools/i965_batchbuffer_dump_show_json.cp
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am | 5 +
src/intel/tools/.gitignore | 1 +
src/intel/tools/i965_batchbuffer_dump_show.c | 135 ++
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/compiler/brw_compile_clip.c | 4 +++-
src/intel/compiler/brw_compile_sf.c | 4 +++-
src/intel/compiler/brw_disasm_info.c | 4 +++-
src/in
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_d
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am| 6 +-
src/intel/tools/.gitignore | 1 +
src/intel/tools/i965_batchbuffer_dump_show_x
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am | 12 +++
src/intel/tools/.gitignore| 1 +
src/intel/tools/i965_batchbuffer_logger
From: Kevin Rogovin <kevin.rogo...@intel.com>
Reviewed-by: Matt Turner
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/tools/disasm.c | 6 +++---
src/intel/tools/gen_disasm.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/to
From: Kevin Rogovin <kevin.rogo...@intel.com>
Define the output format of the BatchbufferLogger. The output
is a sequence of blocks where blocks can have member blocks
or values. The top level blocks come from the application
calling into the BatchBufferLogger when an GL/GLES API call
is s
From: Kevin Rogovin <kevin.rogo...@intel.com>
The length function is needed if one wishes to save GEN binary
shaders to file.
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/tools/disasm.c | 7 +++
src/intel/tools/gen_disasm.h | 2 ++
2 files changed,
From: Kevin Rogovin <kevin.rogo...@intel.com>
The interface for BatchbufferLogger is that it is active
only if it is LD_PRELOAD'ed. Thus, the i965 driver is to
use dlsym to see if it is there, and if so fetch the object
at intel_screen creation.
Signed-off-by: Kevin Rogovin <k
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/driv
From: Kevin Rogovin <kevin.rogo...@intel.com>
Define the driver interface for BatchbufferLogger. The
interface assumes that for any -thread- there is only
one batchbuffer to which commands are to be added. A
driver needs to provide the information on what is the
active batchbuffer on a c
From: Kevin Rogovin <kevin.rogo...@intel.com>
Define the application interface to BatchbufferLogger. The
BatchbufferLogger needs from the application when a GL/GLES
API call is issues and returns. It will use this information
to correctly correlate batchbuffer additions to GL/GLES API
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series defines and implements a BatchbufferLogger
for Intel GEN. The main purpose of the BatchbufferLogger is
to strongly correlate API calls to data added to a batchbuffer.
In addition to this function, the BatchbufferLogger also
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/driv
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/common/gen_debug.c | 1 +
src/intel/common/gen_debug.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_d
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 68 +-
src/mesa/drivers/dri/i965/brw_bufmgr.h | 12 ++
2 files changed, 79 insertions(+), 1 delet
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series adds a new debug option to pad each GEM BO
allocated by the brw_bufmgr with random noise values which
are then checked after each batchbuffer dispatch to the kernel.
This can be quite valuable to find diffucult to trac
From: Kevin Rogovin <kevin.rogo...@intel.com>
One of the presteps in each draw (and compute) call is to validate
the textures. This is the perfect place (since all texture units
are looped through) to see if ASTC5x5 and/or textures with an
auxilary surface are accessed by the GPU.
Sign
From: Kevin Rogovin <kevin.rogo...@intel.com>
Some GEN's have a bug in the sample where if the sampler accesses
a texture with an auxialry surface and an ASTC5x5 texture without
having the texture cache invalidated between such accesses, then
the GPU will hang. This patch d
From: Kevin Rogovin <kevin.rogo...@intel.com>
Perform the ASTC5x5 workaround tasks for drawing; note that
the function does not do anything and immediately returns
if the bug is not present on the hardware.
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/driv
From: Kevin Rogovin <kevin.rogo...@intel.com>
Perform the ASTC5x5 workaround tasks for compute; note that
the function does not do anything and immediately returns
if the bug is not present on the hardware.
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/driv
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series implements a needed workaround for Gen9 for ASTC5x5
sampler reads. The crux of the work around is to make sure that the
sampler does not read an ASTC5x5 texture and a surface with an auxilary
buffer without having a texture
From: Kevin Rogovin <kevin.rogo...@intel.com>
Blorp will only read from an ASTC5x5 texture if it copies from
such a surface, that can only if an application is fetching
such pixels. Because an ASTC5x3 texture can never be a render
target, we do not need to worry about blorp reading such su
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am| 6 +-
src/intel/tools/.gitignore | 1 +
src/intel/tools/i965_batchbuffer_dump_show_x
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am | 21 ++-
src/intel/tools/.gitignore| 1 +
src/intel/tools/gen_shader_disassembler.c | 221 +++
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am| 6 +-
src/intel/tools/.gitignore | 1 +
.../tools/i965_batchbuffer_dump_show_json.cp
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
index 9919b5f241..c308b816f9 1006
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am | 5 ++
src/intel/tools/.gitignore | 1 +
src/intel/tools/i965_batchbuffer_dump_show.c | 129 ++
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/compiler/brw_eu.c | 11 ++-
src/intel/compiler/brw_eu.h | 3 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_eu.c
From: Kevin Rogovin <kevin.rogo...@intel.com>
Without this fix, disassembling of GEN shaders with GPU commands
that the disassembler does not know would result in errors being
added to the annotator which would crash when more than one error
was added.
Signed-off-by: Kevin Rogovin <k
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/tools/disasm.c | 6 +++---
src/intel/tools/gen_disasm.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/tools/disasm.c b/src
From: Kevin Rogovin <kevin.rogo...@intel.com>
Without this patch, if a shader has errors, the disassembly of the
shader often stops after the first opcode that has errors.
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/tools/disasm.c | 13 +
1 fil
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/Makefile.tools.am | 8 ++
src/intel/tools/.gitignore| 1 +
src/intel/tools/i965_batchbuffer_logger
From: Kevin Rogovin <kevin.rogo...@intel.com>
The length function is needed if one wishes to save GEN binary
shaders to file.
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/tools/disasm.c | 7 +++
src/intel/tools/gen_disasm.h | 2 ++
2 files changed,
From: Kevin Rogovin <kevin.rogo...@intel.com>
This patch series defines and implements a BatchbufferLogger
for Intel GEN. The main purpose of the BatchbufferLogger is
to strongly correlate API calls to data added to a batchbuffer.
In addition to this function, the BatchbufferLogger also
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/intel/common/gen_decoder.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/intel/common/gen_decoder.h b/src/intel/common/gen_decoder.h
index 8b00b6edc2..e3b24
From: Kevin Rogovin <kevin.rogo...@intel.com>
Define the driver interface for BatchbufferLogger. The
interface assumes that for any -thread- there is only
one batchbuffer to which commands are to be added. A
driver needs to provide the information on what is the
active batchbuffer on a c
From: Kevin Rogovin <kevin.rogo...@intel.com>
The interface for BatchbufferLogger is that it is active
only if it is LD_PRELOAD'ed. Thus, the i965 driver is to
use dlsym to see if it is there, and if so fetch the object
at intel_screen creation.
Signed-off-by: Kevin Rogovin <k
From: Kevin Rogovin <kevin.rogo...@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com>
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/driv
From: Kevin Rogovin <kevin.rogo...@intel.com>
Define the application interface to BatchbufferLogger. The
BatchbufferLogger needs from the application when a GL/GLES
API call is issues and returns. It will use this information
to correctly correlate batchbuffer additions to GL/GLES API
From: Kevin Rogovin <kevin.rogo...@intel.com>
Define the output format of the BatchbufferLogger. The output
is a sequence of blocks where blocks can have member blocks
or values. The top level blocks come from the application
calling into the BatchBufferLogger when an GL/GLES API call
is s
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