Re: [Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Pohjolainen, Topi]

On Thu, Apr 21, 2016 at 08:03:02AM +0300, Pohjolainen, Topi wrote:
> On Wed, Apr 20, 2016 at 09:49:02PM -0700, Ben Widawsky wrote:
> > From: Ben Widawsky 
> > 
> > Starting with Skylake, the display engine is capable of scanning out from
> > Y-tiled buffers. As such, we can and should use Y-tiling for better 
> > efficiency.
> > This also has the added benefit of being able to fast clear the winsys 
> > buffer.
> > 
> > Note that the buffer allocation done for mipmaps will already never 
> > allocate an
> > X-tiled buffer for GEN9.
> > 
> > Here is the statistically significant difference (percentage) with this 
> > patch. I
> > do not know why we did see these kind of results earlier. This is on a SKL 
> > gt3e
> > with a resolution of 3200x1800.
> 
> Yes, please. A few comments but:
> 
> Reviewed-by: Topi Pohjolainen 
> 
> > 
> > Benchmark  a-master->b-yscanout
> > OglBatch0  8.56
> > OglBatch1  6.85
> > OglBatch2  5.0
> > OglBatch3  4.48
> > OglBatch4  4.16
> > OglBatch6  3.57
> > OglBatch7  2.96
> > OglFillPixel   1.91
> > OglGeomPoint   4.43
> > OglGeomTriList 2.83
> > OglPSBump8 0.32
> > OglShMapVsm6.61
> > OglTerrainFlyInst  5.2
> > OglVSTangent   3.03
> > OglZBuffer 8.88
> > egypt  14.54
> > manhattan  1.59
> > manhattanoff   -0.25
> > triangle   15.35
> > warsow 2.26
> > xonotic7.9
> > 
> > Signed-off-by: Ben Widawsky 
> > ---
> >  src/mesa/drivers/dri/i965/brw_meta_fast_clear.c |  4 ++--
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.c   |  9 +++--
> >  src/mesa/drivers/dri/i965/intel_mipmap_tree.h   |  3 ++-
> >  src/mesa/drivers/dri/i965/intel_screen.c| 21 ++---
> >  4 files changed, 29 insertions(+), 8 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c 
> > b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> > index 1fb5dc8..cf634a2 100644
> > --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> > +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> > @@ -240,7 +240,7 @@ get_fast_clear_rect(struct brw_context *brw, struct 
> > gl_framebuffer *fb,
> > * alignment size returned by intel_get_non_msrt_mcs_alignment(), but
> > * with X alignment multiplied by 16 and Y alignment multiplied by 
> > 32.
> > */
> > -  intel_get_non_msrt_mcs_alignment(irb->mt, _align, _align);
> > +  intel_get_non_msrt_mcs_alignment(brw, irb->mt, _align, _align);
> >x_align *= 16;
> >  
> >/* SKL+ line alignment requirement for Y-tiled are half those of the 
> > prior
> > @@ -821,7 +821,7 @@ get_resolve_rect(struct brw_context *brw,
> >  * by a factor of 2.
> >  */
> >  
> > -   intel_get_non_msrt_mcs_alignment(mt, _align, _align);
> > +   intel_get_non_msrt_mcs_alignment(brw, mt, _align, _align);
> > if (brw->gen >= 9) {
> >x_scaledown = x_align * 8;
> >y_scaledown = y_align * 8;
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index d263ff8..a793370 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -144,7 +144,8 @@ compute_msaa_layout(struct brw_context *brw, 
> > mesa_format format,
> >   *   by half the block width, and Y coordinates by half the block height.
> >   */
> >  void
> > -intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
> > +intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
> > + struct intel_mipmap_tree *mt,
> 
> I think you could mark mt as const while you are at it if you like.
> 
> >   unsigned *width_px, unsigned *height)
> >  {
> > switch (mt->tiling) {
> > @@ -156,6 +157,10 @@ intel_get_non_msrt_mcs_alignment(struct 
> > intel_mipmap_tree *mt,
> >*height = 4;
> >break;
> > case I915_TILING_X:
> > +  /* The docs are somewhat confusing with the way the tables are 
> > displayed.
> > +   * However, it does clearly state: "MCS and Lossless compression is
> > +   * supported for TiledY/TileYs/TileYf non-MSRTs only." */
> 
> Comment closing on its own line. I'm also a little confused if this comment is
> really related to this patch.

It does belong here, my mistake, sorry.
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Re: [Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Kenneth Graunke]

On Wednesday, April 20, 2016 9:49:02 PM PDT Ben Widawsky wrote:
> From: Ben Widawsky 
> 
> Starting with Skylake, the display engine is capable of scanning out from
> Y-tiled buffers. As such, we can and should use Y-tiling for better 
efficiency.
> This also has the added benefit of being able to fast clear the winsys 
buffer.
> 
> Note that the buffer allocation done for mipmaps will already never allocate 
an
> X-tiled buffer for GEN9.
> 
> Here is the statistically significant difference (percentage) with this 
patch. I
> do not know why we did see these kind of results earlier. This is on a SKL 
gt3e
> with a resolution of 3200x1800.
> 
> Benchmark  a-master->b-yscanout
> OglBatch0  8.56
> OglBatch1  6.85
> OglBatch2  5.0
> OglBatch3  4.48
> OglBatch4  4.16
> OglBatch6  3.57
> OglBatch7  2.96
> OglFillPixel   1.91
> OglGeomPoint   4.43
> OglGeomTriList 2.83
> OglPSBump8 0.32
> OglShMapVsm6.61
> OglTerrainFlyInst  5.2
> OglVSTangent   3.03
> OglZBuffer 8.88
> egypt  14.54
> manhattan  1.59
> manhattanoff   -0.25
> triangle   15.35
> warsow 2.26
> xonotic7.9
> 
> Signed-off-by: Ben Widawsky 

I don't know why we didn't see this earlier, either.  I wonder if
there's some version dependency with xf86-video-intel/kernel.

Regardless, these are the results I'd expect at last, and this is
basically the same patch I wrote while trying it myself (except yours is
better), so...

Reviewed-by: Kenneth Graunke 

one nit below

> ---
>  src/mesa/drivers/dri/i965/brw_meta_fast_clear.c |  4 ++--
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c   |  9 +++--
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h   |  3 ++-
>  src/mesa/drivers/dri/i965/intel_screen.c| 21 ++---
>  4 files changed, 29 insertions(+), 8 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/
drivers/dri/i965/brw_meta_fast_clear.c
> index 1fb5dc8..cf634a2 100644
> --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> @@ -240,7 +240,7 @@ get_fast_clear_rect(struct brw_context *brw, struct 
gl_framebuffer *fb,
> * alignment size returned by intel_get_non_msrt_mcs_alignment(), but
> * with X alignment multiplied by 16 and Y alignment multiplied by 
32.
> */
> -  intel_get_non_msrt_mcs_alignment(irb->mt, _align, _align);
> +  intel_get_non_msrt_mcs_alignment(brw, irb->mt, _align, _align);
>x_align *= 16;
>  
>/* SKL+ line alignment requirement for Y-tiled are half those of the 
prior
> @@ -821,7 +821,7 @@ get_resolve_rect(struct brw_context *brw,
>  * by a factor of 2.
>  */
>  
> -   intel_get_non_msrt_mcs_alignment(mt, _align, _align);
> +   intel_get_non_msrt_mcs_alignment(brw, mt, _align, _align);
> if (brw->gen >= 9) {
>x_scaledown = x_align * 8;
>y_scaledown = y_align * 8;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/
drivers/dri/i965/intel_mipmap_tree.c
> index d263ff8..a793370 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -144,7 +144,8 @@ compute_msaa_layout(struct brw_context *brw, mesa_format 
format,
>   *   by half the block width, and Y coordinates by half the block height.
>   */
>  void
> -intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
> +intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
> + struct intel_mipmap_tree *mt,
>   unsigned *width_px, unsigned *height)
>  {
> switch (mt->tiling) {
> @@ -156,6 +157,10 @@ intel_get_non_msrt_mcs_alignment(struct 
intel_mipmap_tree *mt,
>*height = 4;
>break;
> case I915_TILING_X:
> +  /* The docs are somewhat confusing with the way the tables are 
displayed.
> +   * However, it does clearly state: "MCS and Lossless compression is
> +   * supported for TiledY/TileYs/TileYf non-MSRTs only." */

*/ goes on its own line


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Re: [Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Pohjolainen, Topi]

On Wed, Apr 20, 2016 at 09:49:02PM -0700, Ben Widawsky wrote:
> From: Ben Widawsky 
> 
> Starting with Skylake, the display engine is capable of scanning out from
> Y-tiled buffers. As such, we can and should use Y-tiling for better 
> efficiency.
> This also has the added benefit of being able to fast clear the winsys buffer.
> 
> Note that the buffer allocation done for mipmaps will already never allocate 
> an
> X-tiled buffer for GEN9.
> 
> Here is the statistically significant difference (percentage) with this 
> patch. I
> do not know why we did see these kind of results earlier. This is on a SKL 
> gt3e
> with a resolution of 3200x1800.

Yes, please. A few comments but:

Reviewed-by: Topi Pohjolainen 

> 
> Benchmark  a-master->b-yscanout
> OglBatch0  8.56
> OglBatch1  6.85
> OglBatch2  5.0
> OglBatch3  4.48
> OglBatch4  4.16
> OglBatch6  3.57
> OglBatch7  2.96
> OglFillPixel   1.91
> OglGeomPoint   4.43
> OglGeomTriList 2.83
> OglPSBump8 0.32
> OglShMapVsm6.61
> OglTerrainFlyInst  5.2
> OglVSTangent   3.03
> OglZBuffer 8.88
> egypt  14.54
> manhattan  1.59
> manhattanoff   -0.25
> triangle   15.35
> warsow 2.26
> xonotic7.9
> 
> Signed-off-by: Ben Widawsky 
> ---
>  src/mesa/drivers/dri/i965/brw_meta_fast_clear.c |  4 ++--
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c   |  9 +++--
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.h   |  3 ++-
>  src/mesa/drivers/dri/i965/intel_screen.c| 21 ++---
>  4 files changed, 29 insertions(+), 8 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c 
> b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> index 1fb5dc8..cf634a2 100644
> --- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> +++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
> @@ -240,7 +240,7 @@ get_fast_clear_rect(struct brw_context *brw, struct 
> gl_framebuffer *fb,
> * alignment size returned by intel_get_non_msrt_mcs_alignment(), but
> * with X alignment multiplied by 16 and Y alignment multiplied by 32.
> */
> -  intel_get_non_msrt_mcs_alignment(irb->mt, _align, _align);
> +  intel_get_non_msrt_mcs_alignment(brw, irb->mt, _align, _align);
>x_align *= 16;
>  
>/* SKL+ line alignment requirement for Y-tiled are half those of the 
> prior
> @@ -821,7 +821,7 @@ get_resolve_rect(struct brw_context *brw,
>  * by a factor of 2.
>  */
>  
> -   intel_get_non_msrt_mcs_alignment(mt, _align, _align);
> +   intel_get_non_msrt_mcs_alignment(brw, mt, _align, _align);
> if (brw->gen >= 9) {
>x_scaledown = x_align * 8;
>y_scaledown = y_align * 8;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index d263ff8..a793370 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -144,7 +144,8 @@ compute_msaa_layout(struct brw_context *brw, mesa_format 
> format,
>   *   by half the block width, and Y coordinates by half the block height.
>   */
>  void
> -intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
> +intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
> + struct intel_mipmap_tree *mt,

I think you could mark mt as const while you are at it if you like.

>   unsigned *width_px, unsigned *height)
>  {
> switch (mt->tiling) {
> @@ -156,6 +157,10 @@ intel_get_non_msrt_mcs_alignment(struct 
> intel_mipmap_tree *mt,
>*height = 4;
>break;
> case I915_TILING_X:
> +  /* The docs are somewhat confusing with the way the tables are 
> displayed.
> +   * However, it does clearly state: "MCS and Lossless compression is
> +   * supported for TiledY/TileYs/TileYf non-MSRTs only." */

Comment closing on its own line. I'm also a little confused if this comment is
really related to this patch.

> +  assert(brw->gen < 9);
>*width_px = 64 / mt->cpp;
>*height = 2;
> }
> @@ -1552,7 +1557,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context 
> *brw,
> const mesa_format format = MESA_FORMAT_R_UINT32;
> unsigned block_width_px;
> unsigned block_height;
> -   intel_get_non_msrt_mcs_alignment(mt, _width_px, _height);
> +   intel_get_non_msrt_mcs_alignment(brw, mt, _width_px, _height);
> unsigned width_divisor = block_width_px * 4;
> unsigned height_divisor = block_height * 8;
>  
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 7cdfb37..826f572 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -663,7 +663,8 @@ struct intel_mipmap_tree

[Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Ben Widawsky]

From: Ben Widawsky 

Starting with Skylake, the display engine is capable of scanning out from
Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency.
This also has the added benefit of being able to fast clear the winsys buffer.

Note that the buffer allocation done for mipmaps will already never allocate an
X-tiled buffer for GEN9.

Here is the statistically significant difference (percentage) with this patch. I
do not know why we did see these kind of results earlier. This is on a SKL gt3e
with a resolution of 3200x1800.

Benchmark  a-master->b-yscanout
OglBatch0  8.56
OglBatch1  6.85
OglBatch2  5.0
OglBatch3  4.48
OglBatch4  4.16
OglBatch6  3.57
OglBatch7  2.96
OglFillPixel   1.91
OglGeomPoint   4.43
OglGeomTriList 2.83
OglPSBump8 0.32
OglShMapVsm6.61
OglTerrainFlyInst  5.2
OglVSTangent   3.03
OglZBuffer 8.88
egypt  14.54
manhattan  1.59
manhattanoff   -0.25
triangle   15.35
warsow 2.26
xonotic7.9

Signed-off-by: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/brw_meta_fast_clear.c |  4 ++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c   |  9 +++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h   |  3 ++-
 src/mesa/drivers/dri/i965/intel_screen.c| 21 ++---
 4 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c 
b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 1fb5dc8..cf634a2 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -240,7 +240,7 @@ get_fast_clear_rect(struct brw_context *brw, struct 
gl_framebuffer *fb,
* alignment size returned by intel_get_non_msrt_mcs_alignment(), but
* with X alignment multiplied by 16 and Y alignment multiplied by 32.
*/
-  intel_get_non_msrt_mcs_alignment(irb->mt, _align, _align);
+  intel_get_non_msrt_mcs_alignment(brw, irb->mt, _align, _align);
   x_align *= 16;
 
   /* SKL+ line alignment requirement for Y-tiled are half those of the 
prior
@@ -821,7 +821,7 @@ get_resolve_rect(struct brw_context *brw,
 * by a factor of 2.
 */
 
-   intel_get_non_msrt_mcs_alignment(mt, _align, _align);
+   intel_get_non_msrt_mcs_alignment(brw, mt, _align, _align);
if (brw->gen >= 9) {
   x_scaledown = x_align * 8;
   y_scaledown = y_align * 8;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d263ff8..a793370 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -144,7 +144,8 @@ compute_msaa_layout(struct brw_context *brw, mesa_format 
format,
  *   by half the block width, and Y coordinates by half the block height.
  */
 void
-intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
+intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
  unsigned *width_px, unsigned *height)
 {
switch (mt->tiling) {
@@ -156,6 +157,10 @@ intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree 
*mt,
   *height = 4;
   break;
case I915_TILING_X:
+  /* The docs are somewhat confusing with the way the tables are displayed.
+   * However, it does clearly state: "MCS and Lossless compression is
+   * supported for TiledY/TileYs/TileYf non-MSRTs only." */
+  assert(brw->gen < 9);
   *width_px = 64 / mt->cpp;
   *height = 2;
}
@@ -1552,7 +1557,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
const mesa_format format = MESA_FORMAT_R_UINT32;
unsigned block_width_px;
unsigned block_height;
-   intel_get_non_msrt_mcs_alignment(mt, _width_px, _height);
+   intel_get_non_msrt_mcs_alignment(brw, mt, _width_px, _height);
unsigned width_divisor = block_width_px * 4;
unsigned height_divisor = block_height * 8;
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 7cdfb37..826f572 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -663,7 +663,8 @@ struct intel_mipmap_tree
 };
 
 void
-intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt,
+intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
  unsigned *width_px, unsigned *height);
 
 bool
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index db9d94d..878901a 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -516,7 +516,11 @@ intel_create_image(__DRIscreen *screen,
int 

Re: [Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Neil Roberts]

Hi,

Has this situation changed at all? It's probably quite important to get
this working because we have to disable fast clears for X-tiled buffers
on SKL which effectively means we currently can't do it for window
system buffers.

Regards,
- Neil

Chris Wilson  writes:

> On Mon, Apr 13, 2015 at 04:31:29PM +0200, Daniel Vetter wrote:
>> On Sat, Apr 11, 2015 at 01:16:11PM -0700, Ben Widawsky wrote:
>> > Starting with Skylake, the display engine is capable of scanning out from
>> > Y-tiled buffers. As such, we can and should use Y-tiling for better 
>> > efficiency.
>> > 
>> > Note that the buffer allocation done for mipmaps will already never 
>> > allocate an
>> > X-tiled buffer for GEN9.
>> > 
>> > Signed-off-by: Ben Widawsky 
>> 
>> You need a recent enough ddx to make use of Y-tiled buffers, which atm
>> still doesn't yet exist. This would at least need some kind of handshake
>> with the compositor to make sure it understands this, presuming I didn't
>> miss something.
>
> You can send Y-tiled buffers to the DDX. The problem is that the kernel
> won't allow us to display them and so we will (and always have been)
> copying from them.
> -Chris
>
> -- 
> Chris Wilson, Intel Open Source Technology Centre
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Re: [Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Chris Wilson]

On Mon, Apr 13, 2015 at 04:31:29PM +0200, Daniel Vetter wrote:
 On Sat, Apr 11, 2015 at 01:16:11PM -0700, Ben Widawsky wrote:
  Starting with Skylake, the display engine is capable of scanning out from
  Y-tiled buffers. As such, we can and should use Y-tiling for better 
  efficiency.
  
  Note that the buffer allocation done for mipmaps will already never 
  allocate an
  X-tiled buffer for GEN9.
  
  Signed-off-by: Ben Widawsky b...@bwidawsk.net
 
 You need a recent enough ddx to make use of Y-tiled buffers, which atm
 still doesn't yet exist. This would at least need some kind of handshake
 with the compositor to make sure it understands this, presuming I didn't
 miss something.

You can send Y-tiled buffers to the DDX. The problem is that the kernel
won't allow us to display them and so we will (and always have been)
copying from them.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Daniel Vetter]

On Sat, Apr 11, 2015 at 01:16:11PM -0700, Ben Widawsky wrote:
 Starting with Skylake, the display engine is capable of scanning out from
 Y-tiled buffers. As such, we can and should use Y-tiling for better 
 efficiency.
 
 Note that the buffer allocation done for mipmaps will already never allocate 
 an
 X-tiled buffer for GEN9.
 
 Signed-off-by: Ben Widawsky b...@bwidawsk.net

You need a recent enough ddx to make use of Y-tiled buffers, which atm
still doesn't yet exist. This would at least need some kind of handshake
with the compositor to make sure it understands this, presuming I didn't
miss something.

 ---
  src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  4 
  src/mesa/drivers/dri/i965/intel_screen.c  | 21 ++---
  2 files changed, 22 insertions(+), 3 deletions(-)
 
 diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
 b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
 index eb226d5..4408ac9 100644
 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
 +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
 @@ -142,6 +142,10 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
*height = 4;
break;
 case I915_TILING_X:
 +  /* The docs are somewhat confusing with the way the tables are 
 displayed.
 +   * However, it does clearly state: MCS and Lossless compression is
 +   * supported for TiledY/TileYs/TileYf non-MSRTs only. */
 +  assert(brw-gen  9);
*width_px = 64 / mt-cpp;
*height = 2;
 }
 diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
 b/src/mesa/drivers/dri/i965/intel_screen.c
 index cb9710f..06f0a06 100644
 --- a/src/mesa/drivers/dri/i965/intel_screen.c
 +++ b/src/mesa/drivers/dri/i965/intel_screen.c
 @@ -510,7 +510,11 @@ intel_create_image(__DRIscreen *screen,
 int cpp;
 unsigned long pitch;
  
 -   tiling = I915_TILING_X;
 +   if (intelScreen-devinfo-gen = 9) {
 +  tiling = I915_TILING_Y;
 +   } else {
 +  tiling = I915_TILING_X;
 +   }
 if (use  __DRI_IMAGE_USE_CURSOR) {
if (width != 64 || height != 64)
return NULL;
 @@ -1101,8 +1105,14 @@ intel_detect_swizzling(struct intel_screen *screen)
 drm_intel_bo *buffer;
 unsigned long flags = 0;
 unsigned long aligned_pitch;
 -   uint32_t tiling = I915_TILING_X;
 uint32_t swizzle_mode = 0;
 +   uint32_t tiling;
 +
 +   if (screen-devinfo-gen = 9) {
 +  tiling = I915_TILING_Y;
 +   } else {
 +  tiling = I915_TILING_X;
 +   }

Unneeded change (swizzling doesn't change between X and Y tiled) and gen9+
is hardcoded to unswizzled in the hw anyway.
-Daniel

  
 buffer = drm_intel_bo_alloc_tiled(screen-bufmgr, swizzle test,
64, 64, 4,
 @@ -1409,7 +1419,12 @@ intelAllocateBuffer(__DRIscreen *screen,
return NULL;
  
 /* The front and back buffers are color buffers, which are X tiled. */
 -   uint32_t tiling = I915_TILING_X;
 +   uint32_t tiling;
 +   if (intelScreen-devinfo-gen = 9) {
 +  tiling = I915_TILING_Y;
 +   } else {
 +  tiling = I915_TILING_X;
 +   }
 unsigned long pitch;
 int cpp = format / 8;
 intelBuffer-bo = drm_intel_bo_alloc_tiled(intelScreen-bufmgr,
 -- 
 2.3.5
 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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[Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

[Ben Widawsky]

Starting with Skylake, the display engine is capable of scanning out from
Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency.

Note that the buffer allocation done for mipmaps will already never allocate an
X-tiled buffer for GEN9.

Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  4 
 src/mesa/drivers/dri/i965/intel_screen.c  | 21 ++---
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index eb226d5..4408ac9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -142,6 +142,10 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
   *height = 4;
   break;
case I915_TILING_X:
+  /* The docs are somewhat confusing with the way the tables are displayed.
+   * However, it does clearly state: MCS and Lossless compression is
+   * supported for TiledY/TileYs/TileYf non-MSRTs only. */
+  assert(brw-gen  9);
   *width_px = 64 / mt-cpp;
   *height = 2;
}
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index cb9710f..06f0a06 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -510,7 +510,11 @@ intel_create_image(__DRIscreen *screen,
int cpp;
unsigned long pitch;
 
-   tiling = I915_TILING_X;
+   if (intelScreen-devinfo-gen = 9) {
+  tiling = I915_TILING_Y;
+   } else {
+  tiling = I915_TILING_X;
+   }
if (use  __DRI_IMAGE_USE_CURSOR) {
   if (width != 64 || height != 64)
 return NULL;
@@ -1101,8 +1105,14 @@ intel_detect_swizzling(struct intel_screen *screen)
drm_intel_bo *buffer;
unsigned long flags = 0;
unsigned long aligned_pitch;
-   uint32_t tiling = I915_TILING_X;
uint32_t swizzle_mode = 0;
+   uint32_t tiling;
+
+   if (screen-devinfo-gen = 9) {
+  tiling = I915_TILING_Y;
+   } else {
+  tiling = I915_TILING_X;
+   }
 
buffer = drm_intel_bo_alloc_tiled(screen-bufmgr, swizzle test,
 64, 64, 4,
@@ -1409,7 +1419,12 @@ intelAllocateBuffer(__DRIscreen *screen,
   return NULL;
 
/* The front and back buffers are color buffers, which are X tiled. */
-   uint32_t tiling = I915_TILING_X;
+   uint32_t tiling;
+   if (intelScreen-devinfo-gen = 9) {
+  tiling = I915_TILING_Y;
+   } else {
+  tiling = I915_TILING_X;
+   }
unsigned long pitch;
int cpp = format / 8;
intelBuffer-bo = drm_intel_bo_alloc_tiled(intelScreen-bufmgr,
-- 
2.3.5

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