Re: [Mesa-dev] [PATCH] nvc0: allow TK1 (NVEA) queries to work

2017-01-16 Thread Pierre Moreau 
On 07:13 pm - Jan 15 2017, Samuel Pitoiset wrote:
> 
> 
> On 01/14/2017 02:35 AM, Ilia Mirkin wrote:
> > The NVEA 3D class is numerically larger than the NVF0 3D class. The TK1
> > chip uses the SM35 ISA and likely has the same hw counters. Allow these
> > to be used like on all the other supported chips.
> 
> This actually needs more testing. Perf counters are pretty different for
> each generation. The kernel used for reading the counters will work though,
> but the configuration has to be double checked.
> 
> More comments inline.
> 
> > 
> > Signed-off-by: Ilia Mirkin 
> > ---
> >  src/gallium/drivers/nouveau/nvc0/nvc0_query.c |  4 ++--
> >  .../drivers/nouveau/nvc0/nvc0_query_hw_metric.c   |  3 +++
> >  src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c   | 19 
> > ++-
> >  3 files changed, 15 insertions(+), 11 deletions(-)
> > 
> > diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c 
> > b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
> > index 8b9e6b6..6bf2285 100644
> > --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
> > +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
> > @@ -205,7 +205,7 @@ nvc0_screen_get_driver_query_group_info(struct 
> > pipe_screen *pscreen,
> > 
> > if (screen->base.drm->version >= 0x01000101) {
> >if (screen->compute) {
> > - if (screen->base.class_3d <= NVF0_3D_CLASS) {
> > + if (screen->base.class_3d < GM107_3D_CLASS) {
> >  count += 2;
> >   }
> >}
> > @@ -229,7 +229,7 @@ nvc0_screen_get_driver_query_group_info(struct 
> > pipe_screen *pscreen,
> > } else
> > if (id == NVC0_HW_METRIC_QUERY_GROUP) {
> >if (screen->compute) {
> > -  if (screen->base.class_3d <= NVF0_3D_CLASS) {
> > +  if (screen->base.class_3d < GM107_3D_CLASS) {
> 
> Oops, I forgot to expose these groups when I added Maxwell support. These
> groups are only used for AMD_performance_monitor. Presumably this ext
> currently doesn't expose the counters on Maxwell.
> 
> We should enable them in a separate patch just before this one (for
> maxwell).

Do you need me to test anything on Maxwell?

Pierre

> 
> Otherwise, looks good.
> 
> >  info->name = "Performance metrics";
> >  info->max_active_queries = 4; /* A metric uses at least 2 
> > queries */
> >  info->num_queries = nvc0_hw_metric_get_num_queries(screen);
> > diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c 
> > b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
> > index 089af61..494f2dd 100644
> > --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
> > +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
> > @@ -403,6 +403,7 @@ nvc0_hw_metric_get_queries(struct nvc0_screen *screen)
> > case GM200_3D_CLASS:
> > case GM107_3D_CLASS:
> >return sm50_hw_metric_queries;
> > +   case NVEA_3D_CLASS:
> > case NVF0_3D_CLASS:
> >return sm35_hw_metric_queries;
> > case NVE4_3D_CLASS:
> > @@ -425,6 +426,7 @@ nvc0_hw_metric_get_num_queries(struct nvc0_screen 
> > *screen)
> > case GM200_3D_CLASS:
> > case GM107_3D_CLASS:
> >return ARRAY_SIZE(sm50_hw_metric_queries);
> > +   case NVEA_3D_CLASS:
> > case NVF0_3D_CLASS:
> >return ARRAY_SIZE(sm35_hw_metric_queries);
> > case NVE4_3D_CLASS:
> > @@ -684,6 +686,7 @@ nvc0_hw_metric_get_query_result(struct nvc0_context 
> > *nvc0,
> > switch (screen->base.class_3d) {
> > case GM200_3D_CLASS:
> > case GM107_3D_CLASS:
> > +   case NVEA_3D_CLASS:
> > case NVF0_3D_CLASS:
> >value = sm35_hw_metric_calc_result(hq, res64);
> >break;
> > diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c 
> > b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
> > index df5723d..440e5d3 100644
> > --- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
> > +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
> > @@ -2239,6 +2239,7 @@ nvc0_hw_sm_get_queries(struct nvc0_screen *screen)
> >return sm52_hw_sm_queries;
> > case GM107_3D_CLASS:
> >return sm50_hw_sm_queries;
> > +   case NVEA_3D_CLASS:
> > case NVF0_3D_CLASS:
> >return sm35_hw_sm_queries;
> > case NVE4_3D_CLASS:
> > @@ -2262,6 +2263,7 @@ nvc0_hw_sm_get_num_queries(struct nvc0_screen *screen)
> >return ARRAY_SIZE(sm52_hw_sm_queries);
> > case GM107_3D_CLASS:
> >return ARRAY_SIZE(sm50_hw_sm_queries);
> > +   case NVEA_3D_CLASS:
> > case NVF0_3D_CLASS:
> >return ARRAY_SIZE(sm35_hw_sm_queries);
> > case NVE4_3D_CLASS:
> > @@ -2475,15 +2477,14 @@ nvc0_hw_sm_get_program(struct nvc0_screen *screen)
> >prog->code_size = sizeof(gm107_read_hw_sm_counters_code);
> >prog->num_gprs = 14;
> > } else
> > -   if (screen->base.class_3d == NVE4_3D_CLASS ||
> > -   screen->base.class_3d == NVF0_3D_CLASS) {
> > -  if (screen->base.class_3d == NVE4_3D_CLASS) {

Re: [Mesa-dev] [PATCH] nvc0: allow TK1 (NVEA) queries to work

2017-01-15 Thread Samuel Pitoiset 



On 01/14/2017 02:35 AM, Ilia Mirkin wrote:

The NVEA 3D class is numerically larger than the NVF0 3D class. The TK1
chip uses the SM35 ISA and likely has the same hw counters. Allow these
to be used like on all the other supported chips.


This actually needs more testing. Perf counters are pretty different for 
each generation. The kernel used for reading the counters will work 
though, but the configuration has to be double checked.


More comments inline.



Signed-off-by: Ilia Mirkin 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_query.c |  4 ++--
 .../drivers/nouveau/nvc0/nvc0_query_hw_metric.c   |  3 +++
 src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c   | 19 ++-
 3 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
index 8b9e6b6..6bf2285 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
@@ -205,7 +205,7 @@ nvc0_screen_get_driver_query_group_info(struct pipe_screen 
*pscreen,

if (screen->base.drm->version >= 0x01000101) {
   if (screen->compute) {
- if (screen->base.class_3d <= NVF0_3D_CLASS) {
+ if (screen->base.class_3d < GM107_3D_CLASS) {
 count += 2;
  }
   }
@@ -229,7 +229,7 @@ nvc0_screen_get_driver_query_group_info(struct pipe_screen 
*pscreen,
} else
if (id == NVC0_HW_METRIC_QUERY_GROUP) {
   if (screen->compute) {
-  if (screen->base.class_3d <= NVF0_3D_CLASS) {
+  if (screen->base.class_3d < GM107_3D_CLASS) {


Oops, I forgot to expose these groups when I added Maxwell support. 
These groups are only used for AMD_performance_monitor. Presumably this 
ext currently doesn't expose the counters on Maxwell.


We should enable them in a separate patch just before this one (for 
maxwell).


Otherwise, looks good.


 info->name = "Performance metrics";
 info->max_active_queries = 4; /* A metric uses at least 2 queries 
*/
 info->num_queries = nvc0_hw_metric_get_num_queries(screen);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
index 089af61..494f2dd 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
@@ -403,6 +403,7 @@ nvc0_hw_metric_get_queries(struct nvc0_screen *screen)
case GM200_3D_CLASS:
case GM107_3D_CLASS:
   return sm50_hw_metric_queries;
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   return sm35_hw_metric_queries;
case NVE4_3D_CLASS:
@@ -425,6 +426,7 @@ nvc0_hw_metric_get_num_queries(struct nvc0_screen *screen)
case GM200_3D_CLASS:
case GM107_3D_CLASS:
   return ARRAY_SIZE(sm50_hw_metric_queries);
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   return ARRAY_SIZE(sm35_hw_metric_queries);
case NVE4_3D_CLASS:
@@ -684,6 +686,7 @@ nvc0_hw_metric_get_query_result(struct nvc0_context *nvc0,
switch (screen->base.class_3d) {
case GM200_3D_CLASS:
case GM107_3D_CLASS:
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   value = sm35_hw_metric_calc_result(hq, res64);
   break;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
index df5723d..440e5d3 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
@@ -2239,6 +2239,7 @@ nvc0_hw_sm_get_queries(struct nvc0_screen *screen)
   return sm52_hw_sm_queries;
case GM107_3D_CLASS:
   return sm50_hw_sm_queries;
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   return sm35_hw_sm_queries;
case NVE4_3D_CLASS:
@@ -2262,6 +2263,7 @@ nvc0_hw_sm_get_num_queries(struct nvc0_screen *screen)
   return ARRAY_SIZE(sm52_hw_sm_queries);
case GM107_3D_CLASS:
   return ARRAY_SIZE(sm50_hw_sm_queries);
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   return ARRAY_SIZE(sm35_hw_sm_queries);
case NVE4_3D_CLASS:
@@ -2475,15 +2477,14 @@ nvc0_hw_sm_get_program(struct nvc0_screen *screen)
   prog->code_size = sizeof(gm107_read_hw_sm_counters_code);
   prog->num_gprs = 14;
} else
-   if (screen->base.class_3d == NVE4_3D_CLASS ||
-   screen->base.class_3d == NVF0_3D_CLASS) {
-  if (screen->base.class_3d == NVE4_3D_CLASS) {
- prog->code = (uint32_t *)nve4_read_hw_sm_counters_code;
- prog->code_size = sizeof(nve4_read_hw_sm_counters_code);
-  } else {
- prog->code = (uint32_t *)nvf0_read_hw_sm_counters_code;
- prog->code_size = sizeof(nvf0_read_hw_sm_counters_code);
-  }
+   if (screen->base.class_3d > NVE4_3D_CLASS) {
+  prog->code = (uint32_t *)nvf0_read_hw_sm_counters_code;
+  prog->code_size = sizeof(nvf0_read_hw_sm_counters_code);
+  prog->num_gprs = 14;
+   } else
+   if

[Mesa-dev] [PATCH] nvc0: allow TK1 (NVEA) queries to work

2017-01-13 Thread Ilia Mirkin 
The NVEA 3D class is numerically larger than the NVF0 3D class. The TK1
chip uses the SM35 ISA and likely has the same hw counters. Allow these
to be used like on all the other supported chips.

Signed-off-by: Ilia Mirkin 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_query.c |  4 ++--
 .../drivers/nouveau/nvc0/nvc0_query_hw_metric.c   |  3 +++
 src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c   | 19 ++-
 3 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
index 8b9e6b6..6bf2285 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
@@ -205,7 +205,7 @@ nvc0_screen_get_driver_query_group_info(struct pipe_screen 
*pscreen,
 
if (screen->base.drm->version >= 0x01000101) {
   if (screen->compute) {
- if (screen->base.class_3d <= NVF0_3D_CLASS) {
+ if (screen->base.class_3d < GM107_3D_CLASS) {
 count += 2;
  }
   }
@@ -229,7 +229,7 @@ nvc0_screen_get_driver_query_group_info(struct pipe_screen 
*pscreen,
} else
if (id == NVC0_HW_METRIC_QUERY_GROUP) {
   if (screen->compute) {
-  if (screen->base.class_3d <= NVF0_3D_CLASS) {
+  if (screen->base.class_3d < GM107_3D_CLASS) {
 info->name = "Performance metrics";
 info->max_active_queries = 4; /* A metric uses at least 2 queries 
*/
 info->num_queries = nvc0_hw_metric_get_num_queries(screen);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
index 089af61..494f2dd 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c
@@ -403,6 +403,7 @@ nvc0_hw_metric_get_queries(struct nvc0_screen *screen)
case GM200_3D_CLASS:
case GM107_3D_CLASS:
   return sm50_hw_metric_queries;
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   return sm35_hw_metric_queries;
case NVE4_3D_CLASS:
@@ -425,6 +426,7 @@ nvc0_hw_metric_get_num_queries(struct nvc0_screen *screen)
case GM200_3D_CLASS:
case GM107_3D_CLASS:
   return ARRAY_SIZE(sm50_hw_metric_queries);
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   return ARRAY_SIZE(sm35_hw_metric_queries);
case NVE4_3D_CLASS:
@@ -684,6 +686,7 @@ nvc0_hw_metric_get_query_result(struct nvc0_context *nvc0,
switch (screen->base.class_3d) {
case GM200_3D_CLASS:
case GM107_3D_CLASS:
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   value = sm35_hw_metric_calc_result(hq, res64);
   break;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
index df5723d..440e5d3 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_sm.c
@@ -2239,6 +2239,7 @@ nvc0_hw_sm_get_queries(struct nvc0_screen *screen)
   return sm52_hw_sm_queries;
case GM107_3D_CLASS:
   return sm50_hw_sm_queries;
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   return sm35_hw_sm_queries;
case NVE4_3D_CLASS:
@@ -2262,6 +2263,7 @@ nvc0_hw_sm_get_num_queries(struct nvc0_screen *screen)
   return ARRAY_SIZE(sm52_hw_sm_queries);
case GM107_3D_CLASS:
   return ARRAY_SIZE(sm50_hw_sm_queries);
+   case NVEA_3D_CLASS:
case NVF0_3D_CLASS:
   return ARRAY_SIZE(sm35_hw_sm_queries);
case NVE4_3D_CLASS:
@@ -2475,15 +2477,14 @@ nvc0_hw_sm_get_program(struct nvc0_screen *screen)
   prog->code_size = sizeof(gm107_read_hw_sm_counters_code);
   prog->num_gprs = 14;
} else
-   if (screen->base.class_3d == NVE4_3D_CLASS ||
-   screen->base.class_3d == NVF0_3D_CLASS) {
-  if (screen->base.class_3d == NVE4_3D_CLASS) {
- prog->code = (uint32_t *)nve4_read_hw_sm_counters_code;
- prog->code_size = sizeof(nve4_read_hw_sm_counters_code);
-  } else {
- prog->code = (uint32_t *)nvf0_read_hw_sm_counters_code;
- prog->code_size = sizeof(nvf0_read_hw_sm_counters_code);
-  }
+   if (screen->base.class_3d > NVE4_3D_CLASS) {
+  prog->code = (uint32_t *)nvf0_read_hw_sm_counters_code;
+  prog->code_size = sizeof(nvf0_read_hw_sm_counters_code);
+  prog->num_gprs = 14;
+   } else
+   if (screen->base.class_3d == NVE4_3D_CLASS) {
+  prog->code = (uint32_t *)nve4_read_hw_sm_counters_code;
+  prog->code_size = sizeof(nve4_read_hw_sm_counters_code);
   prog->num_gprs = 14;
} else {
   prog->code = (uint32_t *)nvc0_read_hw_sm_counters_code;
-- 
2.10.2

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