Re: [Mesa-dev] [PATCH] radeonsi: fix isolines tess factor writes to control ring

2016-12-06 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek

On Tue, Dec 6, 2016 at 2:45 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> Fixes piglit arb_tessellation_shader/execution/isoline{_no_tcs}.shader_test.
>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/gallium/drivers/radeonsi/si_shader.c | 16 
>  1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
> b/src/gallium/drivers/radeonsi/si_shader.c
> index 44a4dd2..271b8d0 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -2561,24 +2561,32 @@ static void si_write_tess_factors(struct 
> lp_build_tgsi_context *bld_base,
> tess_outer_index = 
> si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
>
> lds_base = tcs_out_current_patch_data_offset;
> lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
>  lp_build_const_int32(gallivm,
>   tess_inner_index * 4), 
> "");
> lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
>  lp_build_const_int32(gallivm,
>   tess_outer_index * 4), 
> "");
>
> -   for (i = 0; i < outer_comps; i++)
> -   out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
> -   for (i = 0; i < inner_comps; i++)
> -   out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, 
> lds_inner);
> +   if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
> +   /* For isolines, the hardware expects tess factors in the
> +* reverse order from what GLSL / TGSI specify.
> +*/
> +   out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
> +   out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
> +   } else {
> +   for (i = 0; i < outer_comps; i++)
> +   out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, 
> lds_outer);
> +   for (i = 0; i < inner_comps; i++)
> +   out[outer_comps+i] = lds_load(bld_base, 
> TGSI_TYPE_SIGNED, i, lds_inner);
> +   }
>
> /* Convert the outputs to vectors for stores. */
> vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
> vec1 = NULL;
>
> if (stride > 4)
> vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
>
> /* Get the buffer. */
> rw_buffers = LLVMGetParam(ctx->main_fn,
> --
> 2.7.4
>
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[Mesa-dev] [PATCH] radeonsi: fix isolines tess factor writes to control ring

2016-12-06 Thread Nicolai Hähnle 
From: Nicolai Hähnle 

Fixes piglit arb_tessellation_shader/execution/isoline{_no_tcs}.shader_test.

Cc: mesa-sta...@lists.freedesktop.org
---
 src/gallium/drivers/radeonsi/si_shader.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 44a4dd2..271b8d0 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2561,24 +2561,32 @@ static void si_write_tess_factors(struct 
lp_build_tgsi_context *bld_base,
tess_outer_index = 
si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
 
lds_base = tcs_out_current_patch_data_offset;
lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
 lp_build_const_int32(gallivm,
  tess_inner_index * 4), 
"");
lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
 lp_build_const_int32(gallivm,
  tess_outer_index * 4), 
"");
 
-   for (i = 0; i < outer_comps; i++)
-   out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
-   for (i = 0; i < inner_comps; i++)
-   out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, 
lds_inner);
+   if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
+   /* For isolines, the hardware expects tess factors in the
+* reverse order from what GLSL / TGSI specify.
+*/
+   out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
+   out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
+   } else {
+   for (i = 0; i < outer_comps; i++)
+   out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, 
lds_outer);
+   for (i = 0; i < inner_comps; i++)
+   out[outer_comps+i] = lds_load(bld_base, 
TGSI_TYPE_SIGNED, i, lds_inner);
+   }
 
/* Convert the outputs to vectors for stores. */
vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
vec1 = NULL;
 
if (stride > 4)
vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
 
/* Get the buffer. */
rw_buffers = LLVMGetParam(ctx->main_fn,
-- 
2.7.4

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