Shader assemblies can be more easily incorporated into debug tools if
they are presented through KHR_debug.
---
src/intel/compiler/brw_fs_generator.cpp | 38 ++++++++++++-----------
src/intel/compiler/brw_vec4_generator.cpp | 22 +++++++------
2 files changed, 33 insertions(+), 27 deletions(-)
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index a8618912cf4..6b80f8433b2 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2463,30 +2463,32 @@ fs_generator::generate_code(const cfg_t *cfg, int
dispatch_width)
brw_compact_instructions(p, start_offset, disasm_info);
int after_size = p->next_insn_offset - start_offset;
+ char *buf;
+ size_t buf_size;
+ FILE * log_fp = open_memstream(&buf, &buf_size);
if (unlikely(debug_flag)) {
- fprintf(stderr, "Native code for %s\n"
- "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d
spills:fills. Promoted %u constants. Compacted %d to %d"
- " bytes (%.0f%%)\n",
- shader_name, dispatch_width, before_size / 16, loop_count,
cfg->cycle_count,
- spill_count, fill_count, promoted_constants, before_size,
after_size,
- 100.0f * (before_size - after_size) / before_size);
-
- dump_assembly(stderr, p->store, disasm_info);
+ fprintf(log_fp, "Native code for %s\n", shader_name);
}
+ fprintf(log_fp, "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
+ "%d:%d spills:fills, Promoted %u constants, "
+ "compacted %d to %d bytes.",
+ _mesa_shader_stage_to_abbrev(stage),
+ dispatch_width, before_size / 16,
+ loop_count, cfg->cycle_count, spill_count,
+ fill_count, promoted_constants, before_size,
+ after_size);
+ if (unlikely(debug_flag)) {
+ dump_assembly(log_fp, p->store, disasm_info);
+ fflush(log_fp);
+ fputs(buf, stderr);
+ }
+ fclose(log_fp);
ralloc_free(disasm_info);
assert(validated);
static GLuint msg_id = 0;
- compiler->shader_debug_log(log_data, &msg_id,
- "%s SIMD%d shader: %d inst, %d loops, %u cycles,
"
- "%d:%d spills:fills, Promoted %u constants, "
- "compacted %d to %d bytes.",
- _mesa_shader_stage_to_abbrev(stage),
- dispatch_width, before_size / 16,
- loop_count, cfg->cycle_count, spill_count,
- fill_count, promoted_constants, before_size,
- after_size);
-
+ compiler->shader_debug_log(log_data, &msg_id, "%s", buf);
+ free(buf);
return start_offset;
}
diff --git a/src/intel/compiler/brw_vec4_generator.cpp
b/src/intel/compiler/brw_vec4_generator.cpp
index 00c89b21daf..f56ec6aa9a1 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -2195,30 +2195,34 @@ generate_code(struct brw_codegen *p,
brw_compact_instructions(p, 0, disasm_info);
int after_size = p->next_insn_offset;
+ char *buf;
+ size_t buf_size;
+ FILE * log_fp = open_memstream(&buf, &buf_size);
if (unlikely(debug_flag)) {
- fprintf(stderr, "Native code for %s %s shader %s:\n",
+ fprintf(log_fp, "Native code for %s %s shader %s:\n",
nir->info.label ? nir->info.label : "unnamed",
_mesa_shader_stage_to_string(nir->info.stage), nir->info.name);
+ }
- fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles.
%d:%d "
+ fprintf(log_fp, "%s vec4 shader: %d instructions. %d loops. %u cycles.
%d:%d "
"spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
stage_abbrev, before_size / 16, loop_count, cfg->cycle_count,
spill_count, fill_count, before_size, after_size,
100.0f * (before_size - after_size) / before_size);
- dump_assembly(stderr, p->store, disasm_info);
+ if (unlikely(debug_flag)) {
+ dump_assembly(log_fp, p->store, disasm_info);
+ fflush(log_fp);
+ fputs(buf, stderr);
}
ralloc_free(disasm_info);
assert(validated);
+ fclose(log_fp);
static GLuint msg_id = 0;
compiler->shader_debug_log(log_data, &msg_id,
- "%s vec4 shader: %d inst, %d loops, %u cycles, "
- "%d:%d spills:fills, compacted %d to %d bytes.",
- stage_abbrev, before_size / 16,
- loop_count, cfg->cycle_count, spill_count,
- fill_count, before_size, after_size);
-
+ "%s", buf);
+ free(buf);
}
extern "C" const unsigned *
--
2.19.2
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