From: Marek Olšák <marek.ol...@amd.com>
---
src/amd/common/ac_gpu_info.c | 2 ++
src/amd/common/ac_gpu_info.h | 1 +
src/gallium/drivers/radeonsi/si_get.c | 16 +++-------------
.../winsys/radeon/drm/radeon_drm_winsys.c | 5 +++++
4 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 5c1bab2e9a0..aa18c97826c 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -320,20 +320,21 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->htile_cmask_support_1d_tiling = true;
info->si_TA_CS_BC_BASE_ADDR_allowed = true;
info->has_bo_metadata = true;
info->has_gpu_reset_status_query = true;
info->has_gpu_reset_counter_query = false;
info->has_eqaa_surface_allocator = true;
info->has_format_bc1_through_bc7 = true;
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
info->drm_minor >= 2;
+ info->has_indirect_compute_dispatch = true;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
if (info->family == CHIP_KAVERI)
info->num_render_backends = 2;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
if (!info->clock_crystal_freq) {
fprintf(stderr, "amdgpu: clock crystal frequency is 0,
timestamps will be wrong\n");
info->clock_crystal_freq = 1;
@@ -476,20 +477,21 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" has_local_buffers = %u\n", info->has_local_buffers);
printf(" kernel_flushes_hdp_before_ib = %u\n",
info->kernel_flushes_hdp_before_ib);
printf(" htile_cmask_support_1d_tiling = %u\n",
info->htile_cmask_support_1d_tiling);
printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n",
info->si_TA_CS_BC_BASE_ADDR_allowed);
printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
printf(" has_gpu_reset_status_query = %u\n",
info->has_gpu_reset_status_query);
printf(" has_gpu_reset_counter_query = %u\n",
info->has_gpu_reset_counter_query);
printf(" has_eqaa_surface_allocator = %u\n",
info->has_eqaa_surface_allocator);
printf(" has_format_bc1_through_bc7 = %u\n",
info->has_format_bc1_through_bc7);
printf(" kernel_flushes_tc_l2_after_ib = %u\n",
info->kernel_flushes_tc_l2_after_ib);
+ printf(" has_indirect_compute_dispatch = %u\n",
info->has_indirect_compute_dispatch);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
printf(" num_good_compute_units = %i\n",
info->num_good_compute_units);
printf(" max_se = %i\n", info->max_se);
printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
printf("Render backend info:\n");
printf(" num_render_backends = %i\n", info->num_render_backends);
printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 5e404714db6..d5d10c60102 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -98,20 +98,21 @@ struct radeon_info {
bool has_local_buffers;
bool kernel_flushes_hdp_before_ib;
bool htile_cmask_support_1d_tiling;
bool si_TA_CS_BC_BASE_ADDR_allowed;
bool has_bo_metadata;
bool has_gpu_reset_status_query;
bool has_gpu_reset_counter_query;
bool has_eqaa_surface_allocator;
bool has_format_bc1_through_bc7;
bool kernel_flushes_tc_l2_after_ib;
+ bool has_indirect_compute_dispatch;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
uint32_t max_shader_clock;
uint32_t num_good_compute_units;
uint32_t max_se; /* shader engines */
uint32_t max_sh_per_se; /* shader arrays per shader
engine */
/* Render backends (color + depth blocks). */
uint32_t r300_num_gb_pipes;
diff --git a/src/gallium/drivers/radeonsi/si_get.c
b/src/gallium/drivers/radeonsi/si_get.c
index cd3e63c73d7..0e7d28e334c 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -76,30 +76,20 @@ const char *si_get_family_name(const struct si_screen
*sscreen)
case CHIP_POLARIS11: return "AMD POLARIS11";
case CHIP_POLARIS12: return "AMD POLARIS12";
case CHIP_VEGAM: return "AMD VEGAM";
case CHIP_VEGA10: return "AMD VEGA10";
case CHIP_VEGA12: return "AMD VEGA12";
case CHIP_RAVEN: return "AMD RAVEN";
default: return "AMD unknown";
}
}
-static bool si_have_tgsi_compute(struct si_screen *sscreen)
-{
- /* Old kernels disallowed some register writes for SI
- * that are used for indirect dispatches. */
- return (sscreen->info.chip_class >= CIK ||
- sscreen->info.drm_major == 3 ||
- (sscreen->info.drm_major == 2 &&
- sscreen->info.drm_minor >= 45));
-}
-
static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
{
struct si_screen *sscreen = (struct si_screen *)pscreen;
switch (param) {
/* Supported features (boolean caps). */
case PIPE_CAP_ACCELERATED:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
@@ -218,21 +208,21 @@ static int si_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
case PIPE_CAP_MAX_VERTEX_STREAMS:
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 4;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
- if (si_have_tgsi_compute(sscreen))
+ if (sscreen->info.has_indirect_compute_dispatch)
return 450;
return 420;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->info.max_alloc_size, INT_MAX);
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
/* SI doesn't support unaligned loads.
@@ -287,21 +277,21 @@ static int si_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_FENCE_SIGNAL:
return sscreen->info.has_syncobj;
case PIPE_CAP_CONSTBUF0_FLAGS:
return SI_RESOURCE_FLAG_32BIT;
case PIPE_CAP_NATIVE_FENCE_FD:
return sscreen->info.has_fence_to_handle;
case PIPE_CAP_QUERY_BUFFER_OBJECT:
- return si_have_tgsi_compute(sscreen);
+ return sscreen->info.has_indirect_compute_dispatch;
case PIPE_CAP_DRAW_PARAMETERS:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
return sscreen->has_draw_indirect_multi;
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
return 30;
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
@@ -401,21 +391,21 @@ static int si_get_shader_param(struct pipe_screen*
pscreen,
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
break;
case PIPE_SHADER_COMPUTE:
switch (param) {
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
int ir = 1 << PIPE_SHADER_IR_NATIVE;
- if (si_have_tgsi_compute(sscreen))
+ if (sscreen->info.has_indirect_compute_dispatch)
ir |= 1 << PIPE_SHADER_IR_TGSI;
return ir;
}
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
uint64_t max_const_buffer_size;
pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
&max_const_buffer_size);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 2f79d6691c3..6edec7b6e71 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -536,20 +536,25 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
/* HTILE is broken with 1D tiling on old kernels and CIK. */
ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
ws->info.drm_minor >= 38;
ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
ws->info.has_bo_metadata = false;
ws->info.has_gpu_reset_status_query = false;
ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
ws->info.has_eqaa_surface_allocator = false;
ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
ws->info.kernel_flushes_tc_l2_after_ib = true;
+ /* Old kernels disallowed register writes via COPY_DATA
+ * that are used for indirect compute dispatches. */
+ ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
+ (ws->info.chip_class == SI &&
+ ws->info.drm_minor >= 45);
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") !=
NULL;
return true;
}
static void radeon_winsys_destroy(struct radeon_winsys *rws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
--
2.17.0
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