Re: [Mesa-dev] [PATCH 1/2] radv: only account for tile_swizzle for color surfaces with DCC

2019-08-02 Thread Bas Nieuwenhuizen
r-b for both

On Thu, Aug 1, 2019 at 3:41 PM Samuel Pitoiset
 wrote:
>
> It's 0 for depth surfaces with TC compat HTILE enabled.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_image.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index f3237dd5985..221b554e73e 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -483,6 +483,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
> meta_va = gpu_address + image->dcc_offset;
> if (chip_class <= GFX8)
> meta_va += base_level_info->dcc_offset;
> +
> +   meta_va |= (uint32_t)plane->surface.tile_swizzle << 8;
> } else if (!is_storage_image &&
>radv_image_is_tc_compat_htile(image)) {
> meta_va = gpu_address + image->htile_offset;
> @@ -490,10 +492,8 @@ si_set_mutable_tex_desc_fields(struct radv_device 
> *device,
>
> if (meta_va) {
> state[6] |= S_008F28_COMPRESSION_EN(1);
> -   if (chip_class <= GFX9) {
> +   if (chip_class <= GFX9)
> state[7] = meta_va >> 8;
> -   state[7] |= plane->surface.tile_swizzle;
> -   }
> }
> }
>
> --
> 2.22.0
>
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[Mesa-dev] [PATCH 1/2] radv: only account for tile_swizzle for color surfaces with DCC

2019-08-01 Thread Samuel Pitoiset
It's 0 for depth surfaces with TC compat HTILE enabled.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_image.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index f3237dd5985..221b554e73e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -483,6 +483,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= GFX8)
meta_va += base_level_info->dcc_offset;
+
+   meta_va |= (uint32_t)plane->surface.tile_swizzle << 8;
} else if (!is_storage_image &&
   radv_image_is_tc_compat_htile(image)) {
meta_va = gpu_address + image->htile_offset;
@@ -490,10 +492,8 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
 
if (meta_va) {
state[6] |= S_008F28_COMPRESSION_EN(1);
-   if (chip_class <= GFX9) {
+   if (chip_class <= GFX9)
state[7] = meta_va >> 8;
-   state[7] |= plane->surface.tile_swizzle;
-   }
}
}
 
-- 
2.22.0

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