Re: [Mesa-dev] [PATCH 1/5] radeonsi: remove fast color clear for single-sample buffers

[Marek Olšák]

Yes.

Marek

On Fri, Mar 30, 2018, 4:47 AM Dieter Nützel  wrote:

> Hello Marek,
>
> 2-3 landed.
> Is #1 dead after my findings? ;-)
>
> Dieter
>
> Am 11.03.2018 19:11, schrieb Marek Olšák:
> > From: Marek Olšák 
> >
> > This should improve the score for the GpuTest Triangle benchmark.
> > Vulkan doesn't use this either.
> > ---
> >  src/gallium/drivers/radeon/r600_pipe_common.h |  1 -
> >  src/gallium/drivers/radeon/r600_texture.c | 11 +---
> >  src/gallium/drivers/radeonsi/si_clear.c   | 37
> > ++-
> >  src/gallium/drivers/radeonsi/si_state.c   |  6 -
> >  4 files changed, 3 insertions(+), 52 deletions(-)
> >
> > diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
> > b/src/gallium/drivers/radeon/r600_pipe_common.h
> > index 7941903..9701757 100644
> > --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> > +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> > @@ -209,21 +209,20 @@ struct r600_cmask_info {
> >  struct r600_texture {
> >   struct r600_resourceresource;
> >
> >   struct radeon_surf  surface;
> >   uint64_tsize;
> >   struct r600_texture *flushed_depth_texture;
> >
> >   /* Colorbuffer compression and fast clear. */
> >   struct r600_fmask_info  fmask;
> >   struct r600_cmask_info  cmask;
> > - struct r600_resource*cmask_buffer;
> >   uint64_tdcc_offset; /* 0 = disabled */
> >   unsignedcb_color_info; /* fast clear
> enable bit */
> >   unsignedcolor_clear_value[2];
> >   unsigned
> last_msaa_resolve_target_micro_mode;
> >   unsignednum_level0_transfers;
> >
> >   /* Depth buffer compression and fast clear. */
> >   uint64_thtile_offset;
> >   float   depth_clear_value;
> >   uint16_tdirty_level_mask; /* each bit says
> if that mipmap is
> > compressed */
> > diff --git a/src/gallium/drivers/radeon/r600_texture.c
> > b/src/gallium/drivers/radeon/r600_texture.c
> > index 125e7ef..03bc955 100644
> > --- a/src/gallium/drivers/radeon/r600_texture.c
> > +++ b/src/gallium/drivers/radeon/r600_texture.c
> > @@ -405,26 +405,22 @@ void si_texture_discard_cmask(struct si_screen
> > *sscreen,
> >  {
> >   if (!rtex->cmask.size)
> >   return;
> >
> >   assert(rtex->resource.b.b.nr_samples <= 1);
> >
> >   /* Disable CMASK. */
> >   memset(>cmask, 0, sizeof(rtex->cmask));
> >   rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
> >   rtex->dirty_level_mask = 0;
> > -
> >   rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
> >
> > - if (rtex->cmask_buffer != >resource)
> > - r600_resource_reference(>cmask_buffer, NULL);
> > -
> >   /* Notify all contexts about the change. */
> >   p_atomic_inc(>dirty_tex_counter);
> >   p_atomic_inc(>compressed_colortex_counter);
> >  }
> >
> >  static bool r600_can_disable_dcc(struct r600_texture *rtex)
> >  {
> >   /* We can't disable DCC if it can be written by another process. */
> >   return rtex->dcc_offset &&
> >  (!rtex->resource.b.is_shared ||
> > @@ -813,24 +809,20 @@ static boolean r600_texture_get_handle(struct
> > pipe_screen* screen,
> > slice_size, whandle);
> >  }
> >
> >  static void r600_texture_destroy(struct pipe_screen *screen,
> >struct pipe_resource *ptex)
> >  {
> >   struct r600_texture *rtex = (struct r600_texture*)ptex;
> >   struct r600_resource *resource = >resource;
> >
> >   r600_texture_reference(>flushed_depth_texture, NULL);
> > -
> > - if (rtex->cmask_buffer != >resource) {
> > - r600_resource_reference(>cmask_buffer, NULL);
> > - }
> >   pb_reference(>buf, NULL);
> >   r600_resource_reference(>dcc_separate_buffer, NULL);
> >   r600_resource_reference(>last_dcc_separate_buffer, NULL);
> >   FREE(rtex);
> >  }
> >
> >  static const struct u_resource_vtbl r600_texture_vtbl;
> >
> >  /* The number of samples can be specified independently of the
> > texture. */
> >  void si_texture_get_fmask_info(struct si_screen *sscreen,
> > @@ -1262,21 +1254,20 @@ r600_texture_create_object(struct pipe_screen
> > *screen,
> >   rtex->db_compatible = true;
> >
> >   if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
> >   r600_texture_allocate_htile(sscreen, rtex);
> >   }
> >   } else {
> >   if (base->nr_samples > 1) {
> >   if (!buf) {
> >   r600_texture_allocate_fmask(sscreen, rtex);
> >   r600_texture_allocate_cmask(sscreen, rtex);
> > -   

Re: [Mesa-dev] [PATCH 1/5] radeonsi: remove fast color clear for single-sample buffers

[Dieter Nützel]

Hello Marek,

2-3 landed.
Is #1 dead after my findings? ;-)

Dieter

Am 11.03.2018 19:11, schrieb Marek Olšák:

From: Marek Olšák 

This should improve the score for the GpuTest Triangle benchmark.
Vulkan doesn't use this either.
---
 src/gallium/drivers/radeon/r600_pipe_common.h |  1 -
 src/gallium/drivers/radeon/r600_texture.c | 11 +---
 src/gallium/drivers/radeonsi/si_clear.c   | 37 
++-

 src/gallium/drivers/radeonsi/si_state.c   |  6 -
 4 files changed, 3 insertions(+), 52 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7941903..9701757 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -209,21 +209,20 @@ struct r600_cmask_info {
 struct r600_texture {
struct r600_resourceresource;

struct radeon_surf  surface;
uint64_tsize;
struct r600_texture *flushed_depth_texture;

/* Colorbuffer compression and fast clear. */
struct r600_fmask_info  fmask;
struct r600_cmask_info  cmask;
-   struct r600_resource*cmask_buffer;
uint64_tdcc_offset; /* 0 = disabled */
unsignedcb_color_info; /* fast clear enable bit 
*/
unsignedcolor_clear_value[2];
unsignedlast_msaa_resolve_target_micro_mode;
unsignednum_level0_transfers;

/* Depth buffer compression and fast clear. */
uint64_thtile_offset;
float   depth_clear_value;
 	uint16_t			dirty_level_mask; /* each bit says if that mipmap is 
compressed */

diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 125e7ef..03bc955 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -405,26 +405,22 @@ void si_texture_discard_cmask(struct si_screen 
*sscreen,

 {
if (!rtex->cmask.size)
return;

assert(rtex->resource.b.b.nr_samples <= 1);

/* Disable CMASK. */
memset(>cmask, 0, sizeof(rtex->cmask));
rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
rtex->dirty_level_mask = 0;
-
rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);

-   if (rtex->cmask_buffer != >resource)
-   r600_resource_reference(>cmask_buffer, NULL);
-
/* Notify all contexts about the change. */
p_atomic_inc(>dirty_tex_counter);
p_atomic_inc(>compressed_colortex_counter);
 }

 static bool r600_can_disable_dcc(struct r600_texture *rtex)
 {
/* We can't disable DCC if it can be written by another process. */
return rtex->dcc_offset &&
   (!rtex->resource.b.is_shared ||
@@ -813,24 +809,20 @@ static boolean r600_texture_get_handle(struct
pipe_screen* screen,
  slice_size, whandle);
 }

 static void r600_texture_destroy(struct pipe_screen *screen,
 struct pipe_resource *ptex)
 {
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = >resource;

r600_texture_reference(>flushed_depth_texture, NULL);
-
-   if (rtex->cmask_buffer != >resource) {
-   r600_resource_reference(>cmask_buffer, NULL);
-   }
pb_reference(>buf, NULL);
r600_resource_reference(>dcc_separate_buffer, NULL);
r600_resource_reference(>last_dcc_separate_buffer, NULL);
FREE(rtex);
 }

 static const struct u_resource_vtbl r600_texture_vtbl;

 /* The number of samples can be specified independently of the 
texture. */

 void si_texture_get_fmask_info(struct si_screen *sscreen,
@@ -1262,21 +1254,20 @@ r600_texture_create_object(struct pipe_screen 
*screen,

rtex->db_compatible = true;

if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
r600_texture_allocate_htile(sscreen, rtex);
}
} else {
if (base->nr_samples > 1) {
if (!buf) {
r600_texture_allocate_fmask(sscreen, rtex);
r600_texture_allocate_cmask(sscreen, rtex);
-   rtex->cmask_buffer = >resource;
}
if (!rtex->fmask.size || !rtex->cmask.size) {
FREE(rtex);
return NULL;
}
}

/* Shared textures must always set up DCC here.
 * If it's not present, it will be disabled by
 * 

Re: [Mesa-dev] [PATCH 1/5] radeonsi: remove fast color clear for single-sample buffers

[Dieter Nützel]

Am 15.03.2018 07:56, schrieb Dieter Nützel:

For the series (1-3)

Tested-by: Dieter Nützel 

Are these numbers OK?

Triangle,Radeon RX 580 Series (POLARIS10 / DRM 3.25.0 /
4.16.0-rc1-1.g7262353-default+, LLVM 7.0.0),3.1 Mesa 18.1.0-devel
(git-a8cc051d2e),1920,1080,YES,Off,5240,6,0,314471

Or should I retest without this series?


WAIT!!!

Marek I've retested back and forth with this series removed and 'GpuTest 
Triangle' and most other stuff of 'GpuTest' is ~10% _slower_ with _this_ 
series applied!


I've even booted with 'nopti, nospectre_v2' 'cause my 'old' X3470 
Nehalem has NO 'PCID' and due to this is much regressed (10-20% with 
height CS count, kernel compilation down from 7:30 to 8:30) with the 
mitigation.


With mitigation:
My best run
_with_ this series was:   318668
_without_ this series was:  350645

'nopti, nospectre_v2'
_with_ this series was:   319327
_without_ this series was:  354074

System specs:
Xeon X3470 Nehalem, 2.93 GHz, 3.6 GHz max turbo, 4c/8t, 24 GB, RX580 8 
GB

cpupower frequency-set -g performance

  current CPU frequency: 2.93 GHz (asserted by call to hardware)
  boost state support:
Supported: yes
Active: yes
3200 MHz max turbo 4 active cores
3200 MHz max turbo 3 active cores
3467 MHz max turbo 2 active cores
3600 MHz max turbo 1 active cores

Hope this helps.

Dieter


Am 11.03.2018 19:11, schrieb Marek Olšák:

From: Marek Olšák 

This should improve the score for the GpuTest Triangle benchmark.
Vulkan doesn't use this either.
---
 src/gallium/drivers/radeon/r600_pipe_common.h |  1 -
 src/gallium/drivers/radeon/r600_texture.c | 11 +---
 src/gallium/drivers/radeonsi/si_clear.c   | 37 
++-

 src/gallium/drivers/radeonsi/si_state.c   |  6 -
 4 files changed, 3 insertions(+), 52 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7941903..9701757 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -209,21 +209,20 @@ struct r600_cmask_info {
 struct r600_texture {
struct r600_resourceresource;

struct radeon_surf  surface;
uint64_tsize;
struct r600_texture *flushed_depth_texture;

/* Colorbuffer compression and fast clear. */
struct r600_fmask_info  fmask;
struct r600_cmask_info  cmask;
-   struct r600_resource*cmask_buffer;
uint64_tdcc_offset; /* 0 = disabled */
unsignedcb_color_info; /* fast clear enable bit 
*/
unsignedcolor_clear_value[2];
unsignedlast_msaa_resolve_target_micro_mode;
unsignednum_level0_transfers;

/* Depth buffer compression and fast clear. */
uint64_thtile_offset;
float   depth_clear_value;
 	uint16_t			dirty_level_mask; /* each bit says if that mipmap is 
compressed */

diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 125e7ef..03bc955 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -405,26 +405,22 @@ void si_texture_discard_cmask(struct si_screen 
*sscreen,

 {
if (!rtex->cmask.size)
return;

assert(rtex->resource.b.b.nr_samples <= 1);

/* Disable CMASK. */
memset(>cmask, 0, sizeof(rtex->cmask));
rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
rtex->dirty_level_mask = 0;
-
rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);

-   if (rtex->cmask_buffer != >resource)
-   r600_resource_reference(>cmask_buffer, NULL);
-
/* Notify all contexts about the change. */
p_atomic_inc(>dirty_tex_counter);
p_atomic_inc(>compressed_colortex_counter);
 }

 static bool r600_can_disable_dcc(struct r600_texture *rtex)
 {
/* We can't disable DCC if it can be written by another process. */
return rtex->dcc_offset &&
   (!rtex->resource.b.is_shared ||
@@ -813,24 +809,20 @@ static boolean r600_texture_get_handle(struct
pipe_screen* screen,
  slice_size, whandle);
 }

 static void r600_texture_destroy(struct pipe_screen *screen,
 struct pipe_resource *ptex)
 {
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = >resource;

r600_texture_reference(>flushed_depth_texture, NULL);
-
-   if (rtex->cmask_buffer != >resource) {
-   r600_resource_reference(>cmask_buffer, NULL);
-   }
pb_reference(>buf, NULL);

Re: [Mesa-dev] [PATCH 1/5] radeonsi: remove fast color clear for single-sample buffers

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 03/11/2018 07:11 PM, Marek Olšák wrote:

From: Marek Olšák 

This should improve the score for the GpuTest Triangle benchmark.
Vulkan doesn't use this either.
---
  src/gallium/drivers/radeon/r600_pipe_common.h |  1 -
  src/gallium/drivers/radeon/r600_texture.c | 11 +---
  src/gallium/drivers/radeonsi/si_clear.c   | 37 ++-
  src/gallium/drivers/radeonsi/si_state.c   |  6 -
  4 files changed, 3 insertions(+), 52 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7941903..9701757 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -209,21 +209,20 @@ struct r600_cmask_info {
  struct r600_texture {
struct r600_resourceresource;
  
  	struct radeon_surf		surface;

uint64_tsize;
struct r600_texture *flushed_depth_texture;
  
  	/* Colorbuffer compression and fast clear. */

struct r600_fmask_info  fmask;
struct r600_cmask_info  cmask;
-   struct r600_resource*cmask_buffer;
uint64_tdcc_offset; /* 0 = disabled */
unsignedcb_color_info; /* fast clear enable bit 
*/
unsignedcolor_clear_value[2];
unsignedlast_msaa_resolve_target_micro_mode;
unsignednum_level0_transfers;
  
  	/* Depth buffer compression and fast clear. */

uint64_thtile_offset;
float   depth_clear_value;
uint16_tdirty_level_mask; /* each bit says if 
that mipmap is compressed */
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 125e7ef..03bc955 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -405,26 +405,22 @@ void si_texture_discard_cmask(struct si_screen *sscreen,
  {
if (!rtex->cmask.size)
return;
  
  	assert(rtex->resource.b.b.nr_samples <= 1);
  
  	/* Disable CMASK. */

memset(>cmask, 0, sizeof(rtex->cmask));
rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
rtex->dirty_level_mask = 0;
-
rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
  
-	if (rtex->cmask_buffer != >resource)

-   r600_resource_reference(>cmask_buffer, NULL);
-
/* Notify all contexts about the change. */
p_atomic_inc(>dirty_tex_counter);
p_atomic_inc(>compressed_colortex_counter);
  }
  
  static bool r600_can_disable_dcc(struct r600_texture *rtex)

  {
/* We can't disable DCC if it can be written by another process. */
return rtex->dcc_offset &&
   (!rtex->resource.b.is_shared ||
@@ -813,24 +809,20 @@ static boolean r600_texture_get_handle(struct 
pipe_screen* screen,
  slice_size, whandle);
  }
  
  static void r600_texture_destroy(struct pipe_screen *screen,

 struct pipe_resource *ptex)
  {
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = >resource;
  
  	r600_texture_reference(>flushed_depth_texture, NULL);

-
-   if (rtex->cmask_buffer != >resource) {
-   r600_resource_reference(>cmask_buffer, NULL);
-   }
pb_reference(>buf, NULL);
r600_resource_reference(>dcc_separate_buffer, NULL);
r600_resource_reference(>last_dcc_separate_buffer, NULL);
FREE(rtex);
  }
  
  static const struct u_resource_vtbl r600_texture_vtbl;
  
  /* The number of samples can be specified independently of the texture. */

  void si_texture_get_fmask_info(struct si_screen *sscreen,
@@ -1262,21 +1254,20 @@ r600_texture_create_object(struct pipe_screen *screen,
rtex->db_compatible = true;
  
  			if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))

r600_texture_allocate_htile(sscreen, rtex);
}
} else {
if (base->nr_samples > 1) {
if (!buf) {
r600_texture_allocate_fmask(sscreen, rtex);
r600_texture_allocate_cmask(sscreen, rtex);
-   rtex->cmask_buffer = >resource;
}
if (!rtex->fmask.size || !rtex->cmask.size) {
FREE(rtex);
return NULL;
}
}
  
  		/* Shared textures must always set up DCC here.

 * If it's not present, it will be disabled by
 * apply_opaque_metadata later.

Re: [Mesa-dev] [PATCH 1/5] radeonsi: remove fast color clear for single-sample buffers

[Dieter Nützel]

Wow,

if we compare Polaris 20 with Ryzen 3 2200G, AMD Vega 8 on Phoronix
https://www.phoronix.com/scan.php?page=article=ryzen3-2200g-vega8=3

Even TessMark against NVIDIA GeForce GTX 1080:
http://openbenchmarking.org/prospect/1606047-HA-PASCALGRA41/946288150b2d292b67300c7fea4e9a47f6bb3f4c

=> 16270 poinst

RX 580: 42083 !!! ;-)

it looks really nice.

Dieter

Am 15.03.2018 07:56, schrieb Dieter Nützel:

For the series (1-3)

Tested-by: Dieter Nützel 

Are these numbers OK?

Triangle,Radeon RX 580 Series (POLARIS10 / DRM 3.25.0 /
4.16.0-rc1-1.g7262353-default+, LLVM 7.0.0),3.1 Mesa 18.1.0-devel
(git-a8cc051d2e),1920,1080,YES,Off,5240,6,0,314471

Or should I retest without this series?

Dieter

Am 11.03.2018 19:11, schrieb Marek Olšák:

From: Marek Olšák 

This should improve the score for the GpuTest Triangle benchmark.
Vulkan doesn't use this either.
---
 src/gallium/drivers/radeon/r600_pipe_common.h |  1 -
 src/gallium/drivers/radeon/r600_texture.c | 11 +---
 src/gallium/drivers/radeonsi/si_clear.c   | 37 
++-

 src/gallium/drivers/radeonsi/si_state.c   |  6 -
 4 files changed, 3 insertions(+), 52 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7941903..9701757 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -209,21 +209,20 @@ struct r600_cmask_info {
 struct r600_texture {
struct r600_resourceresource;

struct radeon_surf  surface;
uint64_tsize;
struct r600_texture *flushed_depth_texture;

/* Colorbuffer compression and fast clear. */
struct r600_fmask_info  fmask;
struct r600_cmask_info  cmask;
-   struct r600_resource*cmask_buffer;
uint64_tdcc_offset; /* 0 = disabled */
unsignedcb_color_info; /* fast clear enable bit 
*/
unsignedcolor_clear_value[2];
unsignedlast_msaa_resolve_target_micro_mode;
unsignednum_level0_transfers;

/* Depth buffer compression and fast clear. */
uint64_thtile_offset;
float   depth_clear_value;
 	uint16_t			dirty_level_mask; /* each bit says if that mipmap is 
compressed */

diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 125e7ef..03bc955 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -405,26 +405,22 @@ void si_texture_discard_cmask(struct si_screen 
*sscreen,

 {
if (!rtex->cmask.size)
return;

assert(rtex->resource.b.b.nr_samples <= 1);

/* Disable CMASK. */
memset(>cmask, 0, sizeof(rtex->cmask));
rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
rtex->dirty_level_mask = 0;
-
rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);

-   if (rtex->cmask_buffer != >resource)
-   r600_resource_reference(>cmask_buffer, NULL);
-
/* Notify all contexts about the change. */
p_atomic_inc(>dirty_tex_counter);
p_atomic_inc(>compressed_colortex_counter);
 }

 static bool r600_can_disable_dcc(struct r600_texture *rtex)
 {
/* We can't disable DCC if it can be written by another process. */
return rtex->dcc_offset &&
   (!rtex->resource.b.is_shared ||
@@ -813,24 +809,20 @@ static boolean r600_texture_get_handle(struct
pipe_screen* screen,
  slice_size, whandle);
 }

 static void r600_texture_destroy(struct pipe_screen *screen,
 struct pipe_resource *ptex)
 {
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = >resource;

r600_texture_reference(>flushed_depth_texture, NULL);
-
-   if (rtex->cmask_buffer != >resource) {
-   r600_resource_reference(>cmask_buffer, NULL);
-   }
pb_reference(>buf, NULL);
r600_resource_reference(>dcc_separate_buffer, NULL);
r600_resource_reference(>last_dcc_separate_buffer, NULL);
FREE(rtex);
 }

 static const struct u_resource_vtbl r600_texture_vtbl;

 /* The number of samples can be specified independently of the 
texture. */

 void si_texture_get_fmask_info(struct si_screen *sscreen,
@@ -1262,21 +1254,20 @@ r600_texture_create_object(struct pipe_screen 
*screen,

rtex->db_compatible = true;

if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
r600_texture_allocate_htile(sscreen, rtex);
}
} else {
if 

Re: [Mesa-dev] [PATCH 1/5] radeonsi: remove fast color clear for single-sample buffers

[Dieter Nützel]

For the series (1-3)

Tested-by: Dieter Nützel 

Are these numbers OK?

Triangle,Radeon RX 580 Series (POLARIS10 / DRM 3.25.0 / 
4.16.0-rc1-1.g7262353-default+, LLVM 7.0.0),3.1 Mesa 18.1.0-devel 
(git-a8cc051d2e),1920,1080,YES,Off,5240,6,0,314471


Or should I retest without this series?

Dieter

Am 11.03.2018 19:11, schrieb Marek Olšák:

From: Marek Olšák 

This should improve the score for the GpuTest Triangle benchmark.
Vulkan doesn't use this either.
---
 src/gallium/drivers/radeon/r600_pipe_common.h |  1 -
 src/gallium/drivers/radeon/r600_texture.c | 11 +---
 src/gallium/drivers/radeonsi/si_clear.c   | 37 
++-

 src/gallium/drivers/radeonsi/si_state.c   |  6 -
 4 files changed, 3 insertions(+), 52 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7941903..9701757 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -209,21 +209,20 @@ struct r600_cmask_info {
 struct r600_texture {
struct r600_resourceresource;

struct radeon_surf  surface;
uint64_tsize;
struct r600_texture *flushed_depth_texture;

/* Colorbuffer compression and fast clear. */
struct r600_fmask_info  fmask;
struct r600_cmask_info  cmask;
-   struct r600_resource*cmask_buffer;
uint64_tdcc_offset; /* 0 = disabled */
unsignedcb_color_info; /* fast clear enable bit 
*/
unsignedcolor_clear_value[2];
unsignedlast_msaa_resolve_target_micro_mode;
unsignednum_level0_transfers;

/* Depth buffer compression and fast clear. */
uint64_thtile_offset;
float   depth_clear_value;
 	uint16_t			dirty_level_mask; /* each bit says if that mipmap is 
compressed */

diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 125e7ef..03bc955 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -405,26 +405,22 @@ void si_texture_discard_cmask(struct si_screen 
*sscreen,

 {
if (!rtex->cmask.size)
return;

assert(rtex->resource.b.b.nr_samples <= 1);

/* Disable CMASK. */
memset(>cmask, 0, sizeof(rtex->cmask));
rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
rtex->dirty_level_mask = 0;
-
rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);

-   if (rtex->cmask_buffer != >resource)
-   r600_resource_reference(>cmask_buffer, NULL);
-
/* Notify all contexts about the change. */
p_atomic_inc(>dirty_tex_counter);
p_atomic_inc(>compressed_colortex_counter);
 }

 static bool r600_can_disable_dcc(struct r600_texture *rtex)
 {
/* We can't disable DCC if it can be written by another process. */
return rtex->dcc_offset &&
   (!rtex->resource.b.is_shared ||
@@ -813,24 +809,20 @@ static boolean r600_texture_get_handle(struct
pipe_screen* screen,
  slice_size, whandle);
 }

 static void r600_texture_destroy(struct pipe_screen *screen,
 struct pipe_resource *ptex)
 {
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = >resource;

r600_texture_reference(>flushed_depth_texture, NULL);
-
-   if (rtex->cmask_buffer != >resource) {
-   r600_resource_reference(>cmask_buffer, NULL);
-   }
pb_reference(>buf, NULL);
r600_resource_reference(>dcc_separate_buffer, NULL);
r600_resource_reference(>last_dcc_separate_buffer, NULL);
FREE(rtex);
 }

 static const struct u_resource_vtbl r600_texture_vtbl;

 /* The number of samples can be specified independently of the 
texture. */

 void si_texture_get_fmask_info(struct si_screen *sscreen,
@@ -1262,21 +1254,20 @@ r600_texture_create_object(struct pipe_screen 
*screen,

rtex->db_compatible = true;

if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
r600_texture_allocate_htile(sscreen, rtex);
}
} else {
if (base->nr_samples > 1) {
if (!buf) {
r600_texture_allocate_fmask(sscreen, rtex);
r600_texture_allocate_cmask(sscreen, rtex);
-   rtex->cmask_buffer = >resource;
}
if (!rtex->fmask.size || !rtex->cmask.size) {

[Mesa-dev] [PATCH 1/5] radeonsi: remove fast color clear for single-sample buffers

[Marek Olšák]

From: Marek Olšák 

This should improve the score for the GpuTest Triangle benchmark.
Vulkan doesn't use this either.
---
 src/gallium/drivers/radeon/r600_pipe_common.h |  1 -
 src/gallium/drivers/radeon/r600_texture.c | 11 +---
 src/gallium/drivers/radeonsi/si_clear.c   | 37 ++-
 src/gallium/drivers/radeonsi/si_state.c   |  6 -
 4 files changed, 3 insertions(+), 52 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7941903..9701757 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -209,21 +209,20 @@ struct r600_cmask_info {
 struct r600_texture {
struct r600_resourceresource;
 
struct radeon_surf  surface;
uint64_tsize;
struct r600_texture *flushed_depth_texture;
 
/* Colorbuffer compression and fast clear. */
struct r600_fmask_info  fmask;
struct r600_cmask_info  cmask;
-   struct r600_resource*cmask_buffer;
uint64_tdcc_offset; /* 0 = disabled */
unsignedcb_color_info; /* fast clear enable bit 
*/
unsignedcolor_clear_value[2];
unsignedlast_msaa_resolve_target_micro_mode;
unsignednum_level0_transfers;
 
/* Depth buffer compression and fast clear. */
uint64_thtile_offset;
float   depth_clear_value;
uint16_tdirty_level_mask; /* each bit says if 
that mipmap is compressed */
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 125e7ef..03bc955 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -405,26 +405,22 @@ void si_texture_discard_cmask(struct si_screen *sscreen,
 {
if (!rtex->cmask.size)
return;
 
assert(rtex->resource.b.b.nr_samples <= 1);
 
/* Disable CMASK. */
memset(>cmask, 0, sizeof(rtex->cmask));
rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
rtex->dirty_level_mask = 0;
-
rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
 
-   if (rtex->cmask_buffer != >resource)
-   r600_resource_reference(>cmask_buffer, NULL);
-
/* Notify all contexts about the change. */
p_atomic_inc(>dirty_tex_counter);
p_atomic_inc(>compressed_colortex_counter);
 }
 
 static bool r600_can_disable_dcc(struct r600_texture *rtex)
 {
/* We can't disable DCC if it can be written by another process. */
return rtex->dcc_offset &&
   (!rtex->resource.b.is_shared ||
@@ -813,24 +809,20 @@ static boolean r600_texture_get_handle(struct 
pipe_screen* screen,
  slice_size, whandle);
 }
 
 static void r600_texture_destroy(struct pipe_screen *screen,
 struct pipe_resource *ptex)
 {
struct r600_texture *rtex = (struct r600_texture*)ptex;
struct r600_resource *resource = >resource;
 
r600_texture_reference(>flushed_depth_texture, NULL);
-
-   if (rtex->cmask_buffer != >resource) {
-   r600_resource_reference(>cmask_buffer, NULL);
-   }
pb_reference(>buf, NULL);
r600_resource_reference(>dcc_separate_buffer, NULL);
r600_resource_reference(>last_dcc_separate_buffer, NULL);
FREE(rtex);
 }
 
 static const struct u_resource_vtbl r600_texture_vtbl;
 
 /* The number of samples can be specified independently of the texture. */
 void si_texture_get_fmask_info(struct si_screen *sscreen,
@@ -1262,21 +1254,20 @@ r600_texture_create_object(struct pipe_screen *screen,
rtex->db_compatible = true;
 
if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
r600_texture_allocate_htile(sscreen, rtex);
}
} else {
if (base->nr_samples > 1) {
if (!buf) {
r600_texture_allocate_fmask(sscreen, rtex);
r600_texture_allocate_cmask(sscreen, rtex);
-   rtex->cmask_buffer = >resource;
}
if (!rtex->fmask.size || !rtex->cmask.size) {
FREE(rtex);
return NULL;
}
}
 
/* Shared textures must always set up DCC here.
 * If it's not present, it will be disabled by
 * apply_opaque_metadata later.
@@ -1306,21 +1297,21 @@ r600_texture_create_object(struct