From: Marek Olšák <marek.ol...@amd.com>
---
src/amd/common/ac_gpu_info.c | 3 +++
src/amd/common/ac_gpu_info.h | 1 +
src/gallium/drivers/radeonsi/si_get.c | 6 +-----
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 3 +++
4 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index aa18c97826c..b7b8c91e264 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -321,20 +321,22 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->si_TA_CS_BC_BASE_ADDR_allowed = true;
info->has_bo_metadata = true;
info->has_gpu_reset_status_query = true;
info->has_gpu_reset_counter_query = false;
info->has_eqaa_surface_allocator = true;
info->has_format_bc1_through_bc7 = true;
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
info->drm_minor >= 2;
info->has_indirect_compute_dispatch = true;
+ /* SI doesn't support unaligned loads. */
+ info->has_unaligned_shader_loads = info->chip_class != SI;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
if (info->family == CHIP_KAVERI)
info->num_render_backends = 2;
info->clock_crystal_freq = amdinfo->gpu_counter_freq;
if (!info->clock_crystal_freq) {
fprintf(stderr, "amdgpu: clock crystal frequency is 0,
timestamps will be wrong\n");
info->clock_crystal_freq = 1;
@@ -478,20 +480,21 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" kernel_flushes_hdp_before_ib = %u\n",
info->kernel_flushes_hdp_before_ib);
printf(" htile_cmask_support_1d_tiling = %u\n",
info->htile_cmask_support_1d_tiling);
printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n",
info->si_TA_CS_BC_BASE_ADDR_allowed);
printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
printf(" has_gpu_reset_status_query = %u\n",
info->has_gpu_reset_status_query);
printf(" has_gpu_reset_counter_query = %u\n",
info->has_gpu_reset_counter_query);
printf(" has_eqaa_surface_allocator = %u\n",
info->has_eqaa_surface_allocator);
printf(" has_format_bc1_through_bc7 = %u\n",
info->has_format_bc1_through_bc7);
printf(" kernel_flushes_tc_l2_after_ib = %u\n",
info->kernel_flushes_tc_l2_after_ib);
printf(" has_indirect_compute_dispatch = %u\n",
info->has_indirect_compute_dispatch);
+ printf(" has_unaligned_shader_loads = %u\n",
info->has_unaligned_shader_loads);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
printf(" num_good_compute_units = %i\n",
info->num_good_compute_units);
printf(" max_se = %i\n", info->max_se);
printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
printf("Render backend info:\n");
printf(" num_render_backends = %i\n", info->num_render_backends);
printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index d5d10c60102..e95dcbd906c 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -99,20 +99,21 @@ struct radeon_info {
bool kernel_flushes_hdp_before_ib;
bool htile_cmask_support_1d_tiling;
bool si_TA_CS_BC_BASE_ADDR_allowed;
bool has_bo_metadata;
bool has_gpu_reset_status_query;
bool has_gpu_reset_counter_query;
bool has_eqaa_surface_allocator;
bool has_format_bc1_through_bc7;
bool kernel_flushes_tc_l2_after_ib;
bool has_indirect_compute_dispatch;
+ bool has_unaligned_shader_loads;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */
uint32_t max_shader_clock;
uint32_t num_good_compute_units;
uint32_t max_se; /* shader engines */
uint32_t max_sh_per_se; /* shader arrays per shader
engine */
/* Render backends (color + depth blocks). */
uint32_t r300_num_gb_pipes;
diff --git a/src/gallium/drivers/radeonsi/si_get.c
b/src/gallium/drivers/radeonsi/si_get.c
index 3feb1ae7823..d2bee21a1fe 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -219,25 +219,21 @@ static int si_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
if (sscreen->info.has_indirect_compute_dispatch)
return 450;
return 420;
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return MIN2(sscreen->info.max_alloc_size, INT_MAX);
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
- /* SI doesn't support unaligned loads.
- * CIK needs DRM 2.50.0 on radeon. */
- return sscreen->info.chip_class == SI ||
- (sscreen->info.drm_major == 2 &&
- sscreen->info.drm_minor < 50);
+ return !sscreen->info.has_unaligned_shader_loads;
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
/* TODO: GFX9 hangs. */
if (sscreen->info.chip_class >= GFX9)
return 0;
/* Disable on SI due to VM faults in CP DMA. Enable once these
* faults are mitigated in software.
*/
if (sscreen->info.chip_class >= CIK &&
sscreen->info.drm_major == 3 &&
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 6edec7b6e71..54ccbf7fd00 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -541,20 +541,23 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.has_gpu_reset_status_query = false;
ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
ws->info.has_eqaa_surface_allocator = false;
ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
ws->info.kernel_flushes_tc_l2_after_ib = true;
/* Old kernels disallowed register writes via COPY_DATA
* that are used for indirect compute dispatches. */
ws->info.has_indirect_compute_dispatch = ws->info.chip_class == CIK ||
(ws->info.chip_class == SI &&
ws->info.drm_minor >= 45);
+ /* SI doesn't support unaligned loads. */
+ ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
+ ws->info.drm_minor >= 50;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") !=
NULL;
return true;
}
static void radeon_winsys_destroy(struct radeon_winsys *rws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
--
2.17.0
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