---
src/gallium/drivers/radeonsi/si_shader.h | 3 +++
src/gallium/drivers/radeonsi/si_shader_nir.c | 19 +++++++++++++++++++
src/gallium/drivers/radeonsi/si_state_shaders.c | 1 +
3 files changed, 23 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_shader.h
b/src/gallium/drivers/radeonsi/si_shader.h
index bcb5c9da4ce..87aa6d416f2 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -647,20 +647,23 @@ void si_shader_apply_scratch_relocs(struct si_shader
*shader,
void si_shader_binary_read_config(struct ac_shader_binary *binary,
struct si_shader_config *conf,
unsigned symbol_offset);
unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
bool writes_samplemask);
const char *si_get_shader_name(const struct si_shader *shader, unsigned
processor);
/* si_shader_nir.c */
void si_nir_scan_shader(const struct nir_shader *nir,
struct tgsi_shader_info *info);
+void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
+ const struct tgsi_shader_info *info,
+ struct tgsi_tessctrl_info *out);
void si_lower_nir(struct si_shader_selector *sel);
/* Inline helpers. */
/* Return the pointer to the main shader part's pointer. */
static inline struct si_shader **
si_get_main_shader_part(struct si_shader_selector *sel,
struct si_shader_key *key)
{
if (key->as_ls)
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index d2760b03bca..f96bf7c2d2f 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -123,20 +123,39 @@ static void scan_instruction(struct tgsi_shader_info
*info,
case nir_intrinsic_ssbo_atomic_exchange:
case nir_intrinsic_ssbo_atomic_comp_swap:
info->writes_memory = true;
break;
default:
break;
}
}
}
+void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
+ const struct tgsi_shader_info *info,
+ struct tgsi_tessctrl_info *out)
+{
+ memset(out, 0, sizeof(*out));
+
+ if (nir->info.stage != MESA_SHADER_TESS_CTRL)
+ return;
+
+ /* Initial value = true. Here the pass will accumulate results from
+ * multiple segments surrounded by barriers. If tess factors aren't
+ * written at all, it's a shader bug and we don't care if this will be
+ * true.
+ */
+ out->tessfactors_are_def_in_all_invocs = true;
+
+ /* TODO: Implement scanning of tess factors, see tgsi backend. */
+}
+
void si_nir_scan_shader(const struct nir_shader *nir,
struct tgsi_shader_info *info)
{
nir_function *func;
unsigned i;
assert(nir->info.stage == MESA_SHADER_VERTEX ||
nir->info.stage == MESA_SHADER_GEOMETRY ||
nir->info.stage == MESA_SHADER_FRAGMENT);
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 4f683b85144..f70af15e113 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2052,20 +2052,21 @@ static void *si_create_shader_selector(struct
pipe_context *ctx,
}
tgsi_scan_shader(state->tokens, &sel->info);
tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
} else {
assert(state->type == PIPE_SHADER_IR_NIR);
sel->nir = state->ir.nir;
si_nir_scan_shader(sel->nir, &sel->info);
+ si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
si_lower_nir(sel);
}
sel->type = sel->info.processor;
p_atomic_inc(&sscreen->num_shaders_created);
si_get_active_slot_masks(&sel->info,
&sel->active_const_and_shader_buffers,
&sel->active_samplers_and_images);
--
2.14.3
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