Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_defines.h | 1 +
src/mesa/drivers/dri/i965/gen8_surface_state.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index fa71865..f7f904c 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -656,6 +656,7 @@
#define GEN8_SURFACE_AUX_MODE_MCS 1
#define GEN8_SURFACE_AUX_MODE_APPEND 2
#define GEN8_SURFACE_AUX_MODE_HIZ 3
+#define GEN9_SURFACE_AUX_MODE_CCS_E 5
/* Surface state DW7 */
#define GEN9_SURFACE_RT_COMPRESSION_SHIFT 30
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 0a52815..b140ff4 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -216,6 +216,9 @@ gen8_get_aux_mode(const struct brw_context *brw,
if (brw->gen >= 9 || mt->num_samples == 1)
assert(mt->halign == 16);
+ if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CSS)
+ return GEN9_SURFACE_AUX_MODE_CCS_E;
+
return GEN8_SURFACE_AUX_MODE_MCS;
}
@@ -484,6 +487,9 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
const uint32_t aux_mode = gen8_get_aux_mode(brw, mt, surf_type);
+ if (aux_mode == GEN9_SURFACE_AUX_MODE_CCS_E)
+ mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
+
uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);
surf[0] = (surf_type << BRW_SURFACE_TYPE_SHIFT) |
--
2.5.0
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