From: Nicolai Hähnle <nicolai.haeh...@amd.com>
---
src/gallium/drivers/radeonsi/si_shader.c | 32 +++++++++++------------
src/gallium/drivers/radeonsi/si_shader_internal.h | 4 +++
2 files changed, 20 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 39ce080..1001b27 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -587,23 +587,23 @@ static LLVMValueRef get_indirect_index(struct
si_shader_context *ctx,
result = LLVMBuildLoad(gallivm->builder, result, "");
result = LLVMBuildAdd(gallivm->builder, result,
LLVMConstInt(ctx->i32, rel_index, 0), "");
return result;
}
/**
* Like get_indirect_index, but restricts the return value to a (possibly
* undefined) value inside [0..num).
*/
-static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
- const struct tgsi_ind_register
*ind,
- int rel_index, unsigned num)
+LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
+ const struct tgsi_ind_register *ind,
+ int rel_index, unsigned num)
{
LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
return si_llvm_bound_index(ctx, result, num);
}
/**
* Calculate a dword address given an input or output register and a stride.
*/
@@ -1754,23 +1754,23 @@ static LLVMValueRef fetch_constant(
return lp_build_gather_values(&ctx->gallivm, values, 4);
}
buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
idx = reg->Register.Index * 4 + swizzle;
if (reg->Register.Dimension && reg->Dimension.Indirect) {
LLVMValueRef ptr = LLVMGetParam(ctx->main_fn,
ctx->param_const_buffers);
LLVMValueRef index;
- index = get_bounded_indirect_index(ctx, ®->DimIndirect,
- reg->Dimension.Index,
- SI_NUM_CONST_BUFFERS);
+ index = si_get_bounded_indirect_index(ctx, ®->DimIndirect,
+ reg->Dimension.Index,
+ SI_NUM_CONST_BUFFERS);
bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
} else
bufp = load_const_buffer_desc(ctx, buf);
if (reg->Register.Indirect) {
addr = ctx->addrs[ireg->Index][ireg->Swizzle];
addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr
reg");
addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
addr = lp_build_add(&bld_base->uint_bld, addr,
LLVMConstInt(ctx->i32, idx * 4, 0));
@@ -3466,23 +3466,23 @@ static LLVMValueRef
shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
const struct tgsi_full_src_register *reg)
{
LLVMValueRef index;
LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
ctx->param_shader_buffers);
if (!reg->Register.Indirect)
index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
else
- index = get_bounded_indirect_index(ctx, ®->Indirect,
- reg->Register.Index,
- SI_NUM_SHADER_BUFFERS);
+ index = si_get_bounded_indirect_index(ctx, ®->Indirect,
+ reg->Register.Index,
+ SI_NUM_SHADER_BUFFERS);
return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
}
static bool tgsi_is_array_sampler(unsigned target)
{
return target == TGSI_TEXTURE_1D_ARRAY ||
target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
target == TGSI_TEXTURE_2D_ARRAY ||
target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
@@ -3583,23 +3583,23 @@ image_fetch_rsrc(
} else {
/* From the GL_ARB_shader_image_load_store extension spec:
*
* If a shader performs an image load, store, or atomic
* operation using an image variable declared as an array,
* and if the index used to select an individual element is
* negative or greater than or equal to the size of the
* array, the results of the operation are undefined but may
* not lead to termination.
*/
- index = get_bounded_indirect_index(ctx, &image->Indirect,
- image->Register.Index,
- SI_NUM_IMAGES);
+ index = si_get_bounded_indirect_index(ctx, &image->Indirect,
+ image->Register.Index,
+ SI_NUM_IMAGES);
}
*rsrc = load_image_desc(ctx, rsrc_ptr, index, target);
if (dcc_off && target != TGSI_TEXTURE_BUFFER)
*rsrc = force_dcc_off(ctx, *rsrc);
}
static LLVMValueRef image_fetch_coords(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_instruction *inst,
@@ -4579,24 +4579,24 @@ static void tex_fetch_ptrs(
const struct tgsi_full_instruction *inst = emit_data->inst;
const struct tgsi_full_src_register *reg;
unsigned target = inst->Texture.Texture;
unsigned sampler_src;
LLVMValueRef index;
sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
reg = &emit_data->inst->Src[sampler_src];
if (reg->Register.Indirect) {
- index = get_bounded_indirect_index(ctx,
- ®->Indirect,
- reg->Register.Index,
- SI_NUM_SAMPLERS);
+ index = si_get_bounded_indirect_index(ctx,
+ ®->Indirect,
+ reg->Register.Index,
+ SI_NUM_SAMPLERS);
} else {
index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
}
if (target == TGSI_TEXTURE_BUFFER)
*res_ptr = load_sampler_desc(ctx, list, index, DESC_BUFFER);
else
*res_ptr = load_sampler_desc(ctx, list, index, DESC_IMAGE);
if (samp_ptr)
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index c3913de..70004fa 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -287,13 +287,17 @@ void si_llvm_emit_store(struct lp_build_tgsi_context
*bld_base,
const struct tgsi_opcode_info *info,
LLVMValueRef dst[4]);
/* Combine these with & instead of |. */
#define NOOP_WAITCNT 0xf7f
#define LGKM_CNT 0x07f
#define VM_CNT 0xf70
void si_emit_waitcnt(struct si_shader_context *ctx, unsigned simm16);
+LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
+ const struct tgsi_ind_register *ind,
+ int rel_index, unsigned num);
+
void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
#endif
--
2.9.3
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