Re: [Mesa-dev] [PATCH 3/3] i965: Use correct VertStride on align16 instructions.

2017-01-23 Thread Matt Turner
On Mon, Jan 23, 2017 at 2:59 AM, Samuel Iglesias Gonsálvez wrote: > On Fri, 2017-01-20 at 14:25 -0800, Francisco Jerez wrote: >> Matt Turner writes: >> >> > In commit c35fa7a, we changed the "width" of DF source registers to >> > 2, >> > which is

Re: [Mesa-dev] [PATCH 3/3] i965: Use correct VertStride on align16 instructions.

2017-01-23 Thread Samuel Iglesias Gonsálvez
On Fri, 2017-01-20 at 14:25 -0800, Francisco Jerez wrote: > Matt Turner writes: > > > In commit c35fa7a, we changed the "width" of DF source registers to > > 2, > > which is conceptually fine. Unfortunately a VertStride of 2 is not > > allowed by align16 instructions on

Re: [Mesa-dev] [PATCH 3/3] i965: Use correct VertStride on align16 instructions.

2017-01-20 Thread Francisco Jerez
Matt Turner writes: > In commit c35fa7a, we changed the "width" of DF source registers to 2, > which is conceptually fine. Unfortunately a VertStride of 2 is not > allowed by align16 instructions on IVB/BYT, and the regular VertStride > of 4 works fine in any case. > I'll

[Mesa-dev] [PATCH 3/3] i965: Use correct VertStride on align16 instructions.

2017-01-20 Thread Matt Turner
In commit c35fa7a, we changed the "width" of DF source registers to 2, which is conceptually fine. Unfortunately a VertStride of 2 is not allowed by align16 instructions on IVB/BYT, and the regular VertStride of 4 works fine in any case. See