Re: [Mesa-dev] [PATCH 3/7] i965: Stop passing read/write domains to load_reg_mem32/64

2016-12-09 Thread Lionel Landwerlin 
Some I915_GEM_DOMAIN_VERTEX are changed to I915_GEM_DOMAIN_INSTRUCTION, 
which are treated the same way in the kernel. So I guess it doesn't matter.


Reviewed-by: Lionel Landwerlin 

On 09/12/16 10:54, Chris Wilson wrote:

The domains used are immaterial, and we should never be marking the read
from the buffer as a write, so stop passing them around from the caller
and choose the appropriate read domain when writing.

Signed-off-by: Chris Wilson 
---
  src/mesa/drivers/dri/i965/brw_compute.c| 27 +--
  src/mesa/drivers/dri/i965/brw_conditional_render.c | 14 ++--
  src/mesa/drivers/dri/i965/brw_context.h| 10 +++---
  src/mesa/drivers/dri/i965/brw_draw.c   | 38 +-
  src/mesa/drivers/dri/i965/hsw_queryobj.c   | 29 -
  src/mesa/drivers/dri/i965/hsw_sol.c| 14 +++-
  src/mesa/drivers/dri/i965/intel_batchbuffer.c  | 19 +--
  7 files changed, 48 insertions(+), 103 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_compute.c 
b/src/mesa/drivers/dri/i965/brw_compute.c
index 16b5df7ca4..51cd45df7a 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -40,15 +40,12 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
 GLintptr indirect_offset = brw->compute.num_work_groups_offset;
 drm_intel_bo *bo = brw->compute.num_work_groups_bo;
  
-   brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo,

- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 0);
-   brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 4);
-   brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 8);
+   brw_load_register_mem32(brw,
+   GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0);
+   brw_load_register_mem32(brw,
+   GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4);
+   brw_load_register_mem32(brw,
+   GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8);
  
 if (brw->gen > 7)

return;
@@ -65,9 +62,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
 ADVANCE_BATCH();
  
 /* Load compute_dispatch_indirect_x_size into SRC0 */

-   brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 0);
+   brw_load_register_mem32(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0);
  
 /* predicate = (compute_dispatch_indirect_x_size == 0); */

 BEGIN_BATCH(1);
@@ -78,9 +73,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
 ADVANCE_BATCH();
  
 /* Load compute_dispatch_indirect_y_size into SRC0 */

-   brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 4);
+   brw_load_register_mem32(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4);
  
 /* predicate |= (compute_dispatch_indirect_y_size == 0); */

 BEGIN_BATCH(1);
@@ -91,9 +84,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
 ADVANCE_BATCH();
  
 /* Load compute_dispatch_indirect_z_size into SRC0 */

-   brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 8);
+   brw_load_register_mem32(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8);
  
 /* predicate |= (compute_dispatch_indirect_z_size == 0); */

 BEGIN_BATCH(1);
diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c 
b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index 122a4ecc0f..8574fc1aeb 100644
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -62,18 +62,8 @@ set_predicate_for_result(struct brw_context *brw,
  */
 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
  
-   brw_load_register_mem64(brw,

-   MI_PREDICATE_SRC0,
-   query->bo,
-   I915_GEM_DOMAIN_INSTRUCTION,
-   0, /* write domain */
-   0 /* offset */);
-   brw_load_register_mem64(brw,
-   MI_PREDICATE_SRC1,
-   query->bo,
-   I915_GEM_DOMAIN_INSTRUCTION,
-   0, /* write domain */
-   8 /* offset */);
+   brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, 0 /* offset */);
+   brw_load_register_mem64(brw, MI_PREDICATE_SRC1, query->bo, 8 /* offset */);
  
 if (inverted)

load_op =

[Mesa-dev] [PATCH 3/7] i965: Stop passing read/write domains to load_reg_mem32/64

2016-12-09 Thread Chris Wilson 
The domains used are immaterial, and we should never be marking the read
from the buffer as a write, so stop passing them around from the caller
and choose the appropriate read domain when writing.

Signed-off-by: Chris Wilson 
---
 src/mesa/drivers/dri/i965/brw_compute.c| 27 +--
 src/mesa/drivers/dri/i965/brw_conditional_render.c | 14 ++--
 src/mesa/drivers/dri/i965/brw_context.h| 10 +++---
 src/mesa/drivers/dri/i965/brw_draw.c   | 38 +-
 src/mesa/drivers/dri/i965/hsw_queryobj.c   | 29 -
 src/mesa/drivers/dri/i965/hsw_sol.c| 14 +++-
 src/mesa/drivers/dri/i965/intel_batchbuffer.c  | 19 +--
 7 files changed, 48 insertions(+), 103 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_compute.c 
b/src/mesa/drivers/dri/i965/brw_compute.c
index 16b5df7ca4..51cd45df7a 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -40,15 +40,12 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
GLintptr indirect_offset = brw->compute.num_work_groups_offset;
drm_intel_bo *bo = brw->compute.num_work_groups_bo;
 
-   brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 0);
-   brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 4);
-   brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo,
- I915_GEM_DOMAIN_VERTEX, 0,
- indirect_offset + 8);
+   brw_load_register_mem32(brw,
+   GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0);
+   brw_load_register_mem32(brw,
+   GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4);
+   brw_load_register_mem32(brw,
+   GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8);
 
if (brw->gen > 7)
   return;
@@ -65,9 +62,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
ADVANCE_BATCH();
 
/* Load compute_dispatch_indirect_x_size into SRC0 */
-   brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 0);
+   brw_load_register_mem32(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0);
 
/* predicate = (compute_dispatch_indirect_x_size == 0); */
BEGIN_BATCH(1);
@@ -78,9 +73,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
ADVANCE_BATCH();
 
/* Load compute_dispatch_indirect_y_size into SRC0 */
-   brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 4);
+   brw_load_register_mem32(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4);
 
/* predicate |= (compute_dispatch_indirect_y_size == 0); */
BEGIN_BATCH(1);
@@ -91,9 +84,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw)
ADVANCE_BATCH();
 
/* Load compute_dispatch_indirect_z_size into SRC0 */
-   brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo,
- I915_GEM_DOMAIN_INSTRUCTION, 0,
- indirect_offset + 8);
+   brw_load_register_mem32(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8);
 
/* predicate |= (compute_dispatch_indirect_z_size == 0); */
BEGIN_BATCH(1);
diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c 
b/src/mesa/drivers/dri/i965/brw_conditional_render.c
index 122a4ecc0f..8574fc1aeb 100644
--- a/src/mesa/drivers/dri/i965/brw_conditional_render.c
+++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c
@@ -62,18 +62,8 @@ set_predicate_for_result(struct brw_context *brw,
 */
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
 
-   brw_load_register_mem64(brw,
-   MI_PREDICATE_SRC0,
-   query->bo,
-   I915_GEM_DOMAIN_INSTRUCTION,
-   0, /* write domain */
-   0 /* offset */);
-   brw_load_register_mem64(brw,
-   MI_PREDICATE_SRC1,
-   query->bo,
-   I915_GEM_DOMAIN_INSTRUCTION,
-   0, /* write domain */
-   8 /* offset */);
+   brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, 0 /* offset */);
+   brw_load_register_mem64(brw, MI_PREDICATE_SRC1, query->bo, 8 /* offset */);
 
if (inverted)
   load_op = MI_PREDICATE_LOADOP_LOAD;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 550eefedcc..77a5f8b879 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1363,15 +1363,13 @@ void brw_init_conditional_render_functions(struct