[Mesa-dev] [PATCH 33/38] radv: store all fragment shader inputs as f32

[Rhys Perry]

Signed-off-by: Rhys Perry <pendingchao...@gmail.com>
---
 src/amd/vulkan/radv_nir_to_llvm.c | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index e5e4637f0d..3d367c1378 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2093,7 +2093,6 @@ static void interp_fs_input(struct radv_shader_context 
*ctx,
        LLVMValueRef attr_number;
        unsigned chan;
        LLVMValueRef i, j;
-       bool interp = !LLVMIsUndef(interp_param);
 
        attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
 
@@ -2107,7 +2106,7 @@ static void interp_fs_input(struct radv_shader_context 
*ctx,
         * fs.interp cannot be used on integers, because they can be equal
         * to NaN.
         */
-       if (interp) {
+       if (interp_param) {
                interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
                                                ctx->ac.v2f32, "");
 
@@ -2120,7 +2119,7 @@ static void interp_fs_input(struct radv_shader_context 
*ctx,
        for (chan = 0; chan < 4; chan++) {
                LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
 
-               if (interp) {
+               if (interp_param) {
                        result[chan] = ac_build_fs_interp(&ctx->ac,
                                                          llvm_chan,
                                                          attr_number,
@@ -2132,7 +2131,6 @@ static void interp_fs_input(struct radv_shader_context 
*ctx,
                                                              attr_number,
                                                              prim_mask);
                        result[chan] = LLVMBuildBitCast(ctx->ac.builder, 
result[chan], ctx->ac.i32, "");
-                       result[chan] = LLVMBuildTruncOrBitCast(ctx->ac.builder, 
result[chan], LLVMTypeOf(interp_param), "");
                }
        }
 }
@@ -2160,10 +2158,6 @@ handle_fs_input_decl(struct radv_shader_context *ctx,
 
                interp = lookup_interp_param(&ctx->abi, 
variable->data.interpolation, interp_type);
        }
-       bool is_16bit = glsl_type_is_16bit(variable->type);
-       LLVMTypeRef type = is_16bit ? ctx->ac.i16 : ctx->ac.i32;
-       if (interp == NULL)
-               interp = LLVMGetUndef(type);
 
        for (unsigned i = 0; i < attrib_count; ++i)
                ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
@@ -2224,7 +2218,7 @@ handle_fs_inputs(struct radv_shader_context *ctx,
        if (ctx->shader_info->info.ps.uses_input_attachments ||
            ctx->shader_info->info.needs_multiview_view_index) {
                ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
-               ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = 
LLVMGetUndef(ctx->ac.i32);
+               ctx->inputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)] = 
NULL;
        }
 
        for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
@@ -2240,7 +2234,7 @@ handle_fs_inputs(struct radv_shader_context *ctx,
                        interp_fs_input(ctx, index, interp_param, 
ctx->abi.prim_mask,
                                        inputs);
 
-                       if (LLVMIsUndef(interp_param))
+                       if (!interp_param)
                                ctx->shader_info->fs.flat_shaded_mask |= 1u << 
index;
                        ++index;
                } else if (i == VARYING_SLOT_CLIP_DIST0) {
-- 
2.19.2

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