Re: [Mesa-dev] [PATCH v3] i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT

2016-06-17 Thread Samuel Iglesias Gonsálvez
On 17/06/16 11:12, Kenneth Graunke wrote: > On Friday, June 17, 2016 11:10:28 AM PDT Samuel Iglesias Gonsálvez wrote: [...] >> What do you think Kenneth? >> >> Sam > > This sounds great to me. I like v4 (your suggestion above) the best. > Thanks for fixing this, and putting in the extra effort

Re: [Mesa-dev] [PATCH v3] i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT

2016-06-17 Thread Kenneth Graunke
On Friday, June 17, 2016 11:10:28 AM PDT Samuel Iglesias Gonsálvez wrote: > > On 17/06/16 10:43, Samuel Iglesias Gonsálvez wrote: > > From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region > > Restrictions, page 844: > > > > "When source or destination datatype is 64b or

Re: [Mesa-dev] [PATCH v3] i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT

2016-06-17 Thread Samuel Iglesias Gonsálvez
On 17/06/16 10:43, Samuel Iglesias Gonsálvez wrote: > From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region > Restrictions, page 844: > > "When source or destination datatype is 64b or operation is integer DWord >multiply, indirect addressing must not be used." > >

[Mesa-dev] [PATCH v3] i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT

2016-06-17 Thread Samuel Iglesias Gonsálvez
From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region Restrictions, page 844: "When source or destination datatype is 64b or operation is integer DWord multiply, indirect addressing must not be used." v2: - Fix it for Broxton too. v3: - Simplify code by using