Re: [Mesa-dev] [PATCH v3 24/42] intel/compiler: fix ddy for half-float in gen8

2019-01-23 Thread Iago Toral
On Tue, 2019-01-22 at 16:36 -0800, Matt Turner wrote: > On Tue, Jan 15, 2019 at 5:54 AM Iago Toral Quiroga > wrote: > > > > We use ALign16 mode for this, since it is more convenient, but the > > PRM > > for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register > > region > >

Re: [Mesa-dev] [PATCH v3 24/42] intel/compiler: fix ddy for half-float in gen8

2019-01-22 Thread Matt Turner
On Tue, Jan 15, 2019 at 5:54 AM Iago Toral Quiroga wrote: > > We use ALign16 mode for this, since it is more convenient, but the PRM > for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region > restrictions', Section '1. Special Restrictions': > >"In Align16 mode, the channel

[Mesa-dev] [PATCH v3 24/42] intel/compiler: fix ddy for half-float in gen8

2019-01-15 Thread Iago Toral Quiroga
We use ALign16 mode for this, since it is more convenient, but the PRM for Broadwell states in Volume 3D Media GPGPU, Chapter 'Register region restrictions', Section '1. Special Restrictions': "In Align16 mode, the channel selects and channel enables apply to a pair of half-floats, because