https://gitlab.freedesktop.org/mesa/mesa/merge_requests/39
Some upcoming Intel platforms do not have 64-bit type support. This series implements support for ARB_gpu_shader_fp64 and ARB_gpu_shader_int64 via software implementations. To do this we add a .glsl file containing GLSL implementations of various 64-bit operations (e.g., double-precision addition) and compile them to NIR when we see that the "user shader" uses some 64-bit operations. Lowering is done in nir_lower_doubles() but a little differently than normal: we convert the to-be-lowered operations into function calls of the software routines and ultimately inline the code. In the future we may wish to use real function calls. I have a few known test failures (seem to be mostly about ARB_enhanced_layouts -- which makes since given that we're faking 64-bit types) but I think this is good enough to merge. I hope after review you will agree! src/compiler/Makefile.glsl.am | 7 + src/compiler/glsl/ast_function.cpp | 5 +- src/compiler/glsl/float64.glsl | 1744 ++++++++++++++++++++ src/compiler/glsl/glsl_to_nir.cpp | 125 +- src/compiler/glsl/meson.build | 10 +- src/compiler/glsl/xxd.py | 109 ++ src/compiler/nir/nir.c | 1 + src/compiler/nir/nir.h | 34 +- src/compiler/nir/nir_algebraic.py | 7 +- src/compiler/nir/nir_builder.h | 1 + src/compiler/nir/nir_clone.c | 1 + src/compiler/nir/nir_gather_info.c | 5 + src/compiler/nir/nir_inline_functions.c | 4 + src/compiler/nir/nir_lower_constant_initializers.c | 32 +- src/compiler/nir/nir_lower_double_ops.c | 208 ++- src/compiler/nir/nir_lower_global_vars_to_local.c | 8 + src/compiler/nir/nir_lower_int64.c | 471 +++++- src/compiler/nir/nir_lower_load_const_to_scalar.c | 7 +- src/compiler/nir/nir_lower_returns.c | 4 + src/compiler/nir/nir_lower_var_copies.c | 7 +- src/compiler/nir/nir_lower_vars_to_ssa.c | 6 +- src/compiler/nir/nir_opt_constant_folding.c | 7 +- src/compiler/nir/nir_opt_copy_prop_vars.c | 4 + src/compiler/nir/nir_opt_copy_propagate.c | 4 + src/compiler/nir/nir_opt_cse.c | 7 +- src/compiler/nir/nir_opt_dce.c | 7 +- src/compiler/nir/nir_opt_dead_cf.c | 7 +- src/compiler/nir/nir_opt_if.c | 4 + src/compiler/nir/nir_opt_peephole_select.c | 7 +- src/compiler/nir/nir_opt_remove_phis.c | 4 + src/compiler/nir/nir_opt_undef.c | 7 +- src/compiler/nir/nir_serialize.c | 4 + src/compiler/nir/nir_split_var_copies.c | 4 + src/compiler/shader_info.h | 5 + src/compiler/spirv/spirv_to_nir.c | 1 + src/intel/compiler/brw_eu_emit.c | 12 +- src/intel/compiler/brw_fs.cpp | 68 +- src/intel/compiler/brw_fs.h | 2 +- src/intel/compiler/brw_fs_combine_constants.cpp | 7 +- src/intel/compiler/brw_fs_generator.cpp | 3 +- src/intel/compiler/brw_fs_nir.cpp | 4 +- src/intel/compiler/brw_fs_reg_allocate.cpp | 2 +- src/intel/compiler/brw_fs_register_coalesce.cpp | 8 +- src/intel/compiler/brw_nir.c | 91 +- src/intel/compiler/brw_reg.h | 7 +- src/intel/compiler/brw_schedule_instructions.cpp | 14 +- src/intel/compiler/brw_vec4.cpp | 12 +- src/intel/compiler/brw_vec4.h | 2 +- src/intel/compiler/brw_vec4_reg_allocate.cpp | 12 +- src/intel/compiler/brw_vec4_visitor.cpp | 4 +- src/intel/compiler/gen6_gs_visitor.cpp | 4 +- src/mesa/drivers/dri/i965/Makefile.am | 1 + src/mesa/drivers/dri/i965/brw_program.c | 61 + src/mesa/drivers/dri/i965/intel_extensions.c | 8 +- src/mesa/drivers/dri/i965/meson.build | 2 +- 55 files changed, 3061 insertions(+), 131 deletions(-) _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
