[Mesa-dev] [PATCH v2] glsl: Skip "unsized arrays aren't allowed" check for TCS/TES/GS vars.

2016-09-17 Thread Kenneth Graunke
Fixes ESEXT-CTS.draw_elements_base_vertex_tests.AEP_shader_stages and ESEXT-CTS.texture_cube_map_array.texture_size_tesselation_con_sh. Signed-off-by: Kenneth Graunke --- src/compiler/glsl/ast_to_hir.cpp | 28 +++- 1 file changed, 27 insertions(+),

Re: [Mesa-dev] [PATCH v2] glsl: Skip "unsized arrays aren't allowed" check for TCS/TES/GS vars.

2016-09-17 Thread Ilia Mirkin
Reviewed-by: Ilia Mirkin On Sep 17, 2016 3:53 PM, "Kenneth Graunke" wrote: > Fixes ESEXT-CTS.draw_elements_base_vertex_tests.AEP_shader_stages and > ESEXT-CTS.texture_cube_map_array.texture_size_tesselation_con_sh. > > Signed-off-by: Kenneth Graunke

Re: [Mesa-dev] [PATCH 00/14] radeon/winsyses: sub-allocation for small buffers

2016-09-17 Thread Marek Olšák
On Tue, Sep 13, 2016 at 11:56 AM, Nicolai Hähnle wrote: > Hi, > > there are a bunch of games that allocate huge numbers of small buffers. This > is especially problematic on amdgpu, where we tend to keep mmaps of buffers > around for performance, and we hit the limit of 64k

Re: [Mesa-dev] [PATCH 04/14] gallium/radeon: add RADEON_FLAG_HANDLE

2016-09-17 Thread Marek Olšák
On Tue, Sep 13, 2016 at 11:56 AM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > When passed to winsys->buffer_create, this flag will indicate that we require > a buffer that maps 1:1 with a kernel buffer handle. > > This is currently set for all

Re: [Mesa-dev] [PATCH 06/14] winsys/amdgpu: add slab entry structures to amdgpu_winsys_bo

2016-09-17 Thread Marek Olšák
On Tue, Sep 13, 2016 at 11:56 AM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > Already adjust amdgpu_bo_map/unmap accordingly. > --- > src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 83 > --- >

Re: [Mesa-dev] [PATCH 0/9] radeonsi: ARB_query_buffer_object implementation

2016-09-17 Thread Nicolai Hähnle
On 16.09.2016 19:11, Ian Romanick wrote: On 09/16/2016 06:57 AM, Nicolai Hähnle wrote: Hi all, as the title says. The implementation uses a compute shader to summarize data from the query buffers. As long as only one query buffer is in flight (the normal case), that compute shader is launched

Re: [Mesa-dev] [PATCH 06/14] winsys/amdgpu: add slab entry structures to amdgpu_winsys_bo

2016-09-17 Thread Nicolai Hähnle
On 17.09.2016 15:19, Marek Olšák wrote: On Tue, Sep 13, 2016 at 11:56 AM, Nicolai Hähnle wrote: From: Nicolai Hähnle Already adjust amdgpu_bo_map/unmap accordingly. --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 83

Re: [Mesa-dev] [PATCH 04/14] gallium/radeon: add RADEON_FLAG_HANDLE

2016-09-17 Thread Nicolai Hähnle
On 17.09.2016 13:49, Marek Olšák wrote: On Tue, Sep 13, 2016 at 11:56 AM, Nicolai Hähnle wrote: From: Nicolai Hähnle When passed to winsys->buffer_create, this flag will indicate that we require a buffer that maps 1:1 with a kernel buffer handle.

Re: [Mesa-dev] [PATCH 3/9] radeonsi: add si_get_shader_buffers/get_pipe_constant_buffers

2016-09-17 Thread Nicolai Hähnle
On 16.09.2016 22:20, Bas Nieuwenhuizen wrote: On Fri, Sep 16, 2016 at 3:57 PM, Nicolai Hähnle wrote: From: Nicolai Hähnle These functions extract the pipe state structure from the current descriptors, for state saving. ---

Re: [Mesa-dev] [PATCH 8/9] gallium/radeon: implement get_query_result_resource

2016-09-17 Thread Nicolai Hähnle
On 16.09.2016 17:18, Gustaw Smolarczyk wrote: 2016-09-16 15:57 GMT+02:00 Nicolai Hähnle : From: Nicolai Hähnle --- src/gallium/drivers/radeon/r600_pipe_common.c | 3 + src/gallium/drivers/radeon/r600_pipe_common.h | 2 +

Re: [Mesa-dev] [PATCH 06/14] winsys/amdgpu: add slab entry structures to amdgpu_winsys_bo

2016-09-17 Thread Marek Olšák
On Sat, Sep 17, 2016 at 4:46 PM, Nicolai Hähnle wrote: > On 17.09.2016 15:19, Marek Olšák wrote: >> >> On Tue, Sep 13, 2016 at 11:56 AM, Nicolai Hähnle >> wrote: >>> >>> From: Nicolai Hähnle >>> >>> Already adjust

Re: [Mesa-dev] [PATCH] nvc0/ir: fix comments about instructions info

2016-09-17 Thread Ilia Mirkin
Acked-by: Ilia Mirkin I didn't double-check the bits, but those sound right, and the number of bits set now matches up to the number of instructions in the comments. On Tue, Sep 13, 2016 at 1:37 PM, Samuel Pitoiset wrote: > The comment for the

Re: [Mesa-dev] [PATCH v2] nvc0/ir: fix subops for IMAD

2016-09-17 Thread Ilia Mirkin
Reviewed-by: Ilia Mirkin On Thu, Sep 15, 2016 at 12:11 PM, Samuel Pitoiset wrote: > Offset was wrong, it's at bit 8, not 4. Also, uses subr instead > of sub when src2 has neg. Similar to GK110 now. > > Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH] vl/dri3: handle the case of different GPU(v4.1)

2016-09-17 Thread Nayan Deshmukh
Hi Leo, Could you push the patches? I don't have the push access. Regards, Nayan. On Fri, Sep 16, 2016 at 7:44 PM, Leo Liu wrote: > This Patch is Reviewed-by: Leo Liu > > > On 09/16/2016 08:51 AM, Nayan Deshmukh wrote: > >> In case of prime when rendering is

Re: [Mesa-dev] [PATCH 00/14] radeon/winsyses: sub-allocation for small buffers

2016-09-17 Thread Edward O'Callaghan
Big series, a lot to take in! But from what I can tell, Reviewed-by: Edward O'Callaghan Obviously someone else's Rb would be good too due how big this change is. Thanks for breaking it down the way you did though! On 09/13/2016 07:56 PM, Nicolai Hähnle wrote: > Hi,