Re: [Mesa-dev] [PATCH] radv: drop assert on bindingDescriptorCount > 0

Yeah, noticed that CTS fail this morning too. :) Reviewed-by: Samuel Pitoiset On 03/08/2018 01:16 AM, Dave Airlie wrote: From: Dave Airlie The spec is pretty clear that this can be 0, and that it operates as a reserved binding. Fixes:

[Mesa-dev] [PATCH 00/11] Initial gl_spirv support in Mesa and i965

Hi, This is the 5rd version of the series adding initial support for ARB_gl_spirv. Although the development branch is bigger (more that 80 patches), as mentioned, we prefer to send small, self-contained series, to make the review process easier. This series is mostly equal to v4 except: * New

[Mesa-dev] [PATCH 02/11] i965: initialize SPIR-V capabilities

Needed for ARB_gl_spirv. Right now those are the same that the intel vulkan driver, but those are not shared. From the ARB_spirv_extensions spec: "3. If a new GL extension is added that includes SPIR-V support via a new SPIR-V extension does it's SPIR-V extension also get enumerated by

[Mesa-dev] [PATCH 04/11] nir/spirv: add gl_spirv_validation method

ARB_gl_spirv adds the ability to use SPIR-V binaries, and a new method, glSpecializeShader. From OpenGL 4.6 spec, section 7.2.1 "Shader Specialization", error table: INVALID_VALUE is generated if does not name a valid entry point for . INVALID_VALUE is generated if any element

Re: [Mesa-dev] [PATCH] radv: don't lower indirects until after opts have run

On Thu, Mar 8, 2018 at 9:37 AM, Timothy Arceri wrote: > Noticed while passing by. nNot sure if it impacts anything, but > likely to impact GFX9 more than anything else since we lower > inputs, outputs and locals there. > --- > src/amd/vulkan/radv_shader.c | 10 +- >

Re: [Mesa-dev] [PATCH 1/2] etnaviv: add query_group_info for sw counters

Am Montag, den 05.03.2018, 23:26 +0100 schrieb Christian Gmeiner: > Signed-off-by: Christian Gmeiner Reviewed-by: Lucas Stach > --- >  src/gallium/drivers/etnaviv/etnaviv_query_sw.c | 30 > -- >  

Re: [Mesa-dev] [PATCH 2/2] etnaviv: add get_driver_query_group_info(..)

Am Montag, den 05.03.2018, 23:26 +0100 schrieb Christian Gmeiner: > This enables AMD_performance_monitor extension. > > Signed-off-by: Christian Gmeiner Reviewed-by: Lucas Stach > --- >  src/gallium/drivers/etnaviv/etnaviv_query.c | 13

[Mesa-dev] [PATCH 08/11] mesa/program: Link SPIR-V shaders using the SPIR-V code-path

From: Eduardo Lima Mitev --- src/mesa/program/ir_to_mesa.cpp | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp index 74089605029..4d45b0a4cd5 100644 --- a/src/mesa/program/ir_to_mesa.cpp

[Mesa-dev] [PATCH 07/11] mesa/glspirv: Add _mesa_spirv_link_shaders() function

From: Eduardo Lima Mitev This is the equivalent to link_shaders() from src/compiler/glsl/linker.cpp, but for SPIR-V programs. It just creates the program and its gl_linked_shader objects, giving drivers the opportunity to implement any linking of SPIR-V shaders they choose, at

Re: [Mesa-dev] [PATCH v4 20/20] clover: Implement clCreateProgramWithIL from OpenCL 2.1

Reviewed-by: Karol Herbst On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote: > Signed-off-by: Pierre Moreau > --- > > Notes: > v3: Remove the const from the length argument of clCreateProgramWithIL > >

Re: [Mesa-dev] [PATCH v4 19/20] clover: Advertise cl_khr_il_program

Reviewed-by: Karol Herbst On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote: > Signed-off-by: Pierre Moreau > --- > > Notes: > Changes in v4: do not advertise SPIR-V support if CLOVER_ALLOW_SPIRV is > not defined > >

[Mesa-dev] [PATCH 01/11] mesa: add gl_constants::SpirVCapabilities

From: Nicolai Hähnle For drivers to declare which SPIR-V features they support. v2: Don't use a pointer (Ian Romanick) --- src/mesa/main/mtypes.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index

[Mesa-dev] [PATCH 05/11] mesa: Implement glSpecializeShaderARB

From: Nicolai Hähnle v2: * Use gl_spirv_validation instead of spirv_to_nir. This method just validates the shader. The conversion to NIR will happen later, during linking. (Alejandro Piñeiro) * Use gl_shader_spirv_data struct to store the SPIR-V data.

[Mesa-dev] [PATCH 09/11] mesa/glspirv: Add a _mesa_spirv_to_nir() function

From: Eduardo Lima Mitev This is basically a wrapper around spirv_to_nir() that includes arguments setup and post-conversion validation. v2: * Rebase update (SpirVCapabilities not a pointer anymore, spirv_to_nir_options added, and others). * Code-style improvements and

[Mesa-dev] [PATCH 11/11] i965: Don't call process_glsl_ir() for SPIR-V shaders

From: Eduardo Lima Mitev v2: Use 'spirv_data' from gl_linked_shader instead, to check if shader is SPIR-V. (Timothy Arceri) Reviewed-by: Timothy Arceri --- src/mesa/drivers/dri/i965/brw_link.cpp | 3 ++- 1 file changed, 2 insertions(+), 1

[Mesa-dev] [PATCH 06/11] mesa: Add a reference to gl_shader_spirv_data to gl_linked_shader

From: Eduardo Lima Mitev This is a reference to the spirv_data object stored in gl_shader, which stores shader SPIR-V data that is needed during linking too. Reviewed-by: Timothy Arceri --- src/mesa/main/mtypes.h| 8

[Mesa-dev] [PATCH 10/11] i965: Call spirv_to_nir() instead of glsl_to_nir() for SPIR-V shaders

From: Eduardo Lima Mitev This is the main fork of the shader compilation code-path, where a NIR shader is obtained by calling spirv_to_nir() or glsl_to_nir(), depending on its nature.. v2: Use 'spirv_data' member from gl_linked_shader to know which method to call. (Timothy

[Mesa-dev] [PATCH 03/11] spirv: add vtn_builder_create

Refactored from spirv_to_nir, in order to be reused later. --- src/compiler/spirv/spirv_to_nir.c | 48 ++- src/compiler/spirv/vtn_private.h | 4 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c

Re: [Mesa-dev] [PATCH v4 04/20] clover: Remove the TGSI backend as unused

Reviewed-by: Karol Herbst On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote: > Signed-off-by: Pierre Moreau > --- > src/gallium/state_trackers/clover/Makefile.am | 11 +- >

Re: [Mesa-dev] [PATCH 00/56] anv: Add support for Vulkan 1.1

Many thanks to you Jason! On Wed, Mar 7, 2018 at 11:08 PM, Jason Ekstrand wrote: > Hi all, > > I just wanted to give a shout out and a huge "Thank You!" to all of the > people who made this release possible. There were a large number of > features packed into the 1.1

Re: [Mesa-dev] [PATCH 00/56] anv: Add support for Vulkan 1.1

Thanks for the kind words Jason, this is a superb achievement and we are very proud to had the chance to work on this with you! Iago On Wed, 2018-03-07 at 15:08 -0800, Jason Ekstrand wrote: > Hi all, > > I just wanted to give a shout out and a huge "Thank You!" to all of > the people who made

Re: [Mesa-dev] [PATCH v4 13/20] configure.ac, meson: Check for SPIRV-Tools and llvm-spirv

I think it would be valuable to put some comment on what kind of llvm-spirv we really need. I know the situation isn't perfect. Link to your branch or something should be good enough. With that: Reviewed-by: Karol Herbst On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau

Re: [Mesa-dev] [PATCH v4 18/20] clover/api: Implement CL_DEVICE_IL_VERSION

Reviewed-by: Karol Herbst On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote: > Signed-off-by: Pierre Moreau > --- > > Notes: > Changes in v4: Use the core define instead of the extension one (Karol > Herbst) > > v3:

[Mesa-dev] [PATCH] radv: don't lower indirects until after opts have run

Noticed while passing by. nNot sure if it impacts anything, but likely to impact GFX9 more than anything else since we lower inputs, outputs and locals there. --- src/amd/vulkan/radv_shader.c | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH] etnaviv: allow mixing different bit depths for color and depth surfaces

Vivante hardware supports this just fine. There is no reason why this shouldn't be advertised as a valid combination. Signed-off-by: Lucas Stach --- src/gallium/drivers/etnaviv/etnaviv_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Mesa-dev] [PATCH 2/5] radeonsi: expand constbuf 0 address correctly to fix Vega10 hangs

Am 07.03.2018 um 21:34 schrieb Marek Olšák: From: Marek Olšák This is only required with the latest libdrm. This fixes 32-bit support with high addresses. (and possibly 64-bit support too because the high bits need to be masked out) Acked-by: Christian König

Re: [Mesa-dev] [PATCH 1/5] radeonsi: align command buffer starting address to fix some Raven hangs

Am 07.03.2018 um 21:34 schrieb Marek Olšák: From: Marek Olšák Cc: 17.3 18.0 Reviewed-by: Christian König . --- src/amd/common/ac_gpu_info.c | 21 -

Re: [Mesa-dev] [PATCH 3/5] winsys/amdgpu: pad compute rings

Am 07.03.2018 um 21:34 schrieb Marek Olšák: From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 1 file changed, 4 insertions(+) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index

Re: [Mesa-dev] [PATCH v4 05/20] clover: Add an helper for checking if an IR is supported

Reviewed-by: Karol Herbst On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote: > Reviewed-by: Aaron Watry > Signed-off-by: Pierre Moreau > --- > > Notes: > v3: > * Dropped supported_irs() (Francisco

Re: [Mesa-dev] [PATCH v4 06/20] clover/device: Replace usage of "1 << PIPE_SHADER_IR_*" with supports_ir

Reviewed-by: Karol Herbst On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau wrote: > Reviewed-by: Aaron Watry > Signed-off-by: Pierre Moreau > --- > src/gallium/state_trackers/clover/core/device.cpp | 6 +- >

[Mesa-dev] [PATCH v5 0/6] NVIDIA Tegra support

From: Thierry Reding This series of patches implements initial support for Tegra. The first two patches import DRM UAPI from v4.16-rc1 that provides framebuffer modifiers that can be used to specify buffers shared between Nouveau and the Tegra DRM driver. Patches 3 and 4 add

[Mesa-dev] [PATCH v5 5/6] tegra: Initial support

Tegra K1 and later use a GPU that can be driven by the Nouveau driver. But the GPU is a pure render node and has no display engine, hence the scanout needs to happen on the Tegra display hardware. The GPU and the display engine each have a separate DRM device node exposed by the kernel. To make

[Mesa-dev] [PATCH v5 4/6] nouveau: Add framebuffer modifier support

From: Thierry Reding This adds support for framebuffer modifiers to Nouveau. This will be used by the Tegra driver to share metadata about the format of buffers (such as the tiling mode or compression). Changes in v2: - remove unused parameters to nouveau_buffer_create() -

[Mesa-dev] [PATCH v5 3/6] nouveau/nvc0: Extract common tile mode macro

From: Thierry Reding Add a new macro that can be used to extract the tiling mode from a tile_mode value. This is will be used to determine the number of GOBs used in block linear mode. Acked-by: Emil Velikov Tested-by: Andre Heider

[Mesa-dev] [PATCH v5 2/6] drm/tegra: Sanitize format modifiers

From: Thierry Reding The existing format modifier definitions were merged prematurely, and recent work has unveiled that the definitions are suboptimal in several ways: - The format specifiers, except for one, are not Tegra specific, but the names don't reflect that.

[Mesa-dev] [PATCH v5 1/6] drm/fourcc: Fix fourcc_mod_code() definition

From: Thierry Reding Avoid a compiler warnings when the val parameter is an expression. This is based on commit 5843f4e02fbe86a59981e35adc6cabebee46fdc0 from Linux v4.16-rc1. Acked-by: Emil Velikov Tested-by: Andre Heider

[Mesa-dev] [PATCH v5 6/6] autotools: Add tegra to AM_DISTCHECK_CONFIGURE_FLAGS

From: Thierry Reding This allows the driver to be built on a make distcheck and makes sure that it properly builds when a distribution tarball is made. Suggested-by: Emil Velikov Signed-off-by: Thierry Reding --- Makefile.am

Re: [Mesa-dev] [RFC 0/6] Remove stubbed GLX_SGIX_swap_{barrier, group}

On 5 March 2018 at 19:08, Ian Romanick wrote: > On 03/05/2018 10:48 AM, Emil Velikov wrote: >> Hi all, >> >> It seems like these two extensions were never implemented or advertised. >> Be that in: >> - glx/dri >> - glx/apple >> - classic xlib-glx >> - gallium xlib-glx >>

[Mesa-dev] [RFC PATCH 8/9] ac/nir: rework handling of the interpolation parameters

Using the input_interp_{mode,loc} arrays which are filled in ac_shader_info. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 23 --- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [RFC PATCH 7/9] ac/shader: scan if shaders use derivatives texture instructions

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_shader_info.c | 30 ++ src/amd/common/ac_shader_info.h | 1 + 2 files changed, 31 insertions(+) diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c index

[Mesa-dev] [RFC PATCH 9/9] ac/nir: do not always preload PS inputs at beginning

RadeonSI does something similar, the VGPRs decrease is a win but not sure if we really want to implement that. Polaris10: Totals from affected shaders: SGPRS: 116376 -> 116768 (0.34 %) VGPRS: 76556 -> 74868 (-2.20 %) Spilled SGPRs: 10347 -> 10466 (1.15 %) Code Size: 072 -> 5569024 (0.25 %)

[Mesa-dev] [RFC PATCH 5/9] ac/shader: scan flat_shaded_mask

This changes how we index flat_shaded_mask for generic varyings, now it's based on location and not on ps_offset. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 2 -- src/amd/common/ac_nir_to_llvm.h | 1 - src/amd/common/ac_shader_info.c | 5

[Mesa-dev] [RFC PATCH 4/9] ac/shader: scan the input fragment shader masks

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 9 + src/amd/common/ac_nir_to_llvm.h | 1 - src/amd/common/ac_shader_info.c | 5 + src/amd/common/ac_shader_info.h | 2 ++ src/amd/vulkan/radv_pipeline.c | 4 ++-- 5 files changed, 10

[Mesa-dev] [RFC PATCH 6/9] ac/shader: scan if shaders use discard (or kill) instructions

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_shader_info.c | 4 src/amd/common/ac_shader_info.h | 1 + 2 files changed, 5 insertions(+) diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c index fad4245986..c495879280 100644 ---

[Mesa-dev] [RFC PATCH 3/9] ac/shader: count the number of input PS interp

This adds a new level of gathering ("post-analysis") because we have to bump the number of interp when the layer is needed. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 1 - src/amd/common/ac_nir_to_llvm.h | 1 -

[Mesa-dev] [RFC PATCH 2/9] ac/shader: scan uses_persp_{centroid, center}

This allows us to remove one nir_foreach_variable loop. Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 16 ++-- src/amd/common/ac_shader_info.c | 11 --- src/amd/common/ac_shader_info.h | 2 ++ 3 files changed, 12

Re: [Mesa-dev] [RFC 0/6] Remove stubbed GLX_SGIX_swap_{barrier, group}

On 5 March 2018 at 21:05, Brian Paul wrote: > > I'm fine with removing them too. If someone really complains, they can > always be restored. > Seriously doubt it'll happen, yet I fully agree. Small correction: only the Xlib based libGLs expose the API. I'll add a note in the

Re: [Mesa-dev] [PATCH mesa 01/21] vulkan: Add KHR_display extension using DRM [v4]

On Wednesday, 2018-03-07 23:24:59 -0800, Keith Packard wrote: > This adds support for the KHR_display extension support to the vulkan > WSI layer. Driver support will be added separately. > > v2: > * fix double ;; in wsi_common_display.c > > * Move mode list from wsi_display to

[Mesa-dev] [Bug 105171] performance regression (3x slower) running glamor with PutImage workload (radeonsi)

https://bugs.freedesktop.org/show_bug.cgi?id=105171 --- Comment #8 from Clemens Eisserer --- > If somebody wants to improve this, > the place to start is probably glamor rather than the drivers. I wonder, what could glamor do better (especially for small uploads) than

Re: [Mesa-dev] [Mesa-stable] [PATCH] [RFC] gallivm: Use new LLVM fast-math-flags API

[Adding Andres, Juan since they'll be doing the next 17.3] On 7 March 2018 at 16:35, Marek Olšák wrote: > I can test piglit+CTS+deqp on the GPU that I have. (currently Polaris12) > Yes please - that sounds great. If we have more than one device that would be amazing. FTR the

[Mesa-dev] [PATCH v4 2/3] i965: prevent using auxilary buffers when an astc5x5 texture is present

From: Kevin Rogovin If ASTC5x5 textures are present, resolve all textures that the sampler accesses so that auxilary buffer is unneeded when the astc5x5 workaround is needed and also program the sampler state to not use the auxilary buffer as well. Signed-off-by: Kevin

[Mesa-dev] [PATCH v4 1/3] i965: define astx5x5 workaround infrastructure

From: Kevin Rogovin Gen9 GPU's suffer from a HW bug where the GPU will hang if the GPU accesses a texture with a an auxilary buffer and an ASTC5x5 texture without having a pipeline cs stall (and texture cache flush) between such accesses. This patch creates the

[Mesa-dev] [PATCH v4 0/3] i965: ASTC5x5 workaround

From: Kevin Rogovin This patch series implements a needed workaround for Gen9 for ASTC5x5 sampler reads. The crux of the work around is to make sure that the sampler does not read an ASTC5x5 texture and a surface with an auxilary buffer without having a texture cache

[Mesa-dev] [PATCH v4 3/3] i965: ASTC5x5 workaround logic for blorp

From: Kevin Rogovin Signed-off-by: Kevin Rogovin --- src/intel/blorp/blorp.c | 16 src/intel/blorp/blorp.h | 6 ++ src/mesa/drivers/dri/i965/genX_blorp_exec.c | 9 + 3 files

[Mesa-dev] [RFC PATCH 1/9] ac/shader: scan input interp mode and location

Signed-off-by: Samuel Pitoiset --- src/amd/common/ac_nir_to_llvm.c | 9 ++--- src/amd/common/ac_shader_info.c | 12 src/amd/common/ac_shader_info.h | 2 ++ 3 files changed, 16 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [Bug 105171] performance regression (3x slower) running glamor with PutImage workload (radeonsi)

https://bugs.freedesktop.org/show_bug.cgi?id=105171 --- Comment #7 from Michel Dänzer --- (In reply to Clemens Eisserer from comment #6) > This still leaves the question to be answered, how/why the nvidia blob can > be magnitudes faster for XPutImage based workloads. If

[Mesa-dev] [Bug 105396] tc compatible htile sets depth of htiles of discarded fragments to 1.0

https://bugs.freedesktop.org/show_bug.cgi?id=105396 --- Comment #1 from James Legg --- Created attachment 137888 --> https://bugs.freedesktop.org/attachment.cgi?id=137888=edit Source for application used in RenderDoc frame capture -- You are receiving this mail

Re: [Mesa-dev] [PATCH] glx/apple: Ship meson build file in tarball

On Wed, Mar 07, 2018 at 10:08:59AM -0800, Dylan Baker wrote: > Quoting Thierry Reding (2018-03-07 07:55:37) > > From: Thierry Reding > > > > The meson build file for Apple GLX is not listed in the EXTRA_DIST make > > variable and therefore isn't shipped as part of the release

Re: [Mesa-dev] [PATCH 00/56] anv: Add support for Vulkan 1.1

Thanks a lot Jason! As Iago said, we are pleased to had the opportunity to work with you on this :-D Sam On 08/03/18 00:08, Jason Ekstrand wrote: > Hi all, > > I just wanted to give a shout out and a huge "Thank You!" to all of > the people who made this release possible.  There were a large

Re: [Mesa-dev] [PATCH v4 4/6] nouveau: Add framebuffer modifier support

On Wed, Mar 07, 2018 at 01:15:35PM -0500, Ilia Mirkin wrote: > On Wed, Mar 7, 2018 at 10:53 AM, Thierry Reding > wrote: > > From: Thierry Reding > > > > This adds support for framebuffer modifiers to Nouveau. This will be > > used by the Tegra driver

Re: [Mesa-dev] [Mesa-stable] [PATCH] i965/vec4: use a temp register to compute offsets for pull loads

On Wed, 2018-02-21 at 08:40 +0100, Iago Toral wrote: > Yes, I agree, thanks for bringing it up. > > Iago > Thanks. I'm including it in next 17.3 release. BTW, this patch was also included in 17.2.8. J.A. > On Tue, 2018-02-20 at 16:38 +0200, Andres Gomez wrote: > > Iago, this looks

[Mesa-dev] [Bug 105396] tc compatible htile sets depth of htiles of discarded fragments to 1.0

https://bugs.freedesktop.org/show_bug.cgi?id=105396 Bug ID: 105396 Summary: tc compatible htile sets depth of htiles of discarded fragments to 1.0 Product: Mesa Version: git Hardware: Other OS: All

[Mesa-dev] [PATCH] radv: Unset ZRANGE_PRECISION when depth was zeroed

This avoids bug 105396 somehow. I suspect it is a VI and GFX9 hardware bug which PAL calls WaTcCompatZRange, but I don't know for sure. In the VK_FORMAT_D32_SFLOAT case, TILE_STENCIL_DISABLE is not set for tc compatible image formats regardless of not having a stencil aspect. If

[Mesa-dev] [Bug 105171] performance regression (3x slower) running glamor with PutImage workload (radeonsi)

https://bugs.freedesktop.org/show_bug.cgi?id=105171 --- Comment #6 from Clemens Eisserer --- Strange, after tinkering around with my system, I cannot reproduce the issue anymore. Even with Mesa-17.3.x x11perf -shnmput10 is now at ~70-80kOps/s - so maybe it was a

Re: [Mesa-dev] [Mesa-stable] [PATCH] program: Don't reset SamplersValidated when restoring from shader cache

On Tue, 2018-02-20 at 13:47 -0800, Jordan Justen wrote: > On 2018-02-20 06:46:24, Andres Gomez wrote: > > Jordan, this looks like a good candidate to nominate for inclusion in > > the 17.3 stable queue. > > > > What do you think? > > I saw this on i965, which does not have shader cache support

Re: [Mesa-dev] [PATCH 07/16] radv: Implement VK_KHR_maintenance3.

On 7 March 2018 at 19:56, Emil Velikov wrote: > On 7 March 2018 at 18:32, Bas Nieuwenhuizen wrote: > >>> >>> Missing break? >> >> So much for the tests ... >> > Speaking of tests, I hope they check that both KHR and non KHR > annotated

[Mesa-dev] [v4 PATCH 3/6] spirv_extensions: add list of extensions and to_string method

Ideally this should be generated somehow. One option would be gather all the extension dependencies listed on the core grammar, but there would be the possibility of not including some of the extensions. Note that spirv-tools is doing it just slightly better, as it has a hardcoded list of

[Mesa-dev] [v4 PATCH 4/6] spirv_extensions: define spirv_extensions_supported

Add a struct to maintain which SPIR-V extensions are supported, and an utility method to initialize it based on nir_spirv_supported_capabilities. v2: * Fixing code style (Ian Romanick) * Adding a prefix (spirv) to fill_supported_spirv_extensions (Ian Romanick) v3: rebase update

[Mesa-dev] [v2 PATCH 5/6] spirv_extensions: add spirv_supported_extensions on gl_constants

We can use it to get real values for ARB_spirv_extensions methods. v2: Rebase update after changes on previous patches. --- src/mesa/main/mtypes.h | 3 +++ src/mesa/main/spirv_extensions.c | 20 +++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [v2 PATCH 6/6] spirv_extensions: i965: initialize SPIR-V extensions

v2: Rebase update after changes on previous patches. --- src/mesa/drivers/dri/i965/brw_context.c | 10 +- src/mesa/main/context.c | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c

[Mesa-dev] [v4 PATCH 1/6] spirv_extensions: add GL_ARB_spirv_extensions boilerplate

v2: * Mention extension gap at gl_API.xml (Emil Velikov) * Bail with INVALID_ENUM if extension not available on getStringi (Emil Velikov) * Use EXTRA_EXT macro when defining the extension at get.c/get_hash_params.py (Emil Velikov) * Rename source files (spirvextensions.[ch] ->

[Mesa-dev] [PATCH 2/6] spirv/radv: add AMD_gcn_shader capability, remove current extensions

So now, during spirv_to_nir, it uses the capability instead of the extension. Note that we are really doing here is treating SPV_AMD_gcn_shader as other supported extensions. SPV_AMD_gcn_shader is not the first SPV extension supported. For example, the capability draw_parameters infers if the

[Mesa-dev] [v5 PATCH 0/6] ARB_spirv_extensions support in Mesa and i965

Hi, This series is the latest version of the support for ARB_spirv_extensions on i965. The patches are basically the same that v4 series we sent some time ago. This is rebased against master and updated due the changes for the support of SPV_AMD_gcn_shader (sorry for missing that one). So it

[Mesa-dev] [PATCH 1/2] nir: add nir_opt_move_load_ubo() optimization pass

This pass moves load UBO operations just before their first use, loosely based on nir_opt_move_comparisons. Signed-off-by: Samuel Pitoiset --- src/compiler/Makefile.sources| 1 + src/compiler/nir/meson.build | 1 + src/compiler/nir/nir.h

[Mesa-dev] [PATCH 2/2] radv: run nir_opt_move_load_ubo

Polaris10: Totals from affected shaders: SGPRS: 106656 -> 105952 (-0.66 %) VGPRS: 73464 -> 73400 (-0.09 %) Spilled SGPRs: 7121 -> 6861 (-3.65 %) Code Size: 4157792 -> 4158716 (0.02 %) bytes Max Waves: 9316 -> 9330 (0.15 %) Vega10: Totals from affected shaders: SGPRS: 106720 -> 106032 (-0.64 %)

[Mesa-dev] [PATCH v4 15/18] anv: Emit the fast clear color address, instead of value.

On Gen10+, instead of copying the clear color from the state buffer to the surface state, just use the address of the state buffer in the surface state directly. This way we can avoid the copy from state buffer to surface state. v4: - Remove use_clear_address from anv code. (Jason) - Use the

[Mesa-dev] [PATCH v4 08/18] intel/blorp: Update clear color state buffer during fast clears.

We always want to update the fast clear color during a fast clear on i965. On anv, we doing that before a resolve, but by adding support to blorp, we can do a similar thing and update it during a fast clear instead. The goal is to remove some code from anv that does such update, and centralize

[Mesa-dev] [PATCH v4 09/18] i965/miptree: Add space to store the clear value in the aux surface.

Similarly to vulkan where we store the clear value in the aux surface, we can do the same in GL. v2: Remove unneeded extra function. v3: Use clear_value_state_size instead of clear_value_size. v4: - rename to clear_color_state_size - store clear_color_bo and clear_color_offset in the aux buf

[Mesa-dev] [PATCH v4 03/18] intel/genxml: Use a single field for clear color address on gen10.

genxml does not support having two address fields with different names but same position in the state struct. Both "Clear Color Address" and "Clear Depth Address Low" mean the same thing, only for different surface types. To workaround this genxml limitation, rename "Clear Color Address" to

[Mesa-dev] [PATCH v4 17/18] anv: Make blorp update the clear color.

Instead of updating the clear color in anv before a resolve, just let blorp handle that for us during fast clears. Signed-off-by: Rafael Antognolli --- src/intel/vulkan/anv_blorp.c | 69 +++--- src/intel/vulkan/anv_private.h

[Mesa-dev] [PATCH v4 16/18] anv: Use clear address for HiZ fast clears too.

Store the default clear address for HiZ fast clears on a global bo, and point to it when needed. Signed-off-by: Rafael Antognolli --- src/intel/vulkan/anv_device.c | 19 +++ src/intel/vulkan/anv_image.c | 10 +++---

[Mesa-dev] [PATCH v4 07/18] intel/blorp: Only copy clear color when doing a resolve.

We only need to copy the clear color from the state buffer to the inlined surface state when doing a resolve. Signed-off-by: Rafael Antognolli --- src/intel/blorp/blorp_genX_exec.h | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git

[Mesa-dev] [PATCH v4 01/18] anv/image: Do not override lower bits of dword.

The lower bits seem to have extra fields in every platform but gen8 (even though we don't use them in gen9). So just go ahead and avoid using them for the address. v4: Use Jason's suggestion for comment explaining the change. Signed-off-by: Rafael Antognolli

Re: [Mesa-dev] nouveau 30bpp / deep color status

Cc'ing mesa-dev, which was left out. On 03/05/2018 01:40 PM, Ilia Mirkin wrote: On Mon, Mar 5, 2018 at 2:25 AM, Mario Kleiner wrote: On 02/05/2018 12:50 AM, Ilia Mirkin wrote: In case anyone's curious about 30bpp framebuffer support, here's the current status:

Re: [Mesa-dev] nouveau 30bpp / deep color status

On Thu, Mar 8, 2018 at 11:57 AM, Mario Kleiner wrote: > Cc'ing mesa-dev, which was left out. > > > On 03/05/2018 01:40 PM, Ilia Mirkin wrote: >> >> On Mon, Mar 5, 2018 at 2:25 AM, Mario Kleiner >> wrote: >>> Afaics EGL does the right thing

[Mesa-dev] [PATCH 3/3] vulkan: autotools: do not redirect stdin/stdout for wayland-scanner

From: Emil Velikov The tool accepts the input and output files as arguments. There's no need for the redirection. Signed-off-by: Emil Velikov --- src/vulkan/Makefile.am | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff

[Mesa-dev] [PATCH 2/3] wayland-drm: autotools: do not redirect stdin/stdout for wayland-scanner

From: Emil Velikov The tool accepts the input and output files as arguments. There's no need for the redirection. Signed-off-by: Emil Velikov --- src/egl/wayland/wayland-drm/Makefile.am | 6 +++--- 1 file changed, 3 insertions(+), 3

[Mesa-dev] [PATCH 1/3] egl: autotools: do not redirect stdin/stdout for wayland-scanner

From: Emil Velikov The tool accepts the input and output files as arguments. There's no need for the redirection. Signed-off-by: Emil Velikov --- src/egl/Makefile.am | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 04/56] anv/entrypoints: Generalize the string map a bit

On 7 March 2018 at 14:34, Jason Ekstrand wrote: > The original string map assumed that the mapping from strings to > entrypoints was a bijection. This will not be true the moment we > add entrypoint aliasing. This reworks things to be an arbitrary map > from strings to

Re: [Mesa-dev] [PATCH 3/3] meson: make GLX_USE_TLS optional

On 8 March 2018 at 18:12, Eric Anholt wrote: > Greg V writes: > >> FreeBSD builds Mesa with --disable-glx-tls in autotools because: >> https://github.com/dumbbell/test-tls-initial-exec >> >> Add the equivalent option to Meson. >> --- >> meson.build

Re: [Mesa-dev] [PATCH 2/5] radeonsi: expand constbuf 0 address correctly to fix Vega10 hangs

On Wed, Mar 7, 2018 at 3:34 PM, Marek Olšák wrote: > From: Marek Olšák > > This is only required with the latest libdrm. > > This fixes 32-bit support with high addresses. > (and possibly 64-bit support too because the high bits need to be masked out)

Re: [Mesa-dev] [PATCH 2/3] meson: use relative paths in megadriver symlinks

Quoting Greg V (2018-03-06 11:16:04) > e.g. libvdpau_radeonsi.so(.1(.0)) were pointing to the absolute > build-time path of libvdpau_radeonsi.so.1.0.0, which caused trouble > when packaging the libraries. > --- > bin/install_megadrivers.py | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >

[Mesa-dev] [PATCH v4 04/18] intel/genxml: Add Clear Color struct.

The size of the clear color struct (expected by the hardware) is 8 dwords (isl_dev.ss.clear_value_state_size here). But we still need to track the size of the clear color, used when memcopying it to/from the state buffer. For that we keep isl_dev.ss.clear_value_size. v4: - Add struct to gen11

[Mesa-dev] [PATCH v4 14/18] anv: Add a helper to extract clear color from the attachment.

Extract the code from color_attachment_compute_aux_usage, so we can later reuse it to update the clear color state buffer. Signed-off-by: Rafael Antognolli --- src/intel/vulkan/anv_private.h | 20 src/intel/vulkan/genX_cmd_buffer.c | 14

[Mesa-dev] [PATCH v4 05/18] intel/isl: Add support to emit clear value address.

gen10 can emit the clear color by setting it on a buffer somewhere, and then adding only the address to the surface state. This commit add support for that on isl_surf_fill_state, and if that is requested, skip setting the clear value itself. v2: Add assert to make sure we are at least on gen10.

[Mesa-dev] [PATCH v4 00/18] Use clear color address in surface state.

New revision of this series. Major differences are: - I tried to incorporate most of the review feedback. - While adding some code in i965 to update the clear color state buffer, I seemd to avoid some bugs by actually doing it in blorp. However, anv already updates the same buffer, so in

[Mesa-dev] [PATCH v4 13/18] i965/surface_state: Emit the clear color address instead of value.

On Gen10, when emitting the surface state, use the value stored in the clear color entry buffer by using a clear color address in the surface state. v4: Use the clear color offset from the clear_color_bo, when available. Signed-off-by: Rafael Antognolli ---

[Mesa-dev] [PATCH v4 02/18] genxml: Preserve fields that share dword space with addresses.

Some instructions contain fields that are either an address or a value of some type based on the content of other fields, such as clear color values vs address. That works fine if these fields are in the less significant dword, the lower 32 bits of the address, because they get OR'ed with the

[Mesa-dev] [PATCH v4 06/18] intel/blorp: Add support for fast clear address.

On gen10+, if surface->clear_color_addr is present, use it directly intead of copying it to the surface state. v4: Remove redundant #if clause for GEN <= 10 (Jason) Signed-off-by: Rafael Antognolli Reviewed-by: Jason Ekstrand ---

Re: [Mesa-dev] [PATCH 3/5] winsys/amdgpu: pad compute rings

On Thu, Mar 8, 2018 at 11:51 AM, Marek Olšák wrote: > From: Marek Olšák > > v2: pad with PKT2 NOPs on SI Reviewed-by: Alex Deucher > --- > src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 4 +++- > 1 file changed, 3 insertions(+),

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