Re: [Mesa-dev] [PATCH 1/3] vulkan: Define new VK_MESA_query_timestamp extension [v2]

On Tue, 10 Jul 2018 11:02:23 -0700 "Keith Packard" wrote: > Pekka Paalanen writes: > > > On Sat, 23 Jun 2018 12:13:53 -0500 > > Jason Ekstrand wrote: > > > >> I haven't thought through this comment all that hard but would it make > >> sense to have three timestamps, CPU, GPU, CPU so that

[Mesa-dev] [PATCH 02/10] nir: evaluate loop terminator condition uses

For simple loop terminators we can evaluate all further uses of the condition in the loop because we know we must have either exited the loop or we have a known value. shader-db results IVB (all changes from dolphin uber shaders): total instructions in shared programs: 10022822 -> 10018187

[Mesa-dev] [PATCH 03/10] nir: allow more nested loops to be unrolled

The innermost check was added to stop us from unrolling multiple loops in a single pass, and to stop outer loops from unrolling. When we successfully unroll a loop we need to run the analysis pass again before deciding if we want to go ahead an unroll a second loop. However the logic was flawed

[Mesa-dev] Loop unrolling and if statement opts

This series started out as me trying to unrolls some useless loops I spotted in some shaders from DXVK games (see patch 10), but I found some other issues and improvements along the way. The biggest winner seem like it could be the dolphin uber shaders on i965 (on radeonsi the shaders don't seem

[Mesa-dev] [PATCH 05/10] nir: add complex_loop bool to loop info

In order to be sure loop_terminator_list is an accurate representation of all the jumps in the loop we need to be sure we didn't encounter any other complex behaviour such as continues, nested breaks, etc during analysis. This will be used in the following patch. --- src/compiler/nir/nir.h

[Mesa-dev] [PATCH 01/10] nir: evaluate if condition uses inside the if branches

Since we know what side of the branch we ended up on we can just replace the use with a constant. All helped shaders are from Unreal Engine 4 besides one shader from Dirt Showdown. shader-db results SKL: total instructions in shared programs: 13219725 -> 13219643 (<.01%) instructions in

[Mesa-dev] [PATCH 08/10] nir: add loop unroll support for complex wrapper loops

In GLSL IR we cheat with switch statements and simply convert them into loops with a single iteration. This allowed us to make use of the existing jump instruction handling provided by the loop handing code, it also allows dead code to be cleaned up once we have wrapped the code in a loop.

[Mesa-dev] [PATCH 09/10] nir: evaluate loop terminator ior use

Here we replace one side of the ior with NIR_TRUE if the src is a loop terminators condition that we know can only be true. No shader-db change. --- src/compiler/nir/nir_opt_if.c | 28 +--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 10/10] nir: evaluate loop terminator ior use when false

This allows some loops to unroll were they are guaranteed to exit after the first iteration. For example: loop { block block_1: /* preds: block_0 block_13 */ vec1 32 ssa_85 = load_const (0x0002 /* 0.00 */) vec1 32

[Mesa-dev] [PATCH 06/10] nir/opt_loop_unroll: Remove unneeded phis if we make progress

Now that SSA values can be derefs and they have special rules, we have to be a bit more careful about our LCSSA phis. In particular, we need to clean up in case LCSSA ended up creating a phi node for a deref. This avoids validation issues with some CTS tests with the new patch, but its possible

[Mesa-dev] [PATCH 07/10] nir: add loop unroll support for wrapper loops

This adds support for unrolling the classic do { // ... } while (false) that is used to wrap multi-line macros. GLSL IR also wraps switch statements in a loop like this. shader-db results IVB: total loops in shared programs: 2515 -> 2512 (-0.12%) loops in affected programs: 33

[Mesa-dev] [PATCH 04/10] nir: always attempt to find loop terminators

This will help later patches with unrolling loops that end with a break i.e. loops the always exit on their first interation. --- src/compiler/nir/nir_loop_analyze.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/compiler/nir/nir_loop_analyze.c

Re: [Mesa-dev] [PATCH] r600: Add spill output to group only if register or target index changes

Am Dienstag, den 10.07.2018, 23:25 +0200 schrieb Roland Scheidegger: ... thanks for the review, > > I'm not really too familiar with this code, but makes sense to me. > Are there piglit or dEPQ or whatever failures associated with this? > If so you could mention them in the commit log. The

Re: [Mesa-dev] [PATCH] radv: using tls to store llvm related info and speed up compiles (v9)

Hi Dave, -Ursprüngliche Nachricht- Von: mesa-dev Im Auftrag von Dave Airlie Gesendet: Montag, 9. Juli 2018 23:15 An: mesa-dev@lists.freedesktop.org Betreff: [Mesa-dev] [PATCH] radv: using tls to store llvm related info and speed up compiles (v9) From: Dave Airlie This uses the

Re: [Mesa-dev] [PATCH] i965/tex: ignore the diff between GL_TEXTURE_2D and GL_TEXTURE_RECTANGLE

Hi, On Tue, 10 Jul 2018 at 18:56, Jason Ekstrand wrote: > > Ugh... not so good. According to Oliver on the bug, this just make the > assert go away and doesn't actually fix anything. Likely this is needed but > not sufficient. Well, maybe not even needed, at least in my case I don't hit

Re: [Mesa-dev] How to apply patches to upstream mesa 9.0.3

On 11. juli 2018 10:22, Thella Shyam Kumar wrote: Hi All, We are using an x86 based platform and we are needing changes in mesa 9.0.3 which is coming with AOSP 7.1.2r36 If we want the changes in mesa in AOSP, our understanding is that these changes should be upstreamed in freedesktop.org

[Mesa-dev] How to apply patches to upstream mesa 9.0.3

Hi All, We are using an x86 based platform and we are needing changes in mesa 9.0.3 which is coming with AOSP 7.1.2r36 If we want the changes in mesa in AOSP, our understanding is that these changes should be upstreamed in freedesktop.org's mesa 9.0.3 because AOSP gets the code from there. So

Re: [Mesa-dev] [PATCH v2 25/49] docs/meson.html: fix numerous issues spotted by xmllint

On 11. juli 2018 01:17, Dylan Baker wrote: --- docs/meson.html | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) This is a HTML-document, not an XML document or XHTML. What xmllint thinks should be irrelevant. diff --git a/docs/meson.html b/docs/meson.html index

Re: [Mesa-dev] [PATCH v2 41/49] meosn: don't build gallium trivial tests on windows

Typo in the subject, "meosn" -> "meson". On 11. juli 2018 01:18, Dylan Baker wrote: They require the pipe-loaders, which require xmlconfig, which doesn't build with msvc. --- src/gallium/tests/meson.build | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git

Re: [Mesa-dev] Loop unrolling and if statement opts

Hi, On 11.07.2018 12:00, Timothy Arceri wrote: On 11/07/18 18:20, Eero Tamminen wrote: Have you considered partial loop unrolling support? I.e. when loop counter is known, but too high for full unroll, doing partial loop unrolling (e.g. unroll 4x times) and dividing loop counter by same

Re: [Mesa-dev] [PATCH v3] radv: make sure to wait for CP DMA when needed

Reviewed-by: Bas Nieuwenhuizen On Mon, Jul 9, 2018 at 6:02 PM, Samuel Pitoiset wrote: > This might fix some synchronization issues. I don't know if > that will affect performance but it's required for correctness. > > v3: - wait for CP DMA in CmdPipelineBarrier() > - clear the busy value

Re: [Mesa-dev] Loop unrolling and if statement opts

On 11/07/18 18:20, Eero Tamminen wrote: Hi, Have you considered partial loop unrolling support? I.e. when loop counter is known, but too high for full unroll, doing partial loop unrolling (e.g. unroll 4x times) and dividing loop counter by same amount (if it didn't divide evenly, need to

Re: [Mesa-dev] Loop unrolling and if statement opts

On 11/07/18 19:45, Eero Tamminen wrote: Hi, On 11.07.2018 12:00, Timothy Arceri wrote: On 11/07/18 18:20, Eero Tamminen wrote: Have you considered partial loop unrolling support? I.e. when loop counter is known, but too high for full unroll, doing partial loop unrolling (e.g. unroll 4x

Re: [Mesa-dev] Loop unrolling and if statement opts

Hi, Have you considered partial loop unrolling support? I.e. when loop counter is known, but too high for full unroll, doing partial loop unrolling (e.g. unroll 4x times) and dividing loop counter by same amount (if it didn't divide evenly, need to unroll remainder outside of loop). This

Re: [Mesa-dev] [PATCH v2 4/4] radv: add support for VK_EXT_conditional_rendering

Don't we need to disable predication too for the PipelineBarriers when a layout change happens? Also in cases the barrier or a blit/copy does different predication, do we not need to do si_emit_set_predication_state again as the state was overridden? On Mon, Jul 9, 2018 at 2:57 PM, Samuel

Re: [Mesa-dev] [PATCH v2 2/3] nir: Add a discard optimization pass

Hi, On 06.07.2018 00:28, Jason Ekstrand wrote: On Thu, Jul 5, 2018 at 2:18 PM, Jason Ekstrand > wrote: [...] >> Optimizing for the latter case is an essentially >> heuristic assumption that needs to be verified experimentally.  Have you >>

[Mesa-dev] [PATCH] radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9

A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion counters) must immediately precede every timestamp event to prevent a GPU hang on GFX9. Signed-off-by: Samuel Pitoiset Cc: 18.1 --- src/amd/vulkan/radv_cmd_buffer.c | 15 +-- src/amd/vulkan/radv_device.c | 4 ++--

Re: [Mesa-dev] [PATCH] i965/miptree: Allocate MS texture BOs as BUSY

On Fri, Jul 06, 2018 at 03:39:26PM -0700, Nanley Chery wrote: > These buffer objects are never accessed with the CPU. Reviewed-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git

[Mesa-dev] [Bug 106861] fatal error: wayland-egl-backend.h: No such file or directory compilation terminated.

https://bugs.freedesktop.org/show_bug.cgi?id=106861 Eero Tamminen changed: What|Removed |Added Status|RESOLVED|VERIFIED -- You are receiving this

[Mesa-dev] [PATCH] intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.

SNB doesn't have a difinition of 3DSTATE_CONSTANT_BODY, thats why we got segmentation fault when used INTEL_DEBUG=bat. Fixed by avoiding parsing of 3DSTATE_CONSTANT_BODY if gen_spec is not observed. Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.) Bugzilla:

Re: [Mesa-dev] [PATCH] radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9

Assuming you confirmed this fixed something: Reviewed-by: Bas Nieuwenhuizen On Wed, Jul 11, 2018 at 11:55 AM, Samuel Pitoiset wrote: > A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion > counters) must immediately precede every timestamp event to > prevent a GPU hang on GFX9. > >

Re: [Mesa-dev] [PATCH] radv: emit a dummy ZPASS_DONE to prevent GPU hangs on GFX9

On 07/11/2018 01:56 PM, Bas Nieuwenhuizen wrote: Assuming you confirmed this fixed something: This doesn't fix anything known. Reviewed-by: Bas Nieuwenhuizen On Wed, Jul 11, 2018 at 11:55 AM, Samuel Pitoiset wrote: A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion counters)

[Mesa-dev] [PATCH v2 1/3] i965: Sweep NIR after linking phase to free held memory

After optimization passes and many trasfromations most of memory NIR holds is a garbage which was being freed only after shader deletion. Freeing it at the end of linking will save memory which would be useful in case there are a lot of complex shaders being compiled. The common case for this

Re: [Mesa-dev] [PATCH 00/13] Fix stencil texturing and BO caching bugs

On Fri, Jul 06, 2018 at 01:29:29PM -0700, Nanley Chery wrote: > On Fri, Jul 06, 2018 at 03:36:01PM +0300, Pohjolainen, Topi wrote: > > On Tue, Jun 12, 2018 at 12:21:52PM -0700, Nanley Chery wrote: > > > This series fixes a couple stencil texturing bugs on HSW and > > > cache-tracking for certain

[Mesa-dev] [Bug 107169] [regression] Upgrade from 18.0.4 to 18.1.0 causes severe stuttering in games

https://bugs.freedesktop.org/show_bug.cgi?id=107169 Denis changed: What|Removed |Added Status|NEW |NEEDINFO --- Comment #1 from Denis --- hi.

[Mesa-dev] [Bug 107169] [regression] Upgrade from 18.0.4 to 18.1.0 causes severe stuttering in games

https://bugs.freedesktop.org/show_bug.cgi?id=107169 --- Comment #2 from Stan Staykov --- (In reply to Denis from comment #1) > hi. Could you plz clarify, what System Shock game you meant? New one, which > wasn't released yet? Or some old game? > Asking because I found demo of new one - >

Re: [Mesa-dev] [PATCH 09/26] python: Use range() instead of xrange()

I've sent 4-9 to our CI, and assuming that it comes back green I'll go ahead and merge those patches today. Quoting Mathieu Bridon (2018-07-05 06:17:40) > Python 2 has a range() function which returns a list, and an xrange() > one which returns an iterator. > > Python 3 lost the function

Re: [Mesa-dev] [RFC] i965/fs: Generalize grf127 hack to dispatch_width > 8

Hi, Thanks for the explanations :-) > > - ra_set_node_reg(g, grf127_send_hack_node, 127); > > + ra_set_node_reg(g, grf127_send_hack_node, 128 - reg_width); > > This configuration is more restrictive than needed. The original code > just avoids any register with any length that uses

Re: [Mesa-dev] [RFC] i965/fs: Generalize grf127 hack to dispatch_width >

> > diff --git a/src/intel/compiler/brw_fs_reg_allocate.cpp > > b/src/intel/compiler/brw_fs_reg_allocate.cpp > > index 59e047483c0..417ddeba09c 100644 > > --- a/src/intel/compiler/brw_fs_reg_allocate.cpp > > +++ b/src/intel/compiler/brw_fs_reg_allocate.cpp > > @@ -549,7 +549,7 @@

Re: [Mesa-dev] [PATCH] vulkan: Fix compilation on older platforms

Quoting Danylo Piliaiev (2018-07-11 04:26:03) > diff --git a/meson.build b/meson.build > index 7d12af3d51..2683060827 100644 > --- a/meson.build > +++ b/meson.build > @@ -1088,6 +1088,8 @@ _drm_freedreno_ver = '2.4.92' > _drm_intel_ver = '2.4.75' > _drm_ver = '2.4.75' > >

Re: [Mesa-dev] [Mesa-stable] [PATCH v3] radv: make sure to wait for CP DMA when needed

Quoting Samuel Pitoiset (2018-07-09 09:02:58) > This might fix some synchronization issues. I don't know if > that will affect performance but it's required for correctness. > > v3: - wait for CP DMA in CmdPipelineBarrier() > - clear the busy value when CP_DMA_SYNC is requested > v2: - wait

Re: [Mesa-dev] [PATCH v2 25/49] docs/meson.html: fix numerous issues spotted by xmllint

Quoting Erik Faye-Lund (2018-07-11 00:39:37) > On 11. juli 2018 01:17, Dylan Baker wrote: > > --- > > docs/meson.html | 5 ++--- > > 1 file changed, 2 insertions(+), 3 deletions(-) > > This is a HTML-document, not an XML document or XHTML. What xmllint > thinks should be irrelevant. I would

Re: [Mesa-dev] [PATCH 1/3] egl/android: Delete set_damage_region from egl dri vtbl

Hi Eric, Eric Anholt writes: > Harish Krupo writes: > >> The intension of the KHR_partial_update was not to send the damage back >> to the platform but to send the damage to the driver to ensure that the >> following rendering could be restricted to those regions. >> This patch removes the

[Mesa-dev] [PATCH v2 10/26] python: Use explicit integer divisions

In Python 2, divisions return an integer: >>> 32 / 4 8 In Python 3 though, they return floats: >>> 32 / 4 8.0 However, Python 3 has an explicit integer division operator: >>> 32 // 4 8 That operator exists on Python >= 2.2, so let's use it everywhere to make the

[Mesa-dev] [PATCH 11/26] python: Fix rich comparisons

Python 3 lost the cmp() builtin, and doesn't call objects __cmp__() methods any more to compare them. Instead, Python 3 requires implementing the rich comparison methods explicitly: __eq__(), __ne(), __lt__(), __le__(), __gt__() and __ge__(). Fortunately those are trivial to implement by just

Re: [Mesa-dev] [PATCH] intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY.

On Wednesday, July 11, 2018 4:43:52 AM PDT Sergii Romantsov wrote: > SNB doesn't have a difinition of 3DSTATE_CONSTANT_BODY, thats > why we got segmentation fault when used INTEL_DEBUG=bat. > Fixed by avoiding parsing of 3DSTATE_CONSTANT_BODY if gen_spec > is not observed. > > Fixes: 169d8e011ae

[Mesa-dev] [PATCH 1/2] intel: Make the disassembler take a const pointer to the assembly.

Disassembling doesn't modify the assembly. --- src/intel/common/gen_disasm.c | 7 --- src/intel/common/gen_disasm.h | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/intel/common/gen_disasm.c b/src/intel/common/gen_disasm.c index 1de20f576d4..4f835c19883 100644 ---

[Mesa-dev] [PATCH 2/2] intel: Make the decoder handle STATE_BASE_ADDRESS not being a buffer.

Normally, i965 programs STATE_BASE_ADDRESS every batch, and puts all state for a given base in a single buffer. I'm working on a prototype which emits STATE_BASE_ADDRESS only once at startup, where each base address is a fixed 4GB region of the PPGTT. State may live in many buffers in that 4GB

[Mesa-dev] [PATCH] vulkan: Fix compilation on older platforms

Make xlease automatically enabled only if xcb-randr >= 1.13, check its version if manually enabled. Enable VK_EXT_display_control only when libdrm >= 2.4.89 Check for DRM_EVENT_CONTEXT_VERSION >= 4 to use sequence_handler. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107170

Re: [Mesa-dev] [PATCH 2/9] i965/fs: Register allocator shoudn't use grf127 for sends dest

Including mesa-dev in my previous reply. El 11/07/18 a las 01:08, Caio Marcelo de Oliveira Filho escribió: >> Since Gen8+ Intel PRM states that "r127 must not be used for return >> address when there is a src and dest overlap in send instruction." > > The previous patch, that verifies the

[Mesa-dev] [Bug 107170] Build fails if building against X server/libxrandr with no leases support

https://bugs.freedesktop.org/show_bug.cgi?id=107170 Danylo changed: What|Removed |Added CC||danylo.pilia...@gmail.com --- Comment #1 from

Re: [Mesa-dev] [PATCH 1/3] vulkan: Define new VK_MESA_query_timestamp extension [v2]

Pekka Paalanen writes: > I did not mean you would be solving that problem. I meant that it would > be good to figure out what people actually want from the API to be able > to solve the problem themselves. Thanks for the clarification. I'd suggest that we not try and solve that problem until we

Re: [Mesa-dev] [RFC] i965/fs: Generalize grf127 hack to dispatch_width > 8

El 11/07/18 a las 03:50, Caio Marcelo de Oliveira Filho escribió: > Change the hack to always apply, adjusting the register number > according to the dispatch_width. > > The original change assumed that given for dispatch_width > 8 we > already prevent the overlap of source and destination for

Re: [Mesa-dev] [PATCH 1/3] egl/android: Delete set_damage_region from egl dri vtbl

Harish Krupo writes: > The intension of the KHR_partial_update was not to send the damage back > to the platform but to send the damage to the driver to ensure that the > following rendering could be restricted to those regions. > This patch removes the set_damage_region from the egl_dri vtbl

[Mesa-dev] [PATCH 2/2] nv50/ir: don't rely on inbound edge order in phi nodes

Previously, a phi node's sources were implicitly ordered by the inbound edge order. This changes that so that a phi node instead has a basic block stored for each source in a deque. Signed-off-by: Rhys Perry --- src/gallium/drivers/nouveau/codegen/nv50_ir.cpp| 20 +-

[Mesa-dev] [PATCH 0/2] nv50/ir: create PhiInstruction

This series it based off the "nv50/ir: don't rely on inbound edge order in phi nodes" series. It differs in that it creates BaseInstruction, a class that both PhiInstruction and Instruction inherit from. This is so that it's more difficult to create incorrect phi instructions. It's rather large,

[Mesa-dev] [PATCH] i965/fs: unspills shoudn't use grf127 as dest since Gen8+

At 232ed8980217dd65ab0925df28156f565b94b2e5 "i965/fs: Register allocator shoudn't use grf127 for sends dest" we didn't take into account the case of SEND instructions that are not send_from_grf. But since Gen7+ although the backend still uses MRFs internally for sends they are finally asigned to a

Re: [Mesa-dev] [PATCH v2] egl: Fix missing clamping in eglSetDamageRegionKHR

Harish Krupo writes: > Clamp the x and y co-ordinates of the rectangles. > > v2: Clamp width/height after converting to co-ordinates > (Ilia Merkin) > > Signed-off-by: Harish Krupo > --- > src/egl/main/eglapi.c | 25 +++-- > 1 file changed, 11 insertions(+), 14

Re: [Mesa-dev] [PATCH 1/2] mesa: MESA_framebuffer_flip_y extension [v3]

+Ken, I had a question about GLboolean. I call you by name in the comments below. On Fri 29 Jun 2018, Fritz Koenig wrote: > Adds an extension to glFramebufferParameteri > that will specify if the framebuffer is vertically > flipped. Historically system framebuffers are > vertically flipped and

[Mesa-dev] [PATCH] radeonsi: add support for Vega20

From: Marek Olšák --- include/pci_ids/radeonsi_pci_ids.h | 7 +++ src/amd/addrlib/amdgpu_asic_addr.h | 2 ++ src/amd/addrlib/gfx9/gfx9addrlib.cpp| 3 ++- src/amd/addrlib/gfx9/gfx9addrlib.h | 1 + src/amd/common/ac_llvm_util.c

Re: [Mesa-dev] [PATCH 2/2] u_blitter: Add an option to draw the triangles using an index buffer.

Am 12.07.2018 um 00:05 schrieb Eric Anholt: > For V3D, the HW will interpolate slightly differently along the shared > edge of the trifan. The conformance tests manage to catch this in the > nearest_consistency_* group. To get interpolation to match, we need the > last vertex of the triangle to

[Mesa-dev] [PATCH 7/9] radeonsi: rework RADEON_PRIO flags to be <= 31

From: Marek Olšák This decreases sizeof(struct amdgpu_cs_buffer) from 24 to 16 bytes. --- src/gallium/drivers/radeon/radeon_winsys.h| 39 ++- src/gallium/drivers/radeonsi/si_debug.c | 2 +- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 +--

[Mesa-dev] [PATCH 2/9] winsys/amdgpu: always update gfx_bo_list_counter

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 9aa489adaa4..77b372d2cea 100644 ---

[Mesa-dev] [PATCH 5/9] radeonsi: remove non-GFX BO priority flags

From: Marek Olšák For a later simplification. --- src/gallium/drivers/radeon/radeon_uvd.c | 3 +-- src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 2 +- src/gallium/drivers/radeon/radeon_vce.c | 2 +- src/gallium/drivers/radeon/radeon_vcn_dec.c | 2 +-

[Mesa-dev] [PATCH 9/9] winsys/amdgpu: pass the BO list via the CS ioctl on DRM >= 3.27.0

From: Marek Olšák TODO: requires latest libdrm for amdgpu_bo_handle_type_kms_noimport --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 6 +++ src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 2 + src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 54 +-- 3 files changed, 58

[Mesa-dev] [PATCH 4/9] winsys/amdgpu: use alloca when using global_bo_list

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 1aaa0667310..ec164175dbc 100644 ---

[Mesa-dev] [PATCH 3/9] winsys/amdgpu: remove label bo_list_error

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 28 +-- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 77b372d2cea..1aaa0667310 100644 ---

[Mesa-dev] [PATCH 0/9] RadeonSI on AMDGPU: Command submission optimizations

Hi, This series improves RadeonSI performance for trivial CPU-bound benchmarks. Other CPU-bound benchmarks may be affected marginally. The first 8 patches are cleanups that surprisingly increase performance. The last patch uses a new chunk type in the CS ioctl for passing the array of buffer

[Mesa-dev] [PATCH 1/9] winsys/amdgpu: make amdgpu_cs_context::flags & handles local

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 23 +-- src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 4 2 files changed, 5 insertions(+), 22 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

[Mesa-dev] [PATCH 6/9] radeonsi: merge DCC/CMASK/HTILE priority flags

From: Marek Olšák For a later simplification. --- src/gallium/drivers/r600/evergreen_state.c| 4 ++-- src/gallium/drivers/r600/r600_state.c | 2 +- src/gallium/drivers/radeon/radeon_winsys.h| 4 +--- src/gallium/drivers/radeonsi/si_debug.c | 4 +---

[Mesa-dev] [PATCH 8/9] winsys/amdgpu: clean up error handling in amdgpu_cs_submit_ib

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 872e67a790a..ac7160a5e51 100644 ---

Re: [Mesa-dev] [RFC PATCH] mesa/st: don't prematurely optimize for render targets when on virgl

If some formats are not supported as render targets, I recommend that they are not supported for texturing either. (radeonsi doesn't support unaligned 3-channel formats either. It only supports aligned formats, such as R8G8B8X8 and R32G32B32X32.) If you can't support RGBX formats as render

[Mesa-dev] [PATCH] anv: Stop setting 3DSTATE_PS_EXTRA::PixelShaderHasUAV

We've had several broadwell hangs that have come down to this bit just not working correctly. Most recently, we've had a pile of hangs reported with apps running under DXVK: https://github.com/doitsujin/dxvk/issues/469 Instead, use the bit that doesn't try to imply weird D3D coherency things

[Mesa-dev] [PATCH] util/rb_tree: Fix a compiler warning

Gcc 8 warns "cast to pointer from integer of different size" in 32-bit builds. --- src/util/rb_tree.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/util/rb_tree.h b/src/util/rb_tree.h index e8750b32d0e..c77e9255ea2 100644 --- a/src/util/rb_tree.h +++ b/src/util/rb_tree.h

[Mesa-dev] [PATCH 1/2] u_draw: Add some indices to the util_draw_elements() helpers.

These helpers have been unused, and were definitely not useful since 330d0607ed60 ("gallium: remove pipe_index_buffer and set_index_buffer") made it so that they never had an index buffer passed in. For an upcoming u_blitter change to use these helpers, I have just 6 bytes of index data, so pass

[Mesa-dev] [PATCH 2/2] u_blitter: Add an option to draw the triangles using an index buffer.

For V3D, the HW will interpolate slightly differently along the shared edge of the trifan. The conformance tests manage to catch this in the nearest_consistency_* group. To get interpolation to match, we need the last vertex of the triangle to be shared. I first tried implementing

Re: [Mesa-dev] [PATCH] i965/fs: unspills shoudn't use grf127 as dest since Gen8+

On Wed, Jul 11, 2018 at 06:03:05PM +0200, Jose Maria Casanova Crespo wrote: > At 232ed8980217dd65ab0925df28156f565b94b2e5 "i965/fs: Register allocator > shoudn't use grf127 for sends dest" we didn't take into account the case > of SEND instructions that are not send_from_grf. But since Gen7+

[Mesa-dev] [PATCH v2] i965/miptree: Init r8stencil_needs_update to false

The current behavior masked two bugs where the flag was not set to true after modifying the stencil texture. One case was a regression introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd and another was a bug in the depthstencil mapping code. These have since been fixed. To prevent

Re: [Mesa-dev] [PATCH 6/6] vtn: handle OpConstantComposites with OpUndef members

1, 2, 3, and 6 are Reviewed-by: Jason Ekstrand On Wed, Jul 11, 2018 at 2:30 PM Karol Herbst wrote: > Signed-off-by: Karol Herbst > --- > src/compiler/spirv/spirv_to_nir.c | 15 +-- > 1 file changed, 13 insertions(+), 2 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 1/3] egl/android: Delete set_damage_region from egl dri vtbl

Harish Krupo writes: > Hi Eric, > > Eric Anholt writes: > >> Harish Krupo writes: >> >>> The intension of the KHR_partial_update was not to send the damage back >>> to the platform but to send the damage to the driver to ensure that the >>> following rendering could be restricted to those

[Mesa-dev] [Bug 107169] [regression] Upgrade from 18.0.4 to 18.1.0 causes severe stuttering in games

https://bugs.freedesktop.org/show_bug.cgi?id=107169 --- Comment #3 from Timothy Arceri --- I highly recommend trying to build mesa from git and doing a git bisect from the 18.0.0 branch point until the 18.1.0 branch point. There are not may devs actively working on the r600 driver and bisecting

[Mesa-dev] [Bug 107156] earth tessellation bug

https://bugs.freedesktop.org/show_bug.cgi?id=107156 --- Comment #5 from Timothy Arceri --- Here are some really quick instructions for building mesa and bisecting the issue. Get and Build RADV: --- git clone https://gitlab.freedesktop.org/mesa/mesa.git cd mesa sudo dnf

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.1.2 fails lp_test_format, lp_test_arit, lp_test_blend, lp_test_printf, lp_test_conv tests

https://bugs.freedesktop.org/show_bug.cgi?id=106644 --- Comment #34 from Ben Crocker --- Also, are you able to run this test on PPC64 BE? (My PPC64 BE machine is out of service at the moment.) -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for

Re: [Mesa-dev] [PATCH 00/18] anv/pipeline: Do cross-stage linking

On 12/07/18 07:18, Jason Ekstrand wrote: I sent out a series for this almost a year ago and it just sat on the list rotting away. You can find the original series here: https://patchwork.freedesktop.org/series/32809/ This v2 is a rebase of that series. I believe Tim reviewed most of the

Re: [Mesa-dev] [PATCH] st/mesa: call resource_changed when binding a EGLImage to a texture

Reviewed-by: Marek Olšák Marek On Mon, Jul 9, 2018 at 12:53 PM, Lucas Stach wrote: > When a EGLImage is newly bound to a texture, we need to make sure the > driver is informed that the resource might have changed. Fixes stale > texture content on Etnaviv when binding an existing EGLImage to an

[Mesa-dev] [PATCH 07/18] anv/pipeline: Populate keys up-front

Instead of having each anv_pipeline_compile_* function populate the shader key, make it part of the anv_pipeline_stage struct and fill it out up-front. --- src/intel/vulkan/anv_pipeline.c | 115 +--- 1 file changed, 60 insertions(+), 55 deletions(-) diff --git

[Mesa-dev] [PATCH 11/18] anv/pipeline: Drop anv_pipeline_add_compiled_stage

We can set active_stages much more directly and then it's just candy around setting pipeline->stages[stage]. --- src/intel/vulkan/anv_pipeline.c | 27 ++- src/intel/vulkan/genX_pipeline.c | 2 -- 2 files changed, 10 insertions(+), 19 deletions(-) diff --git

[Mesa-dev] [PATCH 13/18] anv/pipeline: Compile to NIR in compile_graphics

This pulls the SPIR-V to NIR step out into common code. --- src/intel/vulkan/anv_pipeline.c | 278 +--- 1 file changed, 116 insertions(+), 162 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index bc268b87e55..50d6ab358d2

[Mesa-dev] [PATCH 08/18] anv/pipeline: Hash the entire pipeline in one go

Instead of hashing each stage separately (and TES and TCS together), we hash the entire pipeline. This means we'll get fewer cache hits if they, for instance, re-use the same VS over and over again but it also means we can now safely do cross-stage optimizations. ---

[Mesa-dev] [PATCH 16/18] nir/lower_indirect: Bail early if modes == 0

There's no point in walking the program if 100% if we're never going to actually lower anything. --- src/compiler/nir/nir_lower_indirect_derefs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/nir/nir_lower_indirect_derefs.c b/src/compiler/nir/nir_lower_indirect_derefs.c

[Mesa-dev] [PATCH 05/18] anv/pipeline: Add populate_tcs/tes_key helpers

They don't really do anything interesting, but it's more consistent this way. --- src/intel/vulkan/anv_pipeline.c | 28 +--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index

[Mesa-dev] [PATCH 12/18] anv/pipeline: Recompile all shaders if any are missing from the cache

--- src/intel/vulkan/anv_pipeline.c | 41 + 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 200b8748186..bc268b87e55 100644 --- a/src/intel/vulkan/anv_pipeline.c +++

[Mesa-dev] [PATCH 09/18] anv/pipeline: Call anv_pipeline_compile_* in a loop

--- src/intel/vulkan/anv_pipeline.c | 56 ++--- 1 file changed, 30 insertions(+), 26 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index d56f6ce8966..fb3ae15210d 100644 --- a/src/intel/vulkan/anv_pipeline.c +++

[Mesa-dev] [PATCH 14/18] anv/pipeline: Add a separate "link" stage

This breaks compilation up a bit into "link" and "compile". In the "link" stage, new anv_pipeline_link_* helpers are called which are responsible for setting up the binding table and doing anything needed to properly link with the next stage in the pipeline if one exists. They are called in

[Mesa-dev] [PATCH 10/18] anv/pipeline: Pull shader compilation out into a helper.

--- src/intel/vulkan/anv_pipeline.c | 228 +--- 1 file changed, 120 insertions(+), 108 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index fb3ae15210d..9f35bc9c27b 100644 --- a/src/intel/vulkan/anv_pipeline.c +++

[Mesa-dev] [PATCH 01/18] anv/pipeline: Fix up deref modes if we delete a FS output

With the new deref instructions, we have to keep the modes consistent between the derefs and the variables they reference. Since we remove outputs by changing them to local variables, we need to run the fixup pass to fix the modes. --- src/intel/vulkan/anv_pipeline.c | 5 + 1 file changed, 5

[Mesa-dev] [PATCH 03/18] anv/pipeline: More aggressively optimize away color attachments

Instead of just looking at the number of color attachments, look at which ones are actually used by the subpass. This lets us potentially throw away chunks of the fragment shader. In DXVK, for example, all subpasses have 8 attachments and most are VK_ATTACHMENT_UNUSED so this is very helpful in

[Mesa-dev] [PATCH 04/18] anv/pipeline: Rework the parameters to populate_wm_prog_key

--- src/intel/vulkan/anv_pipeline.c | 46 + 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 0d514fbae47..d6e8e0a0838 100644 --- a/src/intel/vulkan/anv_pipeline.c +++

[Mesa-dev] [PATCH 06/18] anv/pipline: Add a helper struct for per-stage info

--- src/intel/vulkan/anv_pipeline.c | 167 ++-- src/intel/vulkan/anv_private.h | 2 +- 2 files changed, 74 insertions(+), 95 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index e39ce2de010..c2ef8878db6 100644 ---

[Mesa-dev] [PATCH 02/18] anv: Restrict the nuber of color regions to those actually written

The back-end compiler emits the number of color writes specified by wm_prog_key::nr_color_regions regardless of what nir_store_outputs we have. Once we've gone through and figured out which render targets actually exist and are written by the shader, we should restrict the key to avoid extra RT

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