I think I have a similar patch laying around in my 2nd level batch buffer
branch. :)
Reviewed-by: Jason Ekstrand
On Tue, Aug 14, 2018 at 5:26 AM Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> The batch decoder looks for a field with a particular name to decide
> whether an
On 8/15/18 11:49 AM, Jason Ekstrand wrote:
On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset
mailto:samuel.pitoi...@gmail.com>> wrote:
Reviewed-by: Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>>
On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:
> Behavior wrt firstInstance got
From: Kevin Rogovin
The main purpose for having NV_fragment_shader_interlock
extension is because that extension is also for GLES31 while
the ARB extension is for GL only.
---
src/compiler/glsl/builtin_functions.cpp | 18 ++
src/compiler/glsl/glsl_parser.yy | 6 --
Hi Bas,
Il giorno mar 14 ago 2018 alle ore 23:10 Bas Nieuwenhuizen <
b...@basnieuwenhuizen.nl> ha scritto:
> On Tue, Aug 14, 2018 at 10:48 PM, Mauro Rossi
> wrote:
> > (VkShaderModule) cast is added before NULL to avoid following building
> error:
> >
> >
Hi all,
Thanks for your reply.
We shouldn't even get to use the iterator if it's an unknown instruction.
> The decoder should just advance dword by dword until it finds something
> that
> makes sense again.
>
Got it)
So this is an expected behavior there:
return iter_group_offset_bits(iter,
On 2018-08-15 12:13 PM, Timothy Arceri wrote:
> Use enviroment var overrides in legacy drivers instead.
This could break existing user configurations using the driconf tcl_mode
option.
Apart from this, I like the idea of this series.
--
Earthling Michel Dänzer |
On 15 August 2018 at 09:13, Mauro Rossi wrote:
> Hi Robert,
> Il giorno mer 15 ago 2018 alle ore 09:37 Robert Foss
> ha scritto:
>>
>> Hey Mauro,
>>
>> Thanks for catching this.
>>
>> On 14/08/2018 22.27, Mauro Rossi wrote:
>> > This patch fixes a regression in mesa 18.2 and mesa-dev branches
>>
Do you need the game name here, isn't that set in driconf?
On Wed, 15 Aug 2018 at 12:12 Timothy Arceri wrote:
> Cc:
> ---
> src/amd/vulkan/radv_device.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index
On 15/08/18 12:23, Sergii Romantsov wrote:
Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).
-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris
This option allows us to remove additional s_waitcnt instructions
because s_barrier internally does s_waitcnt 0.
Though, apparently there is a problem with LDS accesses that
causes rendering issues with FFXV and DXVK. Disable this
optimization for now (RadeonSI still uses it).
Bugzilla:
Fixes: 3f7bca44d9 ("egl/android: #ifdef out flink name support")
Fixes: c7bb82136b ("egl/android: Add DRM node probing and filtering")
Signed-off-by: Mauro Rossi
---
src/egl/drivers/dri2/platform_android.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
On 2018-08-06 05:19 AM, Qiang Yu wrote:
> Also prepare for the usage of following parseConfigDir patch.
>
> Signed-off-by: Qiang Yu
> ---
> src/util/xmlconfig.c | 62
>
> 1 file changed, 28 insertions(+), 34 deletions(-)
>
> diff --git
Ah,
with 'latest' stuff only #8 choke.
Dieter
Am 15.08.2018 11:21, schrieb Dieter Nützel:
Hello Marek,
sadly this series didn't apply on top of current git master.
Dieter
Am 09.08.2018 04:12, schrieb Marek Olšák:
Hi,
This series adds these extensions:
- AMD_gpu_shader_int64
-
re-associating based on whether or not something has a constant value of
1.0 seems a bit sneaky. I think it's well within the rules but it seems
like something that could bite you.
On Mon, Aug 13, 2018 at 6:35 PM Ian Romanick wrote:
> From: Ian Romanick
>
> Instead of lowering as (a + c(b -
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 12
src/util/xmlpool/ca.po | 16
src/util/xmlpool/de.po | 16
src/util/xmlpool/es.po | 16
src/util/xmlpool/fr.po
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 6 ++
src/util/xmlpool/ca.po | 6 --
src/util/xmlpool/de.po | 6 --
src/util/xmlpool/es.po | 6 --
src/util/xmlpool/fr.po | 5 -
---
src/util/xmlpool/ca.po | 7 ---
src/util/xmlpool/de.po | 7 ---
src/util/xmlpool/es.po | 7 ---
src/util/xmlpool/fr.po | 6 --
src/util/xmlpool/nl.po | 7 ---
src/util/xmlpool/sv.po | 5 -
6 files changed, 39 deletions(-)
diff --git a/src/util/xmlpool/ca.po
Use enviroment var overrides in legacy drivers instead.
---
src/mesa/drivers/dri/r200/r200_context.c | 4 +---
src/mesa/drivers/dri/radeon/radeon_context.c | 5 ++---
src/mesa/drivers/dri/radeon/radeon_screen.c | 2 --
src/util/xmlpool/ca.po | 23
This seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.
---
src/util/xmlpool/ca.po | 16
src/util/xmlpool/de.po | 16
src/util/xmlpool/es.po | 16
src/util/xmlpool/fr.po | 16
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
src/util/xmlpool/ca.po | 4
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
src/util/xmlpool/nl.po
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 10 ++
src/util/xmlpool/ca.po | 12
src/util/xmlpool/de.po | 12
src/util/xmlpool/es.po | 12
src/util/xmlpool/fr.po
This seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.
---
src/util/xmlpool/ca.po | 4
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
src/util/xmlpool/nl.po | 4
This seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.
---
src/util/xmlpool/t_options.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 3e5993caf78..f0dc78dd595 100644
---
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 10 ++
src/util/xmlpool/ca.po | 12
src/util/xmlpool/de.po | 12
src/util/xmlpool/es.po | 12
src/util/xmlpool/fr.po
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
src/util/xmlpool/ca.po | 4
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
src/util/xmlpool/nl.po
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
src/util/xmlpool/ca.po | 4
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
src/util/xmlpool/nl.po
Signed-off-by: Danylo Piliaiev
---
src/compiler/glsl/ir_clone.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/glsl/ir_clone.cpp b/src/compiler/glsl/ir_clone.cpp
index 69441fae7d..e1f4f3b290 100644
--- a/src/compiler/glsl/ir_clone.cpp
+++ b/src/compiler/glsl/ir_clone.cpp
@@
do_assignment validated assigment but when rhs type was not compatible
it proceeded without issues and returned error_emitted = false.
On the other hand process_initializer expected do_assignment to always
return compatible type and never fail.
As a result when variable was initialized with
Hi,
This is my first attempt to review patch for Mesa, so please take it with a
grain of salt.
On úterý 14. srpna 2018 20:21:40 CEST Chris Wilson wrote:
> @@ -504,6 +506,24 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
> bool busy = false;
> bool zeroed = false;
>
> + /* Reuse the
Thanks, Michel.
> What's the point of having the separate _parseOneConfigFile function?
> It's not used outside of parseOneConfigFile AFAICT.
No particular reason from mine, just move out the inline part. So should
be same reason as the original code to separate the parser prepare part
and the
For the series
Tested-by: Dieter Nützel
Dieter
Am 09.08.2018 01:55, schrieb Marek Olšák:
Hi,
The idea is to expose similar limits as our closed driver.
There are also some bug fixes.
Please review.
Thanks,
Marek
___
mesa-dev mailing list
On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote:
On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset
wrote:
The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but
it was initialized to 0.
COMPUTE_RESOURCE_LIMITS is correctly
Quoting Michal Srb (2018-08-15 09:22:19)
> Hi,
>
> This is my first attempt to review patch for Mesa, so please take it with a
> grain of salt.
>
> On úterý 14. srpna 2018 20:21:40 CEST Chris Wilson wrote:
> > @@ -504,6 +506,24 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
> > bool busy =
On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset
wrote:
> Reviewed-by: Samuel Pitoiset
>
> On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:
> > Behavior wrt firstInstance got changed, and a divisor of 0 has been
> > disallowed.
> >
> > The new version of the ext got published in specification
Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).
-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris Wilson).
-v4: changes related to PAGE_SIZE moved
Usage of number 4096 replaced by PAGE_SIZE.
Signed-off-by: Sergii Romantsov
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index
Hey Mauro,
Thanks for catching this.
On 14/08/2018 22.27, Mauro Rossi wrote:
This patch fixes a regression in mesa 18.2 and mesa-dev branches
for HAVE_DRM_GRALLOC code path which is causing black screen on Android
and prevents boot due to SIGSEGV MAPERR crash related to unproper handling
of
Hello, Kenneth.
Thanks for remarks.
Will update patch soon and also will try to look on 3DSTATE_SO_BUFFER.
On Tue, Aug 14, 2018 at 8:39 PM, Kenneth Graunke
wrote:
> Hi Sergii,
>
> This patch causes 2,384 failures in CI. The issue is that we're
> apparently trying to allocate 0 size BOs in some
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
src/util/xmlpool/ca.po | 6 --
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 12
src/util/xmlpool/ca.po | 17 -
src/util/xmlpool/de.po | 17 -
src/util/xmlpool/es.po | 17 -
src/util/xmlpool/fr.po
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 13 +
src/util/xmlpool/ca.po | 20
src/util/xmlpool/de.po | 20
src/util/xmlpool/es.po | 20
Cc:
---
src/amd/vulkan/radv_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 33f24b9d302..cc88abb57a8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -480,6 +480,9 @@
On 15/08/18 22:06, Bas Nieuwenhuizen wrote:
On Wed, Aug 15, 2018 at 1:16 PM, Mike Lothian wrote:
Do you need the game name here, isn't that set in driconf?
There is no driconf for vulkan/radv yet.
Reviewed-by: Bas Nieuwenhuizen
I assume you tested that it works with the workaround?
Yes.
Hi Robert,
Il giorno mer 15 ago 2018 alle ore 09:37 Robert Foss <
robert.f...@collabora.com> ha scritto:
> Hey Mauro,
>
> Thanks for catching this.
>
> On 14/08/2018 22.27, Mauro Rossi wrote:
> > This patch fixes a regression in mesa 18.2 and mesa-dev branches
> > for HAVE_DRM_GRALLOC code path
Hello Marek,
sadly this series didn't apply on top of current git master.
Dieter
Am 09.08.2018 04:12, schrieb Marek Olšák:
Hi,
This series adds these extensions:
- AMD_gpu_shader_int64
- AMD_multi_draw_indirect
- AMD_query_buffer_object
- AMD_texture_texture4
- EXT_vertex_attrib_64bit
It
On Wed, Aug 15, 2018 at 2:04 PM, Mauro Rossi wrote:
> Hi Bas,
>
> Il giorno mar 14 ago 2018 alle ore 23:10 Bas Nieuwenhuizen
> ha scritto:
>>
>> On Tue, Aug 14, 2018 at 10:48 PM, Mauro Rossi
>> wrote:
>> > (VkShaderModule) cast is added before NULL to avoid following building
>> > error:
>> >
I don't like this... but patch is:
Reviewed-by: Samuel Pitoiset
On 8/15/18 1:12 PM, Timothy Arceri wrote:
Cc:
---
src/amd/vulkan/radv_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 33f24b9d302..cc88abb57a8
Hello list,
The third release candidate for the Mesa 18.2.0 is now available.
Currently we have:
- 24 queued
- 1 nominated (outstanding)
- and 0 rejected patches
In the current queue we have:
The GLSL compiler has received a correction when hitting an error
condition.
Mesa's state tracker
https://bugs.freedesktop.org/show_bug.cgi?id=107563
--- Comment #5 from Samuel Pitoiset ---
Can you try to record a renderdoc trace that reproduces the issue please?
--
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the
On Wed, Aug 15, 2018 at 11:49 AM, Jason Ekstrand wrote:
> On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset
> wrote:
>>
>> Reviewed-by: Samuel Pitoiset
>>
>> On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:
>> > Behavior wrt firstInstance got changed, and a divisor of 0 has been
>> > disallowed.
>> >
v4: make the immediate field 16 bits
Signed-off-by: Rhys Perry
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 65 ++
.../nouveau/codegen/nv50_ir_target_gm107.cpp | 6 +-
.../nouveau/codegen/nv50_ir_target_nvc0.cpp| 1 +
3 files changed, 71
Changes in v4:
- remove uint16_t(...) in nv50_ir.h
- change XMAD immediate size from signed 20 bit to unsigned 16 bit
- rework the 4th patch
Changes in v3:
- stylistic changes
- simplify createMulMethod2()
- update shader-db statistics
- use util_bitcount64 and util_next_power_of_two64 instead of
v4: remove uint16_t(...)
v4: don't allow immediates outside [0,65535] in insnCanLoad()
Signed-off-by: Rhys Perry
Reviewed-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 26 ++
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 18 +--
This hits the shader-db numbers a good bit, though a few xmads is way
faster than an imul or imad and the cost is mitigated by the next commit,
which optimizes many multiplications by immediates into shorter and less
register heavy instructions than the xmads.
total instructions in shared
Strongly mitigates the harm from the previous commit, which made many
integer multiplications much more heavy on the register and instruction
count.
total instructions in shared programs : 5820882 -> 5788434 (-0.56%)
total gprs used in shared programs: 670595 -> 669996 (-0.09%)
total shared
https://bugs.freedesktop.org/show_bug.cgi?id=107509
Michel Dänzer changed:
What|Removed |Added
Attachment #140998|text/x-log |text/plain
mime type|
Quoting Bas Nieuwenhuizen (2018-08-09 17:27:46)
> CC:
> ---
> src/amd/vulkan/Android.mk | 2 ++
> src/amd/vulkan/Makefile.am | 2 +-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/Android.mk b/src/amd/vulkan/Android.mk
> index cee3744f40b..51b03561fa7 100644
Reported by Coverity.
Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index
Reviewed-by: Bas Nieuwenhuizen
On Wed, Aug 15, 2018 at 3:28 PM, Samuel Pitoiset
wrote:
> Reported by Coverity.
>
> Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta.c | 5 +++--
> 1 file changed, 3
Added debug-log in case of bo-allocation with 0 size.
Potentially we may not need to allocate such buffers and each
case could be analyzed to improve behaviour.
Signed-off-by: Sergii Romantsov
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=107460
Samuel Pitoiset changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
On August 15, 2018 09:28:36 Bas Nieuwenhuizen wrote:
On Wed, Aug 15, 2018 at 11:49 AM, Jason Ekstrand wrote:
On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset
wrote:
Reviewed-by: Samuel Pitoiset
On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:
Behavior wrt firstInstance got changed, and a
From: Andrii Simiklit
When the SVBI Payload Enable is false I guess the register R1.4
which contains the Maximum Streamed Vertex Buffer Index is filled by zero
and GS stops to write transform feedback when the transform feedback
is not active.
Bugzilla:
On Tue, Aug 14, 2018 at 7:25 PM Timothy Arceri
wrote:
> On 09/08/18 05:05, Jason Ekstrand wrote:
> > Commit 4434591bf56a6b0 caused substantially more URB messages in
> > geometry and tessellation shaders. Before we can really enable this
> > sort of optimization, We either need some way of
On 8/15/18 3:33 PM, Bas Nieuwenhuizen wrote:
Reviewed-by: Bas Nieuwenhuizen
On Wed, Aug 15, 2018 at 3:09 PM, Samuel Pitoiset
wrote:
This option allows us to remove additional s_waitcnt instructions
because s_barrier internally does s_waitcnt 0.
Though, apparently there is a problem with
On 8/15/18 3:34 PM, Bas Nieuwenhuizen wrote:
On Wed, Aug 15, 2018 at 2:13 PM, Samuel Pitoiset
wrote:
On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote:
On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset
wrote:
The last parameter of radeon_set_sh_reg_seq() is the number of
dwords to emit. We
On Wed, Aug 15, 2018 at 2:13 PM, Samuel Pitoiset
wrote:
>
>
> On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote:
>>
>> On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset
>> wrote:
>>>
>>> The last parameter of radeon_set_sh_reg_seq() is the number of
>>> dwords to emit. We were lucky because
Reviewed-by: Samuel Pitoiset
On 8/15/18 4:30 PM, Bas Nieuwenhuizen wrote:
Seems like DXVK depends on that and it might get reverted
upstream. Since apps are not supposed to use 0 in v2 anyway,
we should be safe implementing the old behavior there.
Fixes: 66e12451ac4 "radv: Update to new
> Pardon for the delay, Qiang Yu Series looks good and is
> Reviewed-by: Emil Velikov
>
> The series has been on the list for a while, Michel seems happy with
> it, so I'm inclined to merge this late today/early tomorrow.
> Please keep an eye open for any bug reports - just a gut feeling.
Hello,
that patch is according to remark:
>
> "Additionally, we probably ought to fix the callers to stop allocating 0
> size BOs.
> It looks like most of them come from the 3DSTATE_SO_BUFFER code,
> where one stream has valid transform feedback info, and the other
> 3 are empty. "
And seems
Hi all,
This workaround just helps me to avoid the graphical corruption on SNB but
I not sure is it good idea.
Regards,
Andrii.
On Wed, Aug 15, 2018 at 6:20 PM, wrote:
> From: Andrii Simiklit
>
> When the SVBI Payload Enable is false I guess the register R1.4
> which contains the Maximum
https://bugs.freedesktop.org/show_bug.cgi?id=107509
Michel Dänzer changed:
What|Removed |Added
Assignee|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop
Seems that in a single case we use the renderpass before checking
the pipeline, so check the renderpass before we use it.
Fixes: fbcd1673144 "radv: Add on-demand compilation of built-in shaders."
---
src/amd/vulkan/radv_meta_resolve_fs.c | 8
1 file changed, 8 insertions(+)
diff --git
Seems like DXVK depends on that and it might get reverted
upstream. Since apps are not supposed to use 0 in v2 anyway,
we should be safe implementing the old behavior there.
Fixes: 66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to
version 2."
CC: 18.2
---
On 15/08/18 12:23, Sergii Romantsov wrote:
Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).
-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris
This handy helper is nice for OSes that are not linux or BSD like (mac
and windows) as it knows how to find python3 in odd places.
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 5dc9b45eb42..c8bac35659f 100644
--- a/meson.build
From: "Kristian H. Kristensen"
Signed-off-by: Kristian H. Kristensen
---
src/gallium/drivers/freedreno/a5xx/fd5_compute.c | 2 +-
src/gallium/drivers/freedreno/freedreno_resource.c | 8
src/gallium/drivers/freedreno/ir3/ir3.h| 8 ++--
It's what autotools has required for a long time.
---
meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/meson.build b/meson.build
index 7436164946b..5dc9b45eb42 100644
--- a/meson.build
+++ b/meson.build
@@ -698,9 +698,9 @@ if with_platform_haiku
endif
v2: - Use distutils to do the version checking
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107565
---
scons/gallium.py | 13 +
1 file changed, 13 insertions(+)
diff --git a/scons/gallium.py b/scons/gallium.py
index 659da72c1c3..aa7201a9715 100755
--- a/scons/gallium.py
We don't want to support older versions of python 2 anymore, and we
don't support python 3.x in autotools currently.
---
configure.ac | 7 +++
1 file changed, 7 insertions(+)
diff --git a/configure.ac b/configure.ac
index c2155a541b0..78672734d06 100644
--- a/configure.ac
+++ b/configure.ac
less than 2.7 is not supported.
v2: - Remove check for python >= 2.0, since we've already enforced 2.7
---
SConstruct | 1 +
scons/gallium.py | 4
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/SConstruct b/SConstruct
index 6e034fb968f..51dc301a9a8 100644
---
Reviewed-by: Bas Nieuwenhuizen
On Wed, Aug 15, 2018 at 3:09 PM, Samuel Pitoiset
wrote:
> This option allows us to remove additional s_waitcnt instructions
> because s_barrier internally does s_waitcnt 0.
>
> Though, apparently there is a problem with LDS accesses that
> causes rendering issues
https://bugs.freedesktop.org/show_bug.cgi?id=107457
Mark Janes changed:
What|Removed |Added
Depends on||107359
Referenced Bugs:
On August 15, 2018 14:43:08 Lionel Landwerlin
wrote:
Hey there,
Just a few nits below.
Thanks!
-
Lionel
On 15/08/18 18:42, Yunchao He wrote:
This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.
I verified CTS with the
https://bugs.freedesktop.org/show_bug.cgi?id=103078
Dylan Baker changed:
What|Removed |Added
Resolution|--- |NOTOURBUG
Status|NEW
https://bugs.freedesktop.org/show_bug.cgi?id=83785
Dylan Baker changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.
I verified CTS with the command below:
deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*
v2: 1) support all depth formats, not depth-only formats, 2) fix
a wrong
Disregard this patch. I'm sending a replacement for it.
For the record:
> The pass works by walking through the control flow nodes, and traverse
> the instructions keeping track of the write instructions whose
> destination were not overwritten by other instructions (called "live
> writes").
Since there's no particular reason for the index to be 0, choose an
index that is not used by other block. This is convenient when we
store "per-block" data in an array AND look for the successors
data (e.g. any kind of backwards data-flow analysis).
---
src/compiler/nir/nir.c | 2 +-
1 file
Instead of doing this as part of the existing (local) copy prop vars
pass. This is an intermediate step before changing both the dead
write and the copy prop vars to act on the whole program instead of on
local blocks. The nature of data we store and the way we iterate is
different enough that
---
src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
index db1d74fdee7..d5f42f2a231 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
+++
These are handled by a separate pass now.
---
src/compiler/nir/nir_opt_copy_prop_vars.c | 67 +--
1 file changed, 3 insertions(+), 64 deletions(-)
diff --git a/src/compiler/nir/nir_opt_copy_prop_vars.c
b/src/compiler/nir/nir_opt_copy_prop_vars.c
index
The pass will remove not only writes that are proven to be dead in
block, but also writes that can only be considered dead by looking at
multiple blocks. Such global analysis is necessary to remove dead
writes such as the one marked below:
int total = gl_VertexIndex * 10;
float r =
Our code currently only remove dead writes to vars for each block, but
doesn't tackle cases that involve multiple blocks. This series will
add a pass that use an iterative data-flow analysis to cover those
cases. Commit message for patch 6 has a detailed example.
I'm working on a subsequent
Reviewed-by: Timothy Arceri
---
src/compiler/nir/nir_deref.c | 109
src/compiler/nir/nir_deref.h | 10 ++
src/compiler/nir/nir_opt_copy_prop_vars.c | 145 ++
3 files changed, 132 insertions(+), 132 deletions(-)
diff --git
---
src/util/u_dynarray.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
index dcbbc06d161..4920fe04b67 100644
--- a/src/util/u_dynarray.h
+++ b/src/util/u_dynarray.h
@@ -102,6 +102,15 @@ util_dynarray_resize(struct util_dynarray *buf,
---
src/intel/compiler/brw_nir.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 31ffbe613ec..afc73e58c71 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -543,6 +543,7 @@
Deref paths may share the same deref instructions in their chains,
e.g.
ssa_100 = deref_var A
ssa_101 = deref_struct "array_field" of ssa_100
ssa_102 = deref_array "[1]" of ssa_101
ssa_103 = deref_struct "field_a" of ssa_102
ssa_104 = deref_struct "field_a" of ssa_103
when
Forcing software fallbacks for i965 hasn't been an option since
5e3c093ff866.
---
src/mesa/drivers/dri/i965/brw_context.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 72be8f2a4d0..c32def7c3d7 100644
---
These seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.
---
src/util/xmlpool/ca.po | 8
src/util/xmlpool/de.po | 8
src/util/xmlpool/es.po | 8
src/util/xmlpool/fr.po | 8
src/util/xmlpool/nl.po
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