On 2018-12-04 19:39:05, Jason Ekstrand wrote:
> Given that everyone else has firmly ACKed, I'm going to click the button.
> Congratulations, Jordan, you're now a mesa Owner!
Thanks all!
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https://bugs.freedesktop.org/show_bug.cgi?id=108925
Alex Smith changed:
What|Removed |Added
Attachment #142700|0 |1
is obsolete|
On Tue, Dec 04, 2018 at 08:16:47AM +0100, Iago Toral Quiroga wrote:
> From the Skylake PRM, Extended Math Function:
>
> "The execution size must be no more than 8 when half-floats
>are used in source or destination operand."
>
> Earlier generations do not support Extended Math with
On Wed, Dec 5, 2018 at 6:30 AM Ilia Mirkin wrote:
>
> Signed-off-by: Ilia Mirkin
> ---
> .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 49 +++
> .../nouveau/codegen/nv50_ir_lowering_nvc0.h | 1 +
> 2 files changed, 50 insertions(+)
>
> diff --git
On 12/5/18 11:15 AM, Alex Smith wrote:
Thanks. Though this fixes the 100% repro hang, I think your first patch
is still needed as well to handle getting 0x in the low 32 bits.
Yeah, it's still needed. Though I think it should be enough to wait on
the high 32bits as suggested by Bas.
On Tue, 2018-12-04 at 18:10 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 02:33:25PM +0200, Pohjolainen, Topi wrote:
> > On Tue, Dec 04, 2018 at 08:16:34AM +0100, Iago Toral Quiroga wrote:
> > > Signed-off-by: Samuel Iglesias Gonsálvez
> > > ---
> > >
https://bugs.freedesktop.org/show_bug.cgi?id=106958
Samuel Pitoiset changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
On Wed, Dec 05, 2018 at 09:49:29AM +0100, Iago Toral wrote:
> On Tue, 2018-12-04 at 14:57 +0200, Pohjolainen, Topi wrote:
> > On Tue, Dec 04, 2018 at 08:16:35AM +0100, Iago Toral Quiroga wrote:
> > > From: Samuel Iglesias Gonsálvez
> > >
> > > It is not supported directly in the HW, we need to
Yes, this is correct, indeed.
The issue wasn't present because we used EOP events before removing the
availability bit.
Btw, just noticed that we should reset pending_reset_query directly in
si_emit_cache_flush() to reduce the number of stalls. I will send a patch.
Also note that fill CP
If the driver used a compute shader for resetting a query pool,
it should be completed when caches are flushed.
This might reduce the number of stalls if operations are done
between vkCmdResetQueryPool() and vkCmdBeginQuery()
(or vkCmdWriteTimestamp()).
Signed-off-by: Samuel Pitoiset
---
On 12/5/18 12:34 PM, Bas Nieuwenhuizen wrote:
We do the ImageFormatProperties check already, and rejecting an usage
flag when both ImageFormatProperties and the WSI (which is Android)
support it is not allowed.
Intel does support storage for some of the support WSI formats, such
as
On Wed, 2018-12-05 at 11:39 +0200, Pohjolainen, Topi wrote:
> I remember people preferring to order things 16, 32, 64 before.
> Should
> we follow that here as well?
Yes, it makes sense. I'll change that.
> On Tue, Dec 04, 2018 at 08:16:46AM +0100, Iago Toral Quiroga wrote:
> > ---
> >
On Fri, Sep 7, 2018 at 12:54 AM Kevin Strasser wrote:
>
> Android P and earlier expect that the surface supports storage images, and
> so many of the tests fail when the framework checks for that support. The
> framework also includes various image format and usage combinations that are
> invalid
On Tue, 2018-12-04 at 14:57 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 08:16:35AM +0100, Iago Toral Quiroga wrote:
> > From: Samuel Iglesias Gonsálvez
> >
> > It is not supported directly in the HW, we need to convert to a 32-
> > bit
> > type first as intermediate step.
> >
> >
On Tue, 4 Dec 2018 at 21:57, Bas Nieuwenhuizen
wrote:
> On Tue, Dec 4, 2018 at 4:52 PM Samuel Pitoiset
> wrote:
> >
> > Because WAIT_REG_MEM can only wait for a 32-bit value, it's not
> > safe to use it for timestamp queries. If we only wait on the low
> > 32 bits of a timestamp query we could
From: Christian Gmeiner
A pipe_resource can be shared by all the pipe_context's hanging off the
same pipe_screen.
Signed-off-by: Christian Gmeiner
---
src/gallium/drivers/etnaviv/etnaviv_context.c | 21 -
src/gallium/drivers/etnaviv/etnaviv_context.h | 3 --
Thanks. Though this fixes the 100% repro hang, I think your first patch is
still needed as well to handle getting 0x in the low 32 bits.
On Wed, 5 Dec 2018 at 10:04, Samuel Pitoiset
wrote:
> Yes, this is correct, indeed.
>
> The issue wasn't present because we used EOP events before
https://bugs.freedesktop.org/show_bug.cgi?id=108925
Samuel Pitoiset changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=108914
Samuel Pitoiset changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=108578
Samuel Pitoiset changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
Reviewed-by: Bas Nieuwenhuizen
On Wed, Dec 5, 2018 at 11:43 AM Samuel Pitoiset
wrote:
>
> In case we are unlucky if the low part is 0x.
>
> Fixes: 5d6a560a29 ("radv: do not use the availability bit for timestamp
> queries")
> Signed-off-by: Samuel Pitoiset
> ---
>
On Tue, Dec 4, 2018 at 7:39 PM Jason Ekstrand wrote:
>
> It's been 24 hours and the only owner who hasn't replied yet is Matt. Given
> that everyone else has firmly ACKed, I'm going to click the button.
> Congratulations, Jordan, you're now a mesa Owner!
That's certainly no reflection on my
On Wed, Dec 05, 2018 at 09:20:57AM +0100, Iago Toral wrote:
> On Tue, 2018-12-04 at 18:10 +0200, Pohjolainen, Topi wrote:
> > On Tue, Dec 04, 2018 at 02:33:25PM +0200, Pohjolainen, Topi wrote:
> > > On Tue, Dec 04, 2018 at 08:16:34AM +0100, Iago Toral Quiroga wrote:
> > > > Signed-off-by: Samuel
I remember people preferring to order things 16, 32, 64 before. Should
we follow that here as well?
On Tue, Dec 04, 2018 at 08:16:46AM +0100, Iago Toral Quiroga wrote:
> ---
> src/compiler/nir/nir_opt_algebraic.py | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git
On Wed, 2018-12-05 at 11:08 +0200, Pohjolainen, Topi wrote:
> On Wed, Dec 05, 2018 at 09:49:29AM +0100, Iago Toral wrote:
> > On Tue, 2018-12-04 at 14:57 +0200, Pohjolainen, Topi wrote:
> > > On Tue, Dec 04, 2018 at 08:16:35AM +0100, Iago Toral Quiroga
> > > wrote:
> > > > From: Samuel Iglesias
On Tue, 2018-12-04 at 18:16 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 08:16:36AM +0100, Iago Toral Quiroga wrote:
> > Since we handle booleans as integers this makes more sense.
>
> If this is applied before patch 10, can we merge 10 and 13?
We can't apply this before patch 10
In case we are unlucky if the low part is 0x.
Fixes: 5d6a560a29 ("radv: do not use the availability bit for timestamp
queries")
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_query.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Reviewed-by: Alex Smith
On Wed, 5 Dec 2018 at 10:32, Samuel Pitoiset
wrote:
> If the driver used a compute shader for resetting a query pool,
> it should be completed when caches are flushed.
>
> This might reduce the number of stalls if operations are done
> between vkCmdResetQueryPool() and
As done for vkCmdBeginQuery() already. Prevents timestamps from being
overwritten by previous vkCmdResetQueryPool() calls if the shader path
was used to do the reset.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108925
Fixes: a41e2e9cf5 ("radv: allow to use a compute shader for
We do the ImageFormatProperties check already, and rejecting an usage
flag when both ImageFormatProperties and the WSI (which is Android)
support it is not allowed.
Intel does support storage for some of the support WSI formats, such
as R8G8B8A8_UNORM, and looking at the
On Wed, Dec 05, 2018 at 11:53:44AM +0100, Iago Toral wrote:
> On Wed, 2018-12-05 at 11:39 +0200, Pohjolainen, Topi wrote:
> > I remember people preferring to order things 16, 32, 64 before.
> > Should
> > we follow that here as well?
>
> Yes, it makes sense. I'll change that.
>
> > On Tue, Dec
https://bugs.freedesktop.org/show_bug.cgi?id=108949
--- Comment #2 from mais...@archlinux.us ---
Interesting. No, haven't tried with an LLVM that recent. I'll post when I have
results.
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the
On 12/5/18 1:44 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:37 PM Tapani Pälli wrote:
On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:15 PM Tapani Pälli wrote:
On 12/5/18 1:01 PM, Bas Nieuwenhuizen wrote:
On Fri, Sep 7, 2018 at 12:54 AM Kevin
On 4.12.2018 23.52, Dylan Baker wrote:
> This little series is aimed at fixing problems reported by fedora and debian
> when using meson, there's a couple of patches in here for fixing ppc64
> detection
> (tested without llvm), and a couple for gnu hurd (not tested).
>
> Dylan Baker (5):
>
On Tue, Dec 04, 2018 at 08:16:52AM +0100, Iago Toral Quiroga wrote:
> Source0 and Destination extract the floating-point precision automatically
> from the SrcType and DstType instruction fields respectively when they are
> set to types :F or :HF. For Source1 and Source2 operands, we use the new
>
Reviewed-by: Topi Pohjolainen
On Tue, Dec 04, 2018 at 08:16:51AM +0100, Iago Toral Quiroga wrote:
> ---
> src/intel/compiler/brw_eu_emit.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/compiler/brw_eu_emit.c
> b/src/intel/compiler/brw_eu_emit.c
> index
Required for VK_KHR_shader_atomic_int64.
Signed-off-by: Samuel Pitoiset
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index
On Wed, Dec 5, 2018 at 12:15 PM Tapani Pälli wrote:
>
>
>
> On 12/5/18 1:01 PM, Bas Nieuwenhuizen wrote:
> > On Fri, Sep 7, 2018 at 12:54 AM Kevin Strasser
> > wrote:
> >>
> >> Android P and earlier expect that the surface supports storage images, and
> >> so many of the tests fail when the
On Tuesday, 2018-12-04 13:52:19 -0800, Dylan Baker wrote:
> Otherwise there will be symbol collisions for the vector name.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108943
> Fixes: 34bbb24ce7702658cdc4e9d34a650e169716c39e
>("meson: Add support for ppc
On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:15 PM Tapani Pälli wrote:
On 12/5/18 1:01 PM, Bas Nieuwenhuizen wrote:
On Fri, Sep 7, 2018 at 12:54 AM Kevin Strasser wrote:
Android P and earlier expect that the surface supports storage images, and
so many of the
On Wed, Dec 5, 2018 at 12:37 PM Tapani Pälli wrote:
>
>
>
> On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
> > On Wed, Dec 5, 2018 at 12:15 PM Tapani Pälli wrote:
> >>
> >>
> >>
> >> On 12/5/18 1:01 PM, Bas Nieuwenhuizen wrote:
> >>> On Fri, Sep 7, 2018 at 12:54 AM Kevin Strasser
> >>> wrote:
>
On Wed, Dec 5, 2018 at 12:51 PM Tapani Pälli wrote:
>
>
>
> On 12/5/18 1:44 PM, Bas Nieuwenhuizen wrote:
> > On Wed, Dec 5, 2018 at 12:37 PM Tapani Pälli wrote:
> >>
> >>
> >>
> >> On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
> >>> On Wed, Dec 5, 2018 at 12:15 PM Tapani Pälli
> >>> wrote:
>
On Wed, Dec 5, 2018 at 2:14 PM Samuel Pitoiset
wrote:
>
> Nothing to do, the compiler already handles that.
>
> All new dEQP.VK.ubo.* and dEQP.VK.ssbo.* pass, except some
> 16-bit tests that are quite related to fdo bug #108114.
>
> Signed-off-by: Samuel Pitoiset
> ---
>
Rb
On December 5, 2018 07:26:22 Samuel Pitoiset wrote:
Required for VK_KHR_shader_atomic_int64.
Signed-off-by: Samuel Pitoiset
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=108952
Bug ID: 108952
Summary: mesa-git broke cinnamon, temporary downgrade fix
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
On Tue, Dec 04, 2018 at 08:16:38AM +0100, Iago Toral Quiroga wrote:
> The hardware doesn't support half-float for these.
Reviewed-by: Topi Pohjolainen
> ---
> src/intel/compiler/brw_nir.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/src/intel/compiler/brw_nir.c
On Tue, Dec 04, 2018 at 08:16:48AM +0100, Iago Toral Quiroga wrote:
> The original SrcType is a 3-bit field that takes a subset of the types
> supported for the hardware for 3-source instructions. Since gen8,
> when the half-float type was added, 3-source floating point operations
> can use use
On 12/5/18 1:01 PM, Bas Nieuwenhuizen wrote:
On Fri, Sep 7, 2018 at 12:54 AM Kevin Strasser wrote:
Android P and earlier expect that the surface supports storage images, and
so many of the tests fail when the framework checks for that support. The
framework also includes various image
On Wed, Dec 05, 2018 at 11:23:06AM +0100, Iago Toral wrote:
> On Tue, 2018-12-04 at 18:16 +0200, Pohjolainen, Topi wrote:
> > On Tue, Dec 04, 2018 at 08:16:36AM +0100, Iago Toral Quiroga wrote:
> > > Since we handle booleans as integers this makes more sense.
> >
> > If this is applied before
https://bugs.freedesktop.org/show_bug.cgi?id=108949
--- Comment #1 from Connor Abbott ---
This should be fixed by
https://github.com/llvm-mirror/llvm/commit/e3924b1c15606bb5bf98392e0c20e731b4965311
which was just committed 5 days ago. You'll need to build LLVM and Mesa master
to try it out.
--
On Wed, Dec 05, 2018 at 12:26:06PM +0100, Iago Toral wrote:
> On Wed, 2018-12-05 at 13:20 +0200, Pohjolainen, Topi wrote:
> > On Wed, Dec 05, 2018 at 11:53:44AM +0100, Iago Toral wrote:
> > > On Wed, 2018-12-05 at 11:39 +0200, Pohjolainen, Topi wrote:
> > > > I remember people preferring to order
On 12/5/18 2:00 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:51 PM Tapani Pälli wrote:
On 12/5/18 1:44 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:37 PM Tapani Pälli wrote:
On 12/5/18 1:22 PM, Bas Nieuwenhuizen wrote:
On Wed, Dec 5, 2018 at 12:15 PM Tapani
Before this commit, there were two copies of the algorithm: one in C,
that we would use to figure out what bit-size to give the replacement
expression, and one in Python, that emulated the C one and tried to
prove that the C algorithm would never fail to correctly assign
bit-sizes. That seemed
On Wed, 2018-12-05 at 14:58 +0200, Pohjolainen, Topi wrote:
> On Tue, Dec 04, 2018 at 08:16:52AM +0100, Iago Toral Quiroga wrote:
> > Source0 and Destination extract the floating-point precision
> > automatically
> > from the SrcType and DstType instruction fields respectively when
> > they are
>
Nothing to do, the compiler already handles that.
All new dEQP.VK.ubo.* and dEQP.VK.ssbo.* pass, except some
16-bit tests that are quite related to fdo bug #108114.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 6 ++
src/amd/vulkan/radv_extensions.py | 1 +
2 files
On Wed, Dec 05, 2018 at 02:04:16PM +0100, Iago Toral wrote:
> On Wed, 2018-12-05 at 14:58 +0200, Pohjolainen, Topi wrote:
> > On Tue, Dec 04, 2018 at 08:16:52AM +0100, Iago Toral Quiroga wrote:
> > > Source0 and Destination extract the floating-point precision
> > > automatically
> > > from the
https://bugs.freedesktop.org/show_bug.cgi?id=108949
Bug ID: 108949
Summary: RADV: Subgroup codegen is sub-optimal
Product: Mesa
Version: 18.2
Hardware: Other
OS: All
Status: NEW
Severity: normal
On Wed, 2018-12-05 at 13:20 +0200, Pohjolainen, Topi wrote:
> On Wed, Dec 05, 2018 at 11:53:44AM +0100, Iago Toral wrote:
> > On Wed, 2018-12-05 at 11:39 +0200, Pohjolainen, Topi wrote:
> > > I remember people preferring to order things 16, 32, 64 before.
> > > Should
> > > we follow that here as
nvm, I somehow didn't notice that "if (atom->dType != TYPE_F32)" check...
On Wed, Dec 5, 2018 at 3:43 PM Karol Herbst wrote:
>
> but uhm, how would that work if you assert(atom->subOp ==
> NV50_IR_SUBOP_ATOM_ADD); inside handleSharedATOMGM107? I thought
> that's only needed for fadd, not for all
On Wed, Dec 5, 2018 at 4:59 AM Karol Herbst wrote:
>
> On Wed, Dec 5, 2018 at 6:30 AM Ilia Mirkin wrote:
> >
> > Signed-off-by: Ilia Mirkin
> > ---
> > .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 49 +++
> > .../nouveau/codegen/nv50_ir_lowering_nvc0.h | 1 +
> > 2 files
but uhm, how would that work if you assert(atom->subOp ==
NV50_IR_SUBOP_ATOM_ADD); inside handleSharedATOMGM107? I thought
that's only needed for fadd, not for all atoms
On Wed, Dec 5, 2018 at 3:17 PM Ilia Mirkin wrote:
>
> On Wed, Dec 5, 2018 at 4:59 AM Karol Herbst wrote:
> >
> > On Wed, Dec
Hi guys
On Wed, 5 Dec 2018 at 10:49, Bas Nieuwenhuizen wrote:
>
> Reviewed-by: Bas Nieuwenhuizen
> On Wed, Dec 5, 2018 at 11:43 AM Samuel Pitoiset
> wrote:
> >
> > In case we are unlucky if the low part is 0x.
> >
> > Fixes: 5d6a560a29 ("radv: do not use the availability bit for
Rb me. Now you can review my comparison patches.
On December 5, 2018 06:20:49 Connor Abbott wrote:
Before this commit, there were two copies of the algorithm: one in C,
that we would use to figure out what bit-size to give the replacement
expression, and one in Python, that emulated the C
On Tue, 4 Dec 2018 at 18:51, Kristian H. Kristensen wrote:
>
> A couple of simple fixes for building on Android with autotools.
Reviewed-by: Emil Velikov
-Emil
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Added in 824cfc1ee5e0aba15b676 "radv: rework the TC-compat HTILE
hardware bug with COND_EXEC", but it is unused.
Signed-off-by: Eric Engestrom
---
src/amd/vulkan/radv_cmd_buffer.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_pipeline.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index d55e51adcbb..cadf9288ad9 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_extensions.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index 9ca42d998ef..d572df3c342 100644
--- a/src/intel/vulkan/anv_extensions.py
+++
We were returning 3*pi/4 when we should return 0.0 according to IEEE 754.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
If we have fsin or fcos trigonometric operations with constant values as inputs,
we will multiply the result by 0.7 in brw_nir_apply_trig_workarounds,
making the result wrong. Running nir_opt_constant_folding before, we will
calculate correctly the result for these trignometric ops.
Until now, it was using the floating point version of fmin, instead
of the double version.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_opcodes.py
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/shader_enums.h | 14 ++
src/compiler/shader_info.h| 3 +++
src/compiler/spirv/spirv_to_nir.c | 26 ++
3 files changed, 43 insertions(+)
diff --git a/src/compiler/shader_enums.h
If x < 0 -> atan2(x, x) = -3*pi/4.
If x > 0 -> atan2(x, x) = pi/4.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu.h | 4 ---
src/intel/compiler/brw_eu_emit.c| 36 -
src/intel/compiler/brw_fs_generator.cpp | 13 +++--
src/intel/compiler/brw_fs_nir.cpp | 18 +++--
4 files
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_device.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 17b73c115cd..af07c7c831e 100644
--- a/src/intel/vulkan/anv_device.c
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu.h | 4
src/intel/compiler/brw_eu_defines.h | 10 ++
src/intel/compiler/brw_eu_emit.c| 26 +
src/intel/compiler/brw_fs_generator.cpp | 8 +++-
We need this function to emit code that setups the control register later with
the defined execution mode for the shader.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.h | 1 +
src/intel/compiler/brw_fs_visitor.cpp | 52 +++
2 files
The remove_extra_rounding_modes() optimization will remove duplicated
rounding mode changes.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp
From: Kirill Burtsev
Currently we distinguish if the drawable is a window or pixmap by
checking xcb_present_select_input throws an error or not.
Yet, we don't always free the error state returned by xcb.
Cc: Kirill Burtsev
Cc: Boyan Ding
Fixes: 6bd9ba7d074 ("loader: Add dri3 helper")
https://bugs.freedesktop.org/show_bug.cgi?id=108742
--- Comment #2 from Samuel Pitoiset ---
Did you bisect?
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For the python bits:
Reviewed-by: Dylan Baker
Quoting Connor Abbott (2018-12-05 04:20:30)
> Before this commit, there were two copies of the algorithm: one in C,
> that we would use to figure out what bit-size to give the replacement
> expression, and one in Python, that emulated the C one and
Hello,
This patch series implements the support for
VK_KHR_shader_float_controls for Intel platforms (Broadwell and
later).
This extension enables efficient use of floating-point computations
through the ability to query and override the implementation's default
behavior for rounding modes,
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 7 +++
2 files changed, 8 insertions(+)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index e745cc15fc5..21c3d371a63 100644
---
https://bugs.freedesktop.org/show_bug.cgi?id=108914
--- Comment #16 from tempel.jul...@gmail.com ---
Looking fine now with mesa-git, thanks again!
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Hi Emil,
Yeah, that looks correct, Thanks!
On 12/5/18 4:22 PM, Emil Velikov wrote:
Hi guys
On Wed, 5 Dec 2018 at 10:49, Bas Nieuwenhuizen wrote:
Reviewed-by: Bas Nieuwenhuizen
On Wed, Dec 5, 2018 at 11:43 AM Samuel Pitoiset
wrote:
In case we are unlucky if the low part is 0x.
So my compiler doesn't want to show me warnings? That's something I
would need to fix up. Anyways,
Reviewed-by: Samuel Pitoiset
On 12/5/18 4:44 PM, Eric Engestrom wrote:
Added in 824cfc1ee5e0aba15b676 "radv: rework the TC-compat HTILE
hardware bug with COND_EXEC", but it is unused.
This corresponds to commit 17da9f8231f78cf519b4958c2229463a63ead9e2 on GitHub.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/spirv.core.grammar.json | 316 +++--
src/compiler/spirv/spirv.h | 84 +++---
2 files changed, 281 insertions(+), 119
This reverts commit c4ab1bdcc9710e3c7cc7115d3be9c69b7e7712ef. We need
to check the arguments looking for NaNs, because they can introduce
failures in tests for FOrd*, specially when running
VK_KHR_shader_float_control tests in CTS.
Signed-off-by: Samuel Iglesias Gonsálvez
---
According to VK_KHR_shader_float_controls:
"Denormalized values obtained via unpacking an integer into a vector
of values with smaller bit width and interpreting those values as
floating-point numbers must: be flushed to zero, unless the entry point
is declared with the code:DenormPreserve
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/util/Makefile.sources | 2 +
src/util/double.c | 197 ++
src/util/double.h | 46 +
src/util/meson.build | 2 +
4 files changed, 247 insertions(+)
create mode 100644
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/util/half_float.c | 74 +++
src/util/half_float.h | 7
2 files changed, 81 insertions(+)
diff --git a/src/util/half_float.c b/src/util/half_float.c
index 63aec5c5c14..5fdcb20045b 100644
---
This would do constant folding and also flush to zero denorms operands before
the nir_opt_algebraic is executed.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_nir.c
This way, we can implement its support later if SPIR-V supports it.
Right now, the RTZ, RTNE support in SPIR-V in FPRoundingMode only
applies to f2f16 conversions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 22 +-
1 file changed, 21
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 32e0817ce02..18dcd92219c 100644
--- a/src/intel/compiler/brw_fs.cpp
+++
The denorm mode is set in the control register, no need to do something else.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index
Reviewed-by: Bas Nieuwenhuizen
On Wed, Dec 5, 2018 at 4:44 PM Eric Engestrom wrote:
>
> Added in 824cfc1ee5e0aba15b676 "radv: rework the TC-compat HTILE
> hardware bug with COND_EXEC", but it is unused.
>
> Signed-off-by: Eric Engestrom
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 1 -
> 1 file
It adds round-towards-zero and round-to-nearest-even opcodes for
floating point conversions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 2 +-
src/compiler/nir/nir_opcodes_c.py | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opt_constant_folding.c | 74 +++--
1 file changed, 68 insertions(+), 6 deletions(-)
diff --git a/src/compiler/nir/nir_opt_constant_folding.c
b/src/compiler/nir/nir_opt_constant_folding.c
index
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 0115648cbb0..69588f56968 100644
---
If we have (inf - inf) we should return NaN, not 0.0. Same for
(NaN - NaN) case.
Fixes tests in Vulkan CTS that produce such kind subtractions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opt_algebraic.py | 2 --
1 file changed, 2 deletions(-)
diff --git
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_lower_double_ops.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/compiler/nir/nir_lower_double_ops.c
b/src/compiler/nir/nir_lower_double_ops.c
index b3543bc6963..97b825d2fdb 100644
---
1 - 100 of 138 matches
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