Re: [Mesa-dev] [PATCH v3 2/3] nir: add nir_opt_vectorize_io()

On 15/2/19 7:51 am, Jason Ekstrand wrote: ping? You seem to be asking me to rewrite the entire meat of the pass without any suggestion of how to achieve it, I didn't know how to reply. Recombining stores is tricky, this pass is based on Conners series for vectorizing alu instructions[1].

[Mesa-dev] [PATCH 3/3] panfrost: Swap order of tiled texture (de)alloc

Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_resource.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/panfrost/pan_resource.c b/src/gallium/drivers/panfrost/pan_resource.c index b13461013f5..4be371ba32e 100644 ---

[Mesa-dev] [Bug 106644] [llvmpipe] Mesa 18.3.1 fails lp_test_format, lp_test_arit, lp_test_conv

https://bugs.freedesktop.org/show_bug.cgi?id=106644 erhar...@mailbox.org changed: What|Removed |Added Attachment #140433|0 |1 is obsolete|

[Mesa-dev] [Bug 109615] 19.0.0_rc4 fails u_format_test on ppc64

https://bugs.freedesktop.org/show_bug.cgi?id=109615 erhar...@mailbox.org changed: What|Removed |Added Summary|19.0.0_rc2 fails|19.0.0_rc4 fails

Re: [Mesa-dev] [RFC] gpu/docs: Clarify what userspace means for gl

On Thu, Feb 14, 2019 at 4:00 AM Daniel Vetter wrote: > > Clear rules avoid arguing. > > I think it'd be good to have an equally solid list on the kms side. > But kms is much more meant to be a standard, and the list of userspace > projects we've accepted in the past is constantly shifting and >

Re: [Mesa-dev] [PATCH] meson: egl: correctly manage loader/xmlconfig

On Thu, 14 Feb 2019 11:43:13 + Emil Velikov wrote: > From: Emil Velikov > > Earlier commit introduced support for haiku yet did not properly > annotate the loader/xmlconfig dependencies. > > Thus we ended up adding inc_loader for each !haiku platform - see > 659910eda01 9a96bf0ecd0

Re: [Mesa-dev] [PATCH v4 02/40] intel/compiler: add a NIR pass to lower conversions

On Tue, Feb 12, 2019 at 5:56 AM Iago Toral Quiroga wrote: > Some conversions are not directly supported in hardware and need to be > split in two conversion instructions going through an intermediary type. > Doing this at the NIR level simplifies a bit the complexity in the backend. > > v2: > -

[Mesa-dev] [PATCH 2/3] panfrost: Free imported BOs

Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_resource.c | 4 src/gallium/drivers/panfrost/pan_resource.h | 6 ++ src/gallium/drivers/panfrost/pan_screen.h | 2 ++ 3 files changed, 12 insertions(+) diff --git a/src/gallium/drivers/panfrost/pan_resource.c

Re: [Mesa-dev] [PATCH 0/4] RadeonSI: Upload constants to VRAM via SDMA

Am 12.02.2019 05:10, schrieb Dieter Nützel: Am 12.02.2019 03:22, schrieb Dieter Nützel: Am 12.02.2019 00:40, schrieb Dieter Nützel: Sorry that I step in so late, but the whole family recover slowly from a bad flu... Tried your 'latest" three series altogether with my Polaris 20 (NIR!). UH

[Mesa-dev] OT: POLL Do you want RTX? Cross-website-post.

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hello, I heard from 1 of the people that do HW reviews that AMD was considering implementing their very own RTX and looking at what people think of RTX. I created a poll on LQ: https://www.linuxquestions.org/questions/showthread.php?p=5962219 and in

Re: [Mesa-dev] [PATCH 2/5] intel/fs: Lower integer multiply correctly when destination stride equals 4.

Jason Ekstrand writes: > On Fri, Jan 18, 2019 at 6:09 PM Francisco Jerez > wrote: > >> Because the "low" temporary needs to be accessed with word type and >> twice the original stride, attempting to preserve the alignment of the >> original destination can potentially lead to instructions with

[Mesa-dev] [Bug 109535] [Tracker] Mesa 19.0 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=109535 Bug 109535 depends on bug 109601, which changed state. Bug 109601 Summary: [Regression] RuneLite GPU rendering broken on 18.3.x https://bugs.freedesktop.org/show_bug.cgi?id=109601 What|Removed |Added

Re: [Mesa-dev] [PATCH v6 5/5] gallium/auxiliary/vl: Add video compositor compute shader render

On Thu, Feb 14, 2019, 5:13 PM James Zhu > On 2019-02-14 4:44 p.m., Marek Olšák wrote: > > This still creates gfx shaders. If we switch MM to compute IBs, calling > any gfx function will crash. > > Right now only fs_video_buffer/fs_weave_rgb/fs_rgba have compute shader > replacement. > > The other

[Mesa-dev] [PATCH v5 02/40] intel/compiler: add a NIR pass to lower conversions

Some conversions are not directly supported in hardware and need to be split in two conversion instructions going through an intermediary type. Doing this at the NIR level simplifies a bit the complexity in the backend. v2: - Consider fp16 rounding conversion opcodes - Properly handle swizzles

Re: [Mesa-dev] [PATCH v4 02/40] intel/compiler: add a NIR pass to lower conversions

On Thu, 2019-02-14 at 16:59 -0600, Jason Ekstrand wrote: > On Tue, Feb 12, 2019 at 5:56 AM Iago Toral Quiroga > wrote: > > Some conversions are not directly supported in hardware and need to > > be > > > > split in two conversion instructions going through an intermediary > > type. > > > >

Re: [Mesa-dev] [PATCH v3 2/3] nir: add nir_opt_vectorize_io()

On 15/2/19 1:43 pm, Jason Ekstrand wrote: On Thu, Feb 14, 2019 at 7:25 PM Timothy Arceri > wrote: On 15/2/19 7:51 am, Jason Ekstrand wrote: > ping? You seem to be asking me to rewrite the entire meat of the pass without any suggestion of how to

Re: [Mesa-dev] [PATCH v3 2/3] nir: add nir_opt_vectorize_io()

On 15/2/19 1:43 pm, Jason Ekstrand wrote: On Thu, Feb 14, 2019 at 7:25 PM Timothy Arceri > wrote: On 15/2/19 7:51 am, Jason Ekstrand wrote: > ping? You seem to be asking me to rewrite the entire meat of the pass without any suggestion of how to

[Mesa-dev] [PATCH 2/2] panfrost: Preserve w sign in perspective division

This fixes issues where polygons that should be culled (due to negative w, for instance) may not be. Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/midgard/midgard_compile.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 0/2] panfrost: Fix (depth) clipping bugs

This pair of patches cleans up and resolves bugs related to coordinate clipping, manifesting as severe environmental rendering glitches in various games. Alyssa Rosenzweig (2): panfrost: Cleanup mali_viewport (clipping) code panfrost: Preserve w sign in perspective division

Re: [Mesa-dev] [PATCH 2/5] intel/fs: Lower integer multiply correctly when destination stride equals 4.

On February 14, 2019 21:59:18 Francisco Jerez wrote: Jason Ekstrand writes: On Fri, Jan 18, 2019 at 6:09 PM Francisco Jerez wrote: Because the "low" temporary needs to be accessed with word type and twice the original stride, attempting to preserve the alignment of the original

[Mesa-dev] [Bug 109617] [oland, clover, llvm5] While-If Problem with Booleans

https://bugs.freedesktop.org/show_bug.cgi?id=109617 --- Comment #4 from Natalia --- I have downloaded LLVM from https://github.com/llvm-mirror/llvm, produced Makefile with CMake, did # make # make install # reboot so that # l /usr/local/bin/ | grep "llvm" -rwxr-xr-x 1 root root 174338016

[Mesa-dev] [PATCH] panfrost: Fix build; depend on libdrm

Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/meson.build | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/panfrost/meson.build b/src/gallium/drivers/panfrost/meson.build index 17fdb5e1e0d..8ea0b8d2025 100644 ---

Re: [Mesa-dev] [PATCH] nir: remove simple dead if detection from nir_opt_dead_cf()

On 15/2/19 4:12 pm, Jason Ekstrand wrote: I think the primary issue we had with dead ifs before is that we were running dce and dead_cf but maybe not peephole_select because it didn't seem applicable.  In principle, I think I like dead_cf being able to handle if statements as well because it

Re: [Mesa-dev] [PATCH 1/5] intel/fs: Exclude control sources from execution type and region alignment calculations.

Jason Ekstrand writes: > On Fri, Jan 18, 2019 at 6:09 PM Francisco Jerez > wrote: > >> Currently the execution type calculation will return a bogus value in >> cases like: >> >> mov_indirect(8) vgrf0:w, vgrf1:w, vgrf2:ud, 32u >> >> Which will be considered to have a 32-bit integer execution

Re: [Mesa-dev] [PATCH v3 2/3] nir: add nir_opt_vectorize_io()

On Thu, Feb 14, 2019 at 7:25 PM Timothy Arceri wrote: > On 15/2/19 7:51 am, Jason Ekstrand wrote: > > ping? > > You seem to be asking me to rewrite the entire meat of the pass without > any suggestion of how to achieve it, I didn't know how to reply. > Right... Sorry, that wasn't incredibly

Re: [Mesa-dev] [PATCH 3/5] intel/fs: Cap dst-aligned region stride to maximum representable hstride value.

Jason Ekstrand writes: > On Fri, Jan 18, 2019 at 6:09 PM Francisco Jerez > wrote: > >> This is required in combination with the following commit, because >> otherwise if a source region with an extended 8+ stride is present in >> the instruction (which we're about to declare legal) we'll end up

[Mesa-dev] [PATCH 1/3] panfrost: Fix various leaks unmapping resources

Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_resource.c | 22 - src/gallium/drivers/panfrost/pan_screen.h | 4 +++- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/panfrost/pan_resource.c

[Mesa-dev] [Bug 109333] mesa, meson: Need ability to remember PKG_CONFIG_PATH

https://bugs.freedesktop.org/show_bug.cgi?id=109333 --- Comment #3 from Dylan Baker --- What exactly are you wanting? We (meson) have been trying not to use environment variables when possible because they are so awful to use on Windows. Our goal has been to make config files more comprehensive

Re: [Mesa-dev] [PATCH] nir: remove simple dead if detection from nir_opt_dead_cf()

I think the primary issue we had with dead ifs before is that we were running dce and dead_cf but maybe not peephole_select because it didn't seem applicable. In principle, I think I like dead_cf being able to handle if statements as well because it seems like a thing it should do. However, it's

[Mesa-dev] POLL Do you want RTX? Cross-website-post.

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hello, I heard from 1 of the people that do HW reviews that AMD was considering implementing their very own RTX and looking at what people think of RTX. I created a poll on LQ: https://www.linuxquestions.org/questions/showthread.php?p=5962219 and in

[Mesa-dev] [Bug 109064] temp_comp_access::get_required_live_range: enclosing_scope_first_write is NULL

https://bugs.freedesktop.org/show_bug.cgi?id=109064 --- Comment #1 from Alex Xu (Hello71) --- Still broken in 19.0.0_rc4. #0 0x7f0322468821 in get_temp_registers_required_live_ranges(void*, exec_list*, int, register_live_range*, int, array_live_range*) () from

Re: [Mesa-dev] [PATCH 3/3] egl/sl: use kms_swrast with vgem instead of a random GPU

On Tue, 5 Feb 2019 at 15:35, Emil Velikov wrote: > > From: Emil Velikov > > VGEM and kms_swrast were introduced to work with one another. > > All we do is CPU rendering to dumb buffers. There is no reason to carve > out GPU memory, increasing the memory pressure on a device that could > make a

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #28 from Mark Janes --- Chris Forbes at google found a patch that explains at least some of the reason for this test regression: https://android-review.googlesource.com/c/platform/external/deqp/+/901894 I just realized that this

[Mesa-dev] [PATCH] radv: write the alpha channel of MRT0 when alpha coverage is enabled

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109597 Cc: 18.3 19.0 Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_pipeline.c | 8 1 file changed, 8 insertions(+) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index

[Mesa-dev] [Bug 109333] mesa, meson: Need ability to remember PKG_CONFIG_PATH

https://bugs.freedesktop.org/show_bug.cgi?id=109333 --- Comment #5 from Emil Velikov --- Food for though: AFAICT the concept of reproducible builds relies heavily of having consistent environment. It even suggests to explicitly set SOURCE_DATE_EPOCH although there could be others. Be that

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #29 from Mark Janes --- *** Bug 109260 has been marked as a duplicate of this bug. *** -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list

[Mesa-dev] [PATCH 2/2] anv/image: fix offset's alignment to the surface alignment

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 3999c7399d0..f4a65044a3b 100644 --- a/src/intel/vulkan/anv_image.c +++

[Mesa-dev] [PATCH v6 2/5] i965: Faking the ETC2 compression on Gen < 8 GPUs using two miptrees.

GPUs Gen < 8 cannot sample ETC2 formats. So far, they converted the compressed EAC/ETC2 images to non-compressed RGBA images. When GetCompressed* functions were called, the pixels were returned in this RGBA format and not the compressed format that was expected. Trying to fix this problem, we use

[Mesa-dev] [PATCH 1/2] isl: remove the cache line size alignment requirement

There are formats which bpp are not aligned to a power-of-two and that can cause problems in the checks we do. The cacheline size was a requirement for using the BLT engine, which we don't use anymore except for a few things on old HW, so we drop it. Fixes CTS's CL#3500 test:

[Mesa-dev] [PATCH v6 1/5] i965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*

From: Nanley Chery Use more generic field names. We'll reuse these fields for a workaround with ASTC miptrees. Reviewed-by: Eleni Maria Stea --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 16

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #27 from asimiklit --- (In reply to Ilia Mirkin from comment #24) > """ > But according to next comment it should be 0 because of the BlockB[0] was > optimized > and there is the BlockB[1] only: > >/* The

[Mesa-dev] [Bug 109333] mesa, meson: Need ability to remember PKG_CONFIG_PATH

https://bugs.freedesktop.org/show_bug.cgi?id=109333 --- Comment #4 from Jan Vesely --- (In reply to Dylan Baker from comment #3) > What exactly are you wanting? We (meson) have been trying not to use > environment variables when possible because they are so awful to use on > Windows. Our goal

Re: [Mesa-dev] [PATCH] nir: remove simple dead if detection from nir_opt_dead_cf()

Reviewed-by: Connor Abbott I agree that if we ever need to bring this back, we should just check for both branches empty and no phis afterwards. On Thu, Feb 14, 2019 at 2:38 AM Timothy Arceri wrote: > This was probably useful when it was first written, however it > looks to be no longer

[Mesa-dev] [Bug 109641] GLX swrast driver leaks shared memory segments

https://bugs.freedesktop.org/show_bug.cgi?id=109641 Bug ID: 109641 Summary: GLX swrast driver leaks shared memory segments Product: Mesa Version: 18.0 Hardware: All OS: Linux (All) Status: NEW Severity:

Re: [Mesa-dev] [PATCH] radv: fix invalid element type when filling vertex input default values

Reviewed-by: Bas Nieuwenhuizen On Fri, Feb 15, 2019 at 3:57 PM Samuel Pitoiset wrote: > > The elements added into a vector should have the same type as the > first one, otherwise this hits an assertion in LLVM. > > Fixes: 4b3549c0846 ("radv: reduce the number of loaded channels for vertex >

[Mesa-dev] [ANNOUNCE] Mesa 18.3.4 release candidate

Hello list, The candidate for the Mesa 18.3.4 is now available. Currently we have: - 34 queued - 1 nominated (outstanding) - and 16 rejected patches The current queue consists of: A fix in the XvMC state-tracker, which was causing some video attributes to not take affect. On the video front

Re: [Mesa-dev] [RFC] gpu/docs: Clarify what userspace means for gl

On Thu, Feb 14, 2019 at 05:47:06PM -0500, Rob Clark wrote: > On Thu, Feb 14, 2019 at 4:00 AM Daniel Vetter wrote: > > > > Clear rules avoid arguing. > > > > I think it'd be good to have an equally solid list on the kms side. > > But kms is much more meant to be a standard, and the list of

Re: [Mesa-dev] [PATCH 2/2] i965: Be resilient in the face of GPU hangs

Quoting Chris Wilson (2019-02-14 12:05:00) > If we hang the GPU and end up banning our context, we will no longer be > able to submit and abort with an error (exit(1) no less). As we submit > minimal incremental batches that rely on the logical context state of > previous batches, we can not rely

[Mesa-dev] [PATCH] radv: fix invalid element type when filling vertex input default values

The elements added into a vector should have the same type as the first one, otherwise this hits an assertion in LLVM. Fixes: 4b3549c0846 ("radv: reduce the number of loaded channels for vertex input fetches") reported-by: Philip Rebohle Signed-off-by: Samuel Pitoiset ---

[Mesa-dev] [PATCH v6 0/5] improved the support for ETC2 formats on Gen 7

Intel Gen7 GPUs don't support the ETC2 formats natively and in order to show the pixels properly we decompress them and create decompressed miptrees. The problem with that is that the functions that map the miptrees for reading (for example the GetCompressed* calls), and would be supposed to read

[Mesa-dev] [PATCH v6 3/5] i965: Fixed the CopyImageSubData for ETC2 on Gen < 8

For CopyImageSubData to copy the data during the 1st draw call, we need to update the shadow tree right before the rendering. v2: - Added assertion that the miptree doesn't need update at the time we update the texture surface. (Nanley Chery) v3: - As we now update the tree before the

[Mesa-dev] [PATCH 1/2] isl: remove the cache line size alignment requirement

There are formats which bpp are not aligned to a power-of-two and that can cause problems in the checks we do. The cacheline size was a requirement for using the BLT engine, which we don't use anymore except for a few things on old HW, so we drop it. Fixes CTS's CL#3500 test:

[Mesa-dev] [PATCH v6 5/5] i965: Removed the field etc_format from the struct intel_mipmap_tree

After the previous changes to emulate the ETC/EAC formats using the secondary shadow miptree, the etc_format field of the intel_mipmap_tree struct became redundant and the remaining check that used it has been replaced. (Nanley Chery) --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +-

[Mesa-dev] [Bug 109535] [Tracker] Mesa 19.0 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=109535 Mark Janes changed: What|Removed |Added Depends on||109594 Referenced Bugs:

Re: [Mesa-dev] [PATCH 2/3] panfrost: Free imported BOs

On Fri, 15 Feb 2019 at 08:50, Alyssa Rosenzweig wrote: > > Signed-off-by: Alyssa Rosenzweig > --- > src/gallium/drivers/panfrost/pan_resource.c | 4 > src/gallium/drivers/panfrost/pan_resource.h | 6 ++ > src/gallium/drivers/panfrost/pan_screen.h | 2 ++ > 3 files changed, 12

Re: [Mesa-dev] [PATCH 3/3] panfrost: Swap order of tiled texture (de)alloc

On Fri, 15 Feb 2019 at 08:50, Alyssa Rosenzweig wrote: > > Signed-off-by: Alyssa Rosenzweig > --- > src/gallium/drivers/panfrost/pan_resource.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/src/gallium/drivers/panfrost/pan_resource.c >

Re: [Mesa-dev] [PATCH] panfrost: Backport driver to Mali T600/T700

Hi Alyssa, On Thu, 14 Feb 2019 at 01:58, Alyssa Rosenzweig wrote: > > There are a few differenes between Mali T860 (Panfrost's primary > reference target) and the older Midgard generations (T600/T700): > > - Miscellaneous different magic numbers. It's not clear what these > numbers mean on

[Mesa-dev] [Bug 109645] build error on arm64: tegra_screen.c:33: /usr/include/xf86drm.h:41:10: fatal error: drm.h: No such file or directory

https://bugs.freedesktop.org/show_bug.cgi?id=109645 Bug ID: 109645 Summary: build error on arm64: tegra_screen.c:33: /usr/include/xf86drm.h:41:10: fatal error: drm.h: No such file or directory Product: Mesa

[Mesa-dev] [Bug 109646] New video compositor compute shader render glitches mpv

https://bugs.freedesktop.org/show_bug.cgi?id=109646 --- Comment #1 from leoxs...@gmail.com --- Thanks for the testing. We'll have a look. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___

Re: [Mesa-dev] [PATCH v2] egl/dri2: try to bind old context if bindContext failed

On Wed, 13 Feb 2019 at 09:32, Luigi Santivetti wrote: > > Hello Emil, > > thanks for your feedback, I agree, dri2_make_current() looks complex. > I'll comment inline. > > Emil Velikov writes: > > > Hi all, > > > > Haven't looked it this has landed or not. > > > > On Tue, 5 Feb 2019 at 16:41,

Re: [Mesa-dev] [PATCH 1/3] panfrost: Fix various leaks unmapping resources

Hi Alyssa, On Fri, 15 Feb 2019 at 08:50, Alyssa Rosenzweig wrote: > > Signed-off-by: Alyssa Rosenzweig > --- > src/gallium/drivers/panfrost/pan_resource.c | 22 - > src/gallium/drivers/panfrost/pan_screen.h | 4 +++- > 2 files changed, 16 insertions(+), 10 deletions(-) >

Re: [Mesa-dev] [PATCH] panfrost: Fix build; depend on libdrm

On Fri, 15 Feb 2019 at 08:55, Alyssa Rosenzweig wrote: > > Signed-off-by: Alyssa Rosenzweig > --- > src/gallium/drivers/panfrost/meson.build | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/src/gallium/drivers/panfrost/meson.build > b/src/gallium/drivers/panfrost/meson.build > index

[Mesa-dev] [Bug 109646] New video compositor compute shader render glitches mpv

https://bugs.freedesktop.org/show_bug.cgi?id=109646 Bug ID: 109646 Summary: New video compositor compute shader render glitches mpv Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All)

[Mesa-dev] [Bug 109646] New video compositor compute shader render glitches mpv

https://bugs.freedesktop.org/show_bug.cgi?id=109646 --- Comment #2 from jam...@amd.com --- bmil...@gmail.com: Problem 1,4: the blend implementation seems incomplete with compute shader. Problem 3: could you provide the clip and the screen capture? I want to check on my bench. Problem 2: So far

[Mesa-dev] [PATCH v6 4/5] i965: Enabled the OES_copy_image extension on Gen 7 GPUs

OES_copy_image extension was disabled on Gen7 due to the lack of support for ETC2 images. Enabled it back. (Kenneth Graunke) v2: - Removed the blank lines in the comments above OES_copy_image and OES_texture_view extensions in intel_extensions.c (Nanley Chery) ---

Re: [Mesa-dev] [PATCH] nir: remove simple dead if detection from nir_opt_dead_cf()

On Fri, Feb 15, 2019 at 3:55 AM Timothy Arceri wrote: > > On 15/2/19 4:12 pm, Jason Ekstrand wrote: > > I think the primary issue we had with dead ifs before is that we were > > running dce and dead_cf but maybe not peephole_select because it didn't > > seem applicable. In principle, I think I

[Mesa-dev] [PATCH 2/2] anv/image: fix offset's alignment to the surface alignment

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_image.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 3999c7399d0..f4a65044a3b 100644 --- a/src/intel/vulkan/anv_image.c +++

Re: [Mesa-dev] [RFC] gpu/docs: Clarify what userspace means for gl

[Shouldn't send mails before coffee kicks in, some things got lost below] On Fri, Feb 15, 2019 at 10:20 AM Daniel Vetter wrote: > > On Thu, Feb 14, 2019 at 05:47:06PM -0500, Rob Clark wrote: > > On Thu, Feb 14, 2019 at 4:00 AM Daniel Vetter > > wrote: > > > > > > Clear rules avoid arguing. > >

Re: [Mesa-dev] [PATCH v2 4/6] glsl/linker: don't fail non static used inputs without matching outputs

If the updated piglit tests pass on the Nvidia blob as per my reply to those patches and this patch passes on the new and old piglit tests. Then this patch is: Reviewed-by: Timothy Arceri Thanks for fixing this! On 7/2/19 2:58 am, Andres Gomez wrote: If there is no Static Use of an input

Re: [Mesa-dev] [PATCH v5 02/40] intel/compiler: add a NIR pass to lower conversions

On Fri, Feb 15, 2019 at 2:22 AM Iago Toral Quiroga wrote: > Some conversions are not directly supported in hardware and need to be > split in two conversion instructions going through an intermediary type. > Doing this at the NIR level simplifies a bit the complexity in the backend. > > v2: > -

[Mesa-dev] [PATCH v2 06/41] ac/nir: fix 16-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 89a78b43c6f..b260142c177 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH 00/38] radv, ac: 16-bit and 8-bit arithmetic and 8-bit storage

This series add support for: - VK_KHR_shader_float16_int8 - VK_AMD_gpu_shader_half_float - VK_AMD_gpu_shader_int16 - VK_KHR_8bit_storage on VI+. Half floats are disabled on LLVM 7 because of a bug causing large memory usage and long (or unbounded) compilation times with some CTS tests. It is

[Mesa-dev] [PATCH v2 07/41] ac/nir: implement 8-bit nir_load_const_instr

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 1 file changed, 4 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index b260142c177..f39232b91a1 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH v2 03/41] ac: add various helpers for float16/int16/int8

v2: remove ac_get_one(), ac_get_zero(), ac_get_onef() and ac_get_zerof() v2: remove ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 55 ++--- src/amd/common/ac_llvm_build.h | 15 +++-- src/amd/common/ac_nir_to_llvm.c | 30

[Mesa-dev] [PATCH v2 09/41] ac/nir: fix 64-bit nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 691d444db05..741059b5f1a 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 05/41] ac/nir: implement 8-bit ssbo stores

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 17d952d1ae8..89a78b43c6f 100644 --- a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 13/41] ac/nir: make ac_build_fsign work on all bit sizes

v2: don't use ac_get_zerof() and ac_get_onef() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 3b2257e8bf0..23e454385d7 100644

[Mesa-dev] [PATCH v2 20/41] ac/nir: make emit_b2i work on all bit sizes

v2: don't use ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index e459001c1cf..75bb19031bf 100644 ---

[Mesa-dev] [PATCH v2 08/41] ac/nir: implement 8-bit conversions

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index f39232b91a1..691d444db05 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH v2 04/41] ac/nir: implement 8-bit push constant, ssbo and ubo loads

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 37 +++-- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index bed52490bad..17d952d1ae8 100644 ---

[Mesa-dev] [PATCH v2 02/41] radv: ensure export arguments are always float

So that the signature is correct and consistent, the inputs to a export intrinsic should always be 32-bit floats. This and the previous commit fixes a large amount crashes from dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_* tests Fixes: b722b29f10d ('radv: add

[Mesa-dev] [PATCH v2 29/41] ac/nir: make ac_build_bit_count work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +++-- 1 file changed, 7 insertions(+), 26 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index c986f800fa4..46738faea9d 100644 ---

[Mesa-dev] [PATCH v2 36/41] radv: handle all fragment output types

Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 55 --- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 01b8b097ea1..c46eabf3656 100644 ---

[Mesa-dev] [PATCH v2 22/41] compiler/nir: add lowering option for 16-bit ffma

The lowering needs to be disabled for sufficient precision to pass deqp-vk's 16-bit fma test on radv. Signed-off-by: Rhys Perry --- src/broadcom/compiler/nir_to_vir.c| 1 + src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 4 +++-

[Mesa-dev] [PATCH v2 27/41] ac/nir: make ac_build_umsb work on all bit sizes

v2: don't use ac_get_zero() and ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 38 +++--- 1 file changed, 7 insertions(+), 31 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index

[Mesa-dev] [PATCH v2 24/41] ac/nir: implement 8 and 16 bit ac_build_readlane

v2: don't use ac_int_of_size() Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 71eaac4b7bd..aa92c55c822 100644 ---

[Mesa-dev] [PATCH v2 30/41] ac/nir: make ac_build_bitfield_reverse work on all bit sizes

Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 46738faea9d..dff369aae7f 100644 --- a/src/amd/common/ac_llvm_build.c

[Mesa-dev] [PATCH v2 01/41] radv: bitcast 16-bit outputs to integers

16-bit outputs are stored as 16-bit floats in the outputs array, so they have to be bitcast. Fixes: b722b29f10d ('radv: add support for 16bit input/output') Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH v2 34/41] ac/nir: store all outputs as f32

v2: rebase v2: fix 64-bit visit_load_var() Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 14 ++ src/amd/vulkan/radv_nir_to_llvm.c | 22 +- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 37/41] WIP: radv, ac: implement 16-bit interpolation

v2: add to patch series Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +--- src/amd/common/ac_llvm_build.h | 3 ++- src/amd/common/ac_nir_to_llvm.c | 14 +++--- src/amd/vulkan/radv_nir_to_llvm.c| 27

Re: [Mesa-dev] [PATCH v2 37/41] radv, ac: implement 16-bit interpolation

This patch can be ignored. I forgot to delete it and it ended up getting sent. "[PATCH v2 37/41] WIP: radv, ac: implement 16-bit interpolation" is the correct one. On Sat, 16 Feb 2019 at 00:23, Rhys Perry wrote: > > v2: add to patch series > > Signed-off-by: Rhys Perry > --- >

[Mesa-dev] [PATCH v2 33/41] ac/nir, radv: create an array of varying output types

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 68 +++ src/amd/common/ac_shader_abi.h| 1 + src/amd/vulkan/radv_nir_to_llvm.c | 3 ++ 3 files changed, 72 insertions(+) diff --git a/src/amd/common/ac_nir_to_llvm.c

Re: [Mesa-dev] [PATCH] Revert "glsl: relax input->output validation for SSO programs"

Reviewed-by: Timothy Arceri But I think you should add something like the following to the commit message: "This was fixed properly by commit ..." Once you push "glsl/linker: don't fail non static used inputs without matching outputs" On 9/2/19 4:06 am, Andres Gomez wrote: This reverts

[Mesa-dev] [PATCH v2 40/41] ac/nir: have nir_op_f2f16 round to zero

In the hope that one day LLVM will then be able to generate code with vectorized v_cvt_pkrtz_f16_f32 instructions. Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c

[Mesa-dev] [PATCH v2 37/41] radv, ac: implement 16-bit interpolation

v2: add to patch series Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_build.c | 33 +--- src/amd/common/ac_llvm_build.h | 3 ++- src/amd/common/ac_nir_to_llvm.c | 14 +++--- src/amd/vulkan/radv_nir_to_llvm.c| 27

[Mesa-dev] [PATCH v2 38/41] WIP: ac, radv: run LLVM's SLP vectorizer

v2: rebase v2: move LLVMAddSLPVectorizePass to after LLVMAddEarlyCSEMemSSAPass v2: run unconditionally on GFX9 and later v2: mark as WIP because it can make 32-bit code much worse Signed-off-by: Rhys Perry --- src/amd/common/ac_llvm_util.c | 8 ++-- 1 file changed, 6 insertions(+), 2

[Mesa-dev] [PATCH v2 39/41] ac/nir: generate better code for nir_op_f2f16_rtz

Signed-off-by: Rhys Perry --- src/amd/common/ac_nir_to_llvm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 939b8eb13de..8bfc63958ca 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++

[Mesa-dev] [PATCH v2 41/41] radv, docs: expose float16, int16 and int8 features and extensions

v2: rebase v2: mark VK_KHR_8bit_storage as DONE in features.txt Signed-off-by: Rhys Perry --- docs/features.txt | 2 +- src/amd/vulkan/radv_device.c | 17 + src/amd/vulkan/radv_extensions.py | 4 src/amd/vulkan/radv_shader.c | 3 +++ 4 files

[Mesa-dev] [PATCH v2 35/41] radv: store all fragment shader inputs as f32

v2: rebase Signed-off-by: Rhys Perry --- src/amd/vulkan/radv_nir_to_llvm.c | 14 -- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 2002a744545..01b8b097ea1 100644 ---

[Mesa-dev] [PATCH] panfrost: Fix clipping region

Signed-off-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_context.c | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/panfrost/pan_context.c b/src/gallium/drivers/panfrost/pan_context.c index 97df92258da..a4d0719fdc5 100644 ---

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