On Mon, Jan 14, 2019 at 12:36:26PM +, Daniel Stone wrote:
> FWIW, if you go to
> https://gitlab.freedesktop.org/mesa/mesa/commit/SHA1 then you get a
> hyperlink from the web UI which points you to the MR. The API to do
> this is pretty straightforward and amenable to piping through jq:
> https:
---
src/compiler/nir/tests/vars_tests.cpp | 284
++
3 files changed, 552 insertions(+), 176 deletions(-)
Caio Marcelo de Oliveira Filho
"Passes' function names, separated by comma, listed in NIR_SKIP
environment variable will be skipped in debug mode. The mechanism is
hooked into the _PASS macro, like NIR_PRINT."
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/130
Caio
___
One extra character is leaking from the text into the copied line.
The "+ 1" is an artifact from when malloc was used, strndup will add
the extra '\0' after copying text_size bytes (if available).
7c8ee3f0f "util: simplify string duplication logic"
---
tests/util/piglit-shader-test.c | 2 +-
1 fi
Sorry for the wrong list. Sent again to piglit@.
On Sat, Jan 19, 2019 at 03:40:01PM -0800, Caio Marcelo de Oliveira Filho wrote:
> One extra character is leaking from the text into the copied line.
> The "+ 1" is an artifact from when malloc was used, strndup will add
> t
On Sun, Jan 20, 2019 at 09:09:56AM +, Eric Engestrom wrote:
> Yeah, I had that change locally, but didn't push it :]
>
> Reviewed-by: Eric Engestrom
>
> >
> > 7c8ee3f0f "util: simplify string duplication logic"
>
> "Fixes:" ?
Fixed "Fixes" and pushed :-)
Caio
___
Reviewed-by: Caio Marcelo de Oliveira Filho
On Tue, Jan 22, 2019 at 05:36:56PM +, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/vulkan/util/gen_enum_to_str.py | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/vulkan/util/gen_e
ult:
> + return false;
> + }
> +
> + return false;
Optional: unless you plan to add more cases here, consider replacing
the switch with an if (alu->op == ... || alu->op == ...), so you don't
have this noise at the end.
With the
Hi,
> Did you look at any of the HURT? The problem I was seeing was this could end
> up stopping copy propagation from working on some UBOs etc.
They were not UBO cases like yours, but looking at them I've found a
different problem.
> However with this patch we end up with:
>
> load UBO at off
Hi,
> > The different problem I've found was that uses in the phi instruction
> > after the then/else blocks was being replaced, causing churn in the
> > optimizations further on. As a hack, I've ignored phi instructions in
> > the use loop above. HURTs are gone and HELPs continued.
> >
> > The
On Wed, Jan 23, 2019 at 11:01:46AM +, Eric Engestrom wrote:
> On Friday, 2019-01-11 09:50:25 -0800, Caio Marcelo de Oliveira Filho wrote:
> [snip]
> > - To find the discussion associated with a commit in master, I'd
> > search the title in the mailing list archive
This patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
Since it fixes a patch that were marked for stable, maybe add CC:
stable for this one too?
On Sat, Jan 26, 2019 at 08:28:20AM +, Vinson Lee wrote:
> meson.build:166:21: ERROR: Unknown method "verson_compare"
This patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
On Fri, Jan 25, 2019 at 06:37:33PM +0100, Juan A. Suarez Romero wrote:
> When stitching two blocks A and B, where A's last instruction is a jump,
> it is not required that B is empty; it can be plainly removed.
>
> Thi
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/171
Depends on
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/121, only the
last three commits are new.
Caio Marcelo de Oliveira Filho (3):
nir/copy_prop_vars: add tests for indirect array deref
nir/copy_prop_vars
iginated from a conversation with Ken.
Caio Marcelo de Oliveira Filho (3):
i965: skip bit6 swizzle detection in Gen8+
anv: skip bit6 swizzle detection in Gen8+
isl: assert that Gen8+ don't have bit6_swizzling
Series diff --stat
src/intel/isl/isl.c | 3 +
This patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
On Wed, Feb 06, 2019 at 04:43:00PM -0600, Jason Ekstrand wrote:
> It's more clear and means we don't have to update the array every time
> we add an optional texture instruction argument
> ---
> src/intel/compil
Hi Juan,
On Tue, Feb 12, 2019 at 04:37:23PM +0100, Juan A. Suarez Romero wrote:
> On Fri, 2019-02-08 at 15:39 -0600, Jason Ekstrand wrote:
> > I had a chat with Caio about this and I'm skeptical. In general, users of
> > the CF manipulation code shouldn't be stitching two blocks together where
Just saw your patch. I'll review that one then :-)
On Tue, Feb 12, 2019 at 09:38:32AM -0800, Caio Marcelo de Oliveira Filho wrote:
> Hi Juan,
>
> On Tue, Feb 12, 2019 at 04:37:23PM +0100, Juan A. Suarez Romero wrote:
> > On Fri, 2019-02-08 at 15:39 -0600, Jason Ekstrand
tinue block and keep the one from continue list, as it will be
> executed first.
>
> CC: Jason Ekstrand
> ---
> src/compiler/nir/nir_opt_if.c | 21 +++--
> 1 file changed, 19 insertions(+), 2 deletions(-)
Reviewed-by: Caio Marcelo de Oliveira Filho
> dif
---
src/compiler/nir/nir_opt_if.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index 9afb901be14..170caaad89d 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -96,7 +96,7 @@
Reviewed-by: Caio Marcelo de Oliveira Filho
On Wed, Feb 13, 2019 at 03:03:59PM -0800, Ian Romanick wrote:
> From: Ian Romanick
>
> Fixes: c6465fec0c5 ("spirv: add SpvCapabilityInt64Atomics")
> CID: 1442555
> ---
> src/compiler/spirv/spirv_to_nir.c | 1 +
&g
nsertions(+), 2 deletions(-)
Reviewed-by: Caio Marcelo de Oliveira Filho
There's a single case in
src/compiler/spirv/vtn_variables.c:^vtn_access_link_as_ssa
that does a check for != 1 before multiply. Maybe remove it too?
> diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/ni
On Sat, Mar 16, 2019 at 09:28:48AM +0800, Qiang Yu wrote:
> This is for the case that user only know a max size
> it wants to append to the array and enlarge the array
> capacity before writing into it.
>
> Signed-off-by: Qiang Yu
> ---
> src/util/u_dynarray.h | 19 +++
> 1 file
---
src/compiler/spirv/spirv.h | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/src/compiler/spirv/spirv.h b/src/compiler/spirv/spirv.h
index 61559a1c9c..233dc6d691 100644
--- a/src/compiler/spirv/spirv.h
+++ b/src/compiler/spirv/spirv.h
@@ -1,5 +1,5
Reviewed-by: Caio Marcelo de Oliveira Filho
On Tue, Jun 12, 2018 at 03:48:13PM -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> Since SSBOs can be written, copy propagating a read can cause the
Optional: maybe write "... can be written by other threads"?
> value to m
Reviewed-by: Caio Marcelo de Oliveira Filho
On Tue, Jun 12, 2018 at 03:48:14PM -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> Since SSBOs can be written, copy propagating a read can cause the
> value to magically change. SSBO reads are also very expensive, so
> doing i
---
src/util/set.c | 23 +++
src/util/set.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/src/util/set.c b/src/util/set.c
index 2c9b09319ff..b2aa5ba13d5 100644
--- a/src/util/set.c
+++ b/src/util/set.c
@@ -34,6 +34,7 @@
#include
#include
+#include
#include
When handling 'if' in copy propagation elements, if a certain variable
was killed when processing the first branch of the 'if', then the
second would get any propagation from previous nodes.
x = y;
if (...) {
z = x; // This would turn into z = y.
x = 22; // x gets killed.
When handling 'if' in constant propagation, if a certain variable was
killed when processing the first branch of the 'if', then the second
would get any propagation from previous nodes. This is similar to the
change done for copy propagation code.
x = 1;
if (...) {
z = x; // This
When handling 'if' in copy propagation, if a certain variable was
killed when processing the first branch of the 'if', then the second
would get any propagation from previous nodes.
x = y;
if (...) {
z = x; // This would turn into z = y.
x = 22; // x gets killed.
} els
Separate higher level logic of visiting instructions and chosing when
to store and use new copy data from the datastructure holding the copy
propagation information. This will also make easier later patches that
change the structure.
---
.../glsl/opt_copy_propagation_elements.cpp| 269
't care much about performance. There are some low hanging
fruits but I'll invest only if there's interest.
Because NIR passes pick up most of the slack, another reasonable
approach could be just stick some comments in the GLSL passes about
the "if/else" case. So I don&#x
---
src/util/set.c | 9 +
src/util/set.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/src/util/set.c b/src/util/set.c
index b2aa5ba13d5..feef96d16ea 100644
--- a/src/util/set.c
+++ b/src/util/set.c
@@ -383,6 +383,15 @@ _mesa_set_remove(struct set *ht, struct set_entry *entry)
Instead of keeping multiple acp_entries in lists, have a single
acp_entry per variable. With this, the implementation of clone is more
convenient and now fully implemented. In the previous code, clone was
only partial.
Before this patch, each acp_entry struct represented a write to a
variable incl
Keep information in acp_entry whether the entry is full or not, and
use the ACP in more nodes when visiting the instructions:
- add_copy: write whole variables to the ACP state (regardless the
type).
- visit(ir_dereference_variable *): perform the propagation here if we have a
full candidate.
When handling loops in constant propagation, implement the "FINISHME"
comment like copy propagation: perform a first pass to find values
that can't be propagated, then perform a second pass with the ACP
containing still valid values.
Certain values are killed because the loop may run more than one
Now that the elements version handles both cases, remove the
non-elements version.
---
src/compiler/Makefile.sources | 1 -
src/compiler/glsl/glsl_parser_extras.cpp | 1 -
src/compiler/glsl/ir_optimization.h| 1 -
src/compiler/glsl/meson.build | 1 -
src
Reviewed-by: Caio Marcelo de Oliveira Filho
On Wed, Jun 27, 2018 at 09:46:14PM -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> src/intel/compiler/brw_nir.c: In function ‘brw_nir_lower_vue_outputs’:
> src/intel/compiler/brw_nir.c:464:32: warning: unused parameter ‘is_scalar’
Patch looks good to me, consider suggestion in the end of the email.
Reviewed-by: Caio Marcelo de Oliveira Filho
A related question: for the case "if (inst->opcode == BRW_OPCODE_CMP
&& !inst->src[1].is_zero())" don't we need to break if we find an ADD
that is
Hi,
> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> index 67c062d91f5..6a0d4090fa7 100644
> --- a/src/intel/compiler/brw_nir.c
> +++ b/src/intel/compiler/brw_nir.c
> @@ -557,7 +557,22 @@ brw_nir_optimize(nir_shader *nir, const struct
> brw_compiler *compiler,
>
Hi,
On Wed, Jun 27, 2018 at 09:46:24PM -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> This pass attempts to dectect code sequences like
>
> if (x < y) {
> z = y - z;
Typo "z = x - y".
> Currently only floating point compares and adds are supported. Adding
> support for int
Hi,
> > The hurt instruction count is caused because the extra propagation
> > causes an input variable to be read from two branches of an
> > if (load_input intrinsic in NIR). Depending on the complexity of each
> > branch this might be a win or not in terms of cycles.
>
> I just sent out a patc
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index b279f01e1a1..921b420ab81 100644
--- a/src/mesa/drivers/dri/i965/genX_state_uplo
> diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
> b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
> index 9a5eec8f870..7753f85824d 100644
> --- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
> +++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
> @@ -194,12 +194,1
> diff --git a/src/intel/Makefile.tools.am b/src/intel/Makefile.tools.am
> index b00cc8cc2cb..4f2027cdfd6 100644
> --- a/src/intel/Makefile.tools.am
> +++ b/src/intel/Makefile.tools.am
> @@ -27,6 +27,8 @@ tools_aubinator_SOURCES = \
> tools/aubinator.c \
> tools/intel_aub.h
>
> +nodis
Patches 1-3 are
Reviewed-by: Caio Marcelo de Oliveira Filho
But consider comment below.
> @@ -1430,6 +1431,18 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
> anv_subpass_view_count(pipeline->subpass);
> }
>
> + const VkPipelineVertexInputDivisor
> > @@ -1430,6 +1431,18 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
> > anv_subpass_view_count(pipeline->subpass);
> > }
> >
> > + const VkPipelineVertexInputDivisorStateCreateInfoEXT *vi_div_state =
> > + vk_find_struct_const(pCreateInfo->pNext,
> > +
> >> +nodist_EXTRA_tools_aubinator_SOURCES = dummy.cpp
> >> +
> >> tools_aubinator_CFLAGS = \
> >>$(AM_CFLAGS) \
> >>$(ZLIB_CFLAGS)
> >> @@ -47,6 +49,8 @@ tools_aubinator_LDADD = \
> >> tools_aubinator_error_decode_SOURCES = \
> >>tools/aubinator_error_decode.c
> >>
> >> +nodist_EXT
> How about this version?
> https://gitlab.freedesktop.org/jekstrand/mesa/commits/wip/VK_EXT_vertex_attribute_divisor
>
> I've changed it to first grab the vertex divisors from the struct and then
> the multiview handling is a *=. This moves it to more of a "set a bunch of
> stuff then compile" m
Reviewed-by: Caio Marcelo de Oliveira Filho
Also consider including a fixes tag.
Fixes: 6f5abf31466 "i965: Fix output register sizes when multiple variables
share a slot."
On Fri, May 18, 2018 at 03:31:00PM +0200, Neil Roberts wrote:
> In 6f5abf31466aed this code was fixed to
> +/**
> + * Check that the register region given by r [r.offset, r.offset + dr[
> + * is exactly the same as the the register region given by s
> + * [s.offset, s.offset + ds[
> + */
> +static inline bool
> +region_match(const fs_reg &r, unsigned dr, const fs_reg &s, unsigned ds)
> +{
> + return
Hi,
> + /* Look for any follow-up instructions that sources from the boolean
> +* result of the producer instruction and rewrite them to use the correct
> +* bit-size.
> +*/
> + foreach_inst_in_block_starting_from(fs_inst, fixup_inst, inst) {
> + if (!inst_supports_boolean(fi
Reviewed-by: Iago Toral Quiroga
---
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_pipeline.c| 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index d0b70a0405..b5bee0881c 100644
--- a/src/intel/vulka
Remove the need of converting values that are documented in
hexadecimal. This patch would allow writing
instead of
---
src/intel/genxml/gen_pack_header.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/intel/genxml/gen_pack_header.py
b/src/intel/genxml/gen_
Series is
Reviewed-by: Caio Marcelo de Oliveira Filho
On Mon, May 07, 2018 at 01:40:44PM -0700, Kenneth Graunke wrote:
> Python's assert can take both a condition and a string, which will cause
> it to print the string if the assertion trips. (You can't use parens as
> t
Reviewed-by: Caio Marcelo de Oliveira Filho
On Wed, May 09, 2018 at 04:40:37PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.")
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 1 -
&g
From: Gustavo Lima Chaves
v2:
An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
also follows, with the interpretation to said mode being we prevent
writes to the built-in FragStencilRefEXT variable when the execution
mode isn't set.
v3:
A more cautious reading of 1db44252d0
From: Gustavo Lima Chaves
Reviewed-by: Jason Ekstrand
Reviewed-by: Iago Toral Quiroga
---
This is the original patch from Gustavo Lima Chaves rebased and
with the added R-b's.
src/compiler/shader_info.h | 1 +
src/compiler/spirv/spirv_to_nir.c | 4
src/compiler/spirv/vtn_variab
On Fri, May 11, 2018 at 03:31:31PM -0400, Ilia Mirkin wrote:
> > diff --git a/src/intel/vulkan/anv_pipeline.c
> > b/src/intel/vulkan/anv_pipeline.c
> > index 8f30136b100..c37b9b96e11 100644
> > --- a/src/intel/vulkan/anv_pipeline.c
> > +++ b/src/intel/vulkan/anv_pipeline.c
> > @@ -152,6 +152,7 @@
> > [please wait for someone who knows what they're doing to actually
> > review before sending a new version]
>
> Sorry, I wanted to have some recent on the list for folks doing CTS
> review to apply. I will avoid this in the future.
After a second read, I probably misunderstood what you meant t
From: Gustavo Lima Chaves
---
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_pipeline.c| 1 +
src/intel/vulkan/genX_pipeline.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index b5bee0881ce..8
From: Gustavo Lima Chaves
v2:
An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
also follows, with the interpretation to said mode being we prevent
writes to the built-in FragStencilRefEXT variable when the execution
mode isn't set.
v3:
A more cautious reading of 1db44252d0
From: Gustavo Lima Chaves
v2:
An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
also follows, with the interpretation to said mode being we prevent
writes to the built-in FragStencilRefEXT variable when the execution
mode isn't set.
v3:
A more cautious reading of 1db44252d0
From: Gustavo Lima Chaves
---
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_pipeline.c| 1 +
src/intel/vulkan/genX_pipeline.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index b5bee0881ce..8
On Thu, Aug 16, 2018 at 04:00:16PM +0100, Eric Engestrom wrote:
> These are all already assigned when declared, a few lines above.
>
> Signed-off-by: Eric Engestrom
> ---
> Note: I'm not 100% certain the value can never change by the time this
> second assignment is done, so maybe it's the initia
On Thu, Aug 16, 2018 at 07:29:40AM +0200, Thomas Helland wrote:
> 2018-08-15 23:56 GMT+02:00 Caio Marcelo de Oliveira Filho
> :
> > ---
> > src/util/u_dynarray.h | 9 +
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/src/util/u_dynarray
Hello,
> +(add a new row after the exiting "atomicMax" table row, p. 179)
> +
> +float atomicMax(inout float mem, float data)
> +
> +Computes a new value by taking the maximum of the value of data and
> + the contents of mem. If one of these is an IEEE signaling NaN (i.e.,
deletions(-)
Regardless of the suggestion above, this patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
You've fixed the warnings in "generate_*" functions in another patch
that landed. I guess this commit also fixed and the rebase was clean,
but the commit message remained.
With that update to the commit message, this patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
On Fr
This patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
On Fri, Jun 22, 2018 at 10:03:57PM -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> This is a strictly alphabetic sort, as is done in extensions_table.h
> There are other options. We should pick one and document it.
On Fri, Jun 22, 2018 at 10:03:54PM -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> Signed-off-by: Ian Romanick
> ---
> src/compiler/glsl/glsl_to_nir.cpp| 32
> ++--
> src/compiler/nir/nir_intrinsics.py | 11 +-
> src/compiler/nir/nir_lo
Hi,
> @@ -1133,6 +1159,9 @@ builtin_builder::create_intrinsics()
> _atomic_intrinsic2(buffer_atomics_supported,
> glsl_type::int_type,
> ir_intrinsic_generic_atomic_add),
> +_atomic_intrinsic2(
> The code is here:
>
>
> https://cgit.freedesktop.org/~idr/mesa/log/?h=INTEL_shader_atomic_float_minmax
The series is
Reviewed-by: Caio Marcelo de Oliveira Filho
I'd consider adding some clarification about not quietizing sNaN
and/or relaxing the definition in
> > Question: why some builtins care about "supported" while other care
> > about the extension being "enabled"?
>
> There are actually two different things happening. In the cases where
> we only care about the extension being supported, we're creating a
> hidden intrinsic function. These are u
/compiler/nir/nir.h| 1 +
> src/compiler/nir/nir_split_vars.c | 271 ++
> 4 files changed, 274 insertions(+)
> create mode 100644 src/compiler/nir/nir_split_vars.c
With the fix below, this patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
>
:
> - Fix a couple of bugs that were added in the rework including one
>which basically prevented it from running
> ---
> src/compiler/nir/nir.h| 1 +
> src/compiler/nir/nir_split_vars.c | 583 ++
> 2 files changed, 584 insert
to be
> lowered to SSA values is fairly advanced.
> ---
> src/intel/compiler/brw_nir.c | 2 ++
> 1 file changed, 2 insertions(+)
This patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> index 5990427b731..
Hi,
On Sat, Jul 28, 2018 at 10:44:39PM -0700, Jason Ekstrand wrote:
> This pass looks for variables with vector or array-of-vector types and
> narrows the type to only the components used.
> ---
> src/compiler/nir/nir.h| 1 +
> src/compiler/nir/nir_split_vars.c | 694 +++
> diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> index 96ad77c3906..5e9da9e1ef2 100644
> --- a/src/intel/compiler/brw_nir.c
> +++ b/src/intel/compiler/brw_nir.c
> @@ -542,6 +542,7 @@ brw_nir_optimize(nir_shader *nir, const struct
> brw_compiler *compiler,
> do {
>
a few minor comments and a comment about store write mask.
Assuming those are resolved this patch is:
Reviewed-by: Caio Marcelo de Oliveira Filho
Note: the "deref_map" (well, an evolution of it) from the dead write
elimination series, could be used to keep track of multiple of such
copies
On Tue, Aug 21, 2018 at 06:15:20PM -0500, Jason Ekstrand wrote:
> On Tue, Aug 21, 2018 at 5:55 PM Caio Marcelo de Oliveira Filho <
> caio.olive...@intel.com> wrote:
>
> > Hi,
> >
> > On Sat, Jul 28, 2018 at 10:44:39PM -0700, Jason Ekstrand wrote:
> > > Th
> I've applied your suggestions. Please double-check:
>
> https://gitlab.freedesktop.org/jekstrand/mesa/commit/28c01e9a0ce84ff53fa8805e4a35a691ea3fc744
Reviewed-by: Caio Marcelo de Oliveira Filho
___
mesa-dev mailing
On Mon, Jul 09, 2018 at 05:11:54PM -0700, Jason Ekstrand wrote:
> ---
> src/compiler/nir/nir_lower_vars_to_ssa.c | 18 ++
> 1 file changed, 14 insertions(+), 4 deletions(-)
This patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
I also verified it pass the test
ninitialised memory.
>
> While at it, drop the unused assignment right before returning.
>
> Signed-off-by: Eric Engestrom
> ---
> src/vulkan/wsi/wsi_common_x11.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-b
reads instead of making a copy of 4.5 KiB of input data
> and then indirecting on it with if-ladders.
> ---
> src/intel/compiler/brw_nir.c | 16 +---
> src/intel/compiler/brw_nir.h | 3 ++-
> 2 files changed, 11 insertions(+), 8 deletions(-)
Given the comment mentioned below i
it_vars.c | 694 ++
> 2 files changed, 695 insertions(+)
This patch and the one that enables the pass are
Reviewed-by: Caio Marcelo de Oliveira Filho
I have some suggestions below, pick the ones you like.
(...)
> +static void
> +mark_deref_use
Ian Romanick writes:
> I don't know why we never did this. Almost every shader in shader-db
> that uses atomicAdd or imageAtomicAdd uses it with a constant of 1 or
> -1.
Nice. The series is
Reviewed-by: Caio Marcelo de Oliveira Filho
Jason Ekstrand writes:
> On Sat, Aug 25, 2018 at 9:40 AM Jason Ekstrand wrote:
>
>> Sorry I haven't given you any in-line review yet. I've been letting this
>> pass simmer in my brain a bit and thinking about complexity and data
>> structures. Here's a few questions for which I do not expect y
Jason Ekstrand writes:
> On Wed, Aug 15, 2018 at 4:57 PM Caio Marcelo de Oliveira Filho <
> caio.olive...@intel.com> wrote:
>
>> Instead of doing this as part of the existing (local) copy prop vars
>> pass. This is an intermediate step before changing both the dead
(Disregard the incomplete mail, still adapting to notmuch-emacs).
Jason Ekstrand writes:
>> +static nir_deref_path *
>> +get_path(struct state *state, nir_deref_instr *deref)
>> +{
>> + struct hash_entry *entry = _mesa_hash_table_search(state->paths,
>> deref);
>> + if (!entry) {
>> + n
---
The move of comapre functions landed before the suggestion to remove
the comment, so removing it now.
src/compiler/nir/nir_deref.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/compiler/nir/nir_deref.c b/src/compiler/nir/nir_deref.c
index c8851688f9d..097ea8f1046 100644
--- a/src
Jason Ekstrand writes:
>> >> +static bool
>> >> +remove_dead_write_vars_local(struct state *state, nir_block *block)
>> >> +{
>> >> + bool progress = false;
>> >> +
>> >> + struct util_dynarray unused_writes;
>> >> + util_dynarray_init(&unused_writes, state->mem_ctx);
>> >> +
>> >> + nir_
_bug.cgi?id=107745
> Fixes: 37f7983bcca1 "intel/compiler: Do image load/store lowering..."
> ---
> src/intel/compiler/brw_nir_lower_image_load_store.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Caio Marcelo de Oliveira Filho
These combinations are common enough and deserve a shortcut.
---
src/util/hash_table.c | 10 ++
src/util/hash_table.h | 3 +++
src/util/set.c| 12
src/util/set.h| 3 +++
4 files changed, 28 insertions(+)
diff --git a/src/util/hash_table.c b/src/util/hash_tab
Calls are not used yet (functions are inlined), but since new code is
already taking them into account, do it here too. The convention here
and in other places is that no writable memory is assumed to remain
unchanged, as well as global variables.
Also, explicitly state the modes affected (instea
---
I've ended up not using this macro in this series, but it is useful
for other cases, so kept it here.
src/util/u_dynarray.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
index f74bfc7080b..53dde9241bb 100644
--- a/src/util/u_dynarray.h
+++
Note at the moment the pass called is nir_opt_copy_prop_vars, because
dead write elimination is implemented there.
Also added tests that involve identifying dead writes in multiple
blocks (e.g. the overwrite happens in another block). Those currently
fail as expected, so are marked to be skipped.
Add basic helpers for doing tests on the vars related optimization
passes. The main goal is to lower the barrier to create tests during
development and debugging of the passes. Full coverage is not a
requirement.
---
src/compiler/Makefile.nir.am | 34 +++--
src/compiler/nir/meson.build
the copies, or only the fully qualified load/stores, or handle
only scalars (after a vec to scalar pass).
For now, I've shelved the global optimization for dead write removal.
It wasn't helping any cases, so will wait until we have more derefs
around to see the difference.
Caio Marcelo
Useful to walk the array removing elements by swapping them with the
last element.
---
src/util/u_dynarray.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
index 6bea481d44b..f74bfc7080b 100644
--- a/src/util/u_dynarray.h
+++ b/src/util/u_dy
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