Re: [Mesa-dev] [PATCH 3/3] i965: Apply a homebrew workaround for GPU hang in OGLC api-texcoord.

2011-07-19 Thread Chris Wilson
hangs in OGLC and the engine demo. Whilst you are deep in flushing territory, do you know of any similar rules regarding 3DSTATE_CC_STATE_POINTERS? rendercheck demands a NP or flush before the blend mode is changed. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] X/Graphics DevRoom at FOSDEM 2012? (4-5 February)

2011-09-20 Thread Chris Wilson
us a thing or two about the DRM infrastructure and what it might look like in a year or two as more SoC gradually become mainline? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http

[Mesa-dev] [PATCH 1/2] dri: Support depth-15 Visuals

2013-03-04 Thread Chris Wilson
Note: This is a candidate for the stable branches. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/common/utils.c |5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/drivers/dri/common/utils.c b/src/mesa/drivers/dri/common/utils.c index ac0773b

[Mesa-dev] [PATCH 2/2] intel: Support depth-15 Visuals

2013-03-04 Thread Chris Wilson
Note: This is a candidate for the stable branches. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/intel/intel_screen.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers

Re: [Mesa-dev] [PATCH] winsys/sw/xlib: Prevent shared memory segment leakage.

2013-04-24 Thread Chris Wilson
are attached). This is only true on Linux. The *BSD perform an immediate release and so require you to complete the XShmAttach prior to calling IPC_RMID. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev

Re: [Mesa-dev] renaming i965g

2013-04-26 Thread Chris Wilson
Option DRI ilo EndSection to use your new driver without having to rename existing dri.so. Hope that helps, -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http

Re: [Mesa-dev] [PATCH] i965: Fix GPU hangs when a blorp batch is the first thing to execute.

2013-05-02 Thread Chris Wilson
to this is that DynamicStateUpperBound is programmed to an unsafe value and should be (0x7fff | 1) for most of our hardware. The actual value to program requires information not easily reported by the kernel (just like the mappable aperture size). -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] [PATCH] i965: Fix GPU hangs when a blorp batch is the first thing to execute.

2013-05-02 Thread Chris Wilson
the end of the GTT - and so prevented by programming the upper bound to the end of the GTT. Those with access to the simulator can hopefully verify this, and perhaps we should add this to the set of known bad commands in igt. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] [PATCH] i965: Fix GPU hangs when a blorp batch is the first thing to execute.

2013-05-02 Thread Chris Wilson
On Thu, May 02, 2013 at 09:07:08AM -0700, Eric Anholt wrote: Chris Wilson ch...@chris-wilson.co.uk writes: On Thu, May 02, 2013 at 07:26:06AM -0700, Paul Berry wrote: Can you provide a documentation reference for why the value we're currently programming (0xf001) is unsafe

Re: [Mesa-dev] [PATCH 2/2] i965/hsw: Set MOCS to L3_CACHEABLE for some packets

2013-07-17 Thread Chris Wilson
rendering)? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 3/5] i965/hsw: Change L3 MOCS of SURFACE_STATE

2013-07-19 Thread Chris Wilson
On Fri, Jul 19, 2013 at 10:19:12AM -0700, Chad Versace wrote: On 07/19/2013 09:58 AM, Daniel Vetter wrote: On Fri, Jul 19, 2013 at 02:03:31PM +0100, Chris Wilson wrote: On Thu, Jul 18, 2013 at 03:00:59PM -0700, Chad Versace wrote: Change from not cacheable to cacheable in L3. Do so

[Mesa-dev] [PATCH] dri2: Remove the extra roundtrip during SwapBuffers

2013-08-11 Thread Chris Wilson
protocol with XCB. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Marek Olšák mar...@gmail.com Cc: Eric Anholt e...@anholt.net --- src/glx/dri2_glx.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c index c54edac..899bb1f 100644 --- a/src/glx

Re: [Mesa-dev] [PATCH] dri2: Remove the extra roundtrip during SwapBuffers

2013-08-11 Thread Chris Wilson
On Sun, Aug 11, 2013 at 08:42:45PM +0200, Eric Anholt wrote: Chris Wilson ch...@chris-wilson.co.uk writes: Currently we call XSync() to run the event queue to catch the invalidate event before we wait for the reply from the DRI2SwapBuffers request. However, the XServer sends

Re: [Mesa-dev] dri broken on i915

2012-06-26 Thread Chris Wilson
On Tue, 26 Jun 2012 09:12:10 +0200, Knut Petersen knut_peter...@t-online.de wrote: @ Chris: mieq* problems are back, see log. During connector probing. Unusual, I can blame Eugeni since he touched it last :) -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] [PATCH 01/15] intel: Remove dead code in intelAllocateBuffer

2012-07-21 Thread Chris Wilson
be advantageous in many circumstances, basically any surface which is not a candidate for pageflipping? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman

Re: [Mesa-dev] [PATCH 2/2] intel: Reserve enough space to finish occlusion queries on Gen6.

2012-08-10 Thread Chris Wilson
in comparison to fixing the bug, so Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 12/13] i915g: implement unfenced colordepth buffer using tiling bits

2010-11-21 Thread Chris Wilson
(uint32_t tiling) { uint32_t v = 0; switch (tiling) { case I915_TILING_Y: v |= BUF_3D_TILE_WALK_Y; case I915_TILING_X: v |= BUF_3D_TILED_SURFACE; case I915_TILING_NONE: break; } return v; } -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] [PATCH] glx/dri2: use GLX prefix to enable INTEL_swap_event

2012-02-08 Thread Chris Wilson
noticed before since GLX_INTEL_swap_event was being implicitly enabled for GLX v1.4 but that was changed in commit d3f7597bc9f6d5 Signed-off-by: Robert Bragg rob...@sixbynine.org This sounds related to https://bugs.freedesktop.org/show_bug.cgi?id=43667 -Chris -- Chris Wilson, Intel Open

Re: [Mesa-dev] [PATCH] Use signbit() in IS_NEGATIVE and DIFFERENT_SIGNS

2012-09-18 Thread Chris Wilson
looked like it should cause any problems. The cause of the second regression is fairly simple (unsigned char)(131) == 0. The fi_type is also ill-defined where sizeof(GLint) != sizef(float). -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] [PATCH 1/1] intel: corrected the header include path for recent Valgrind versions.

2012-10-22 Thread Chris Wilson
On Mon, 22 Oct 2012 15:00:20 +0300, Oliver McFadden oliver.mcfad...@linux.intel.com wrote: intel_bufmgr_gem.c:67:22: fatal error: valgrind.h: No such file or directory Should be setup by `pkg-config --clfags valgrind` to point into the right valgrind header directory. -Chris -- Chris Wilson

Re: [Mesa-dev] Mesa (master): mesa: reduce calls to _mesa_test_framebuffer_completeness()

2011-03-01 Thread Chris Wilson
in lightsmark (with the i965 driver at least) - entire frames are rendered black. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] Sandy Bridge heisenbug

2011-03-31 Thread Chris Wilson
://bugs.freedesktop.org/show_bug.cgi?id=35820 perhaps? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] Sandy Bridge heisenbug

2011-03-31 Thread Chris Wilson
On Thu, 31 Mar 2011 15:01:53 -0500, Ian Pilcher arequip...@gmail.com wrote: On 03/31/2011 02:53 PM, Chris Wilson wrote: https://bugs.freedesktop.org/show_bug.cgi?id=35820 perhaps? I don't think so. My system doesn't hang, and I don't get any X crash, just messages in the syslog (see below

Re: [Mesa-dev] Sandy Bridge heisenbug

2011-03-31 Thread Chris Wilson
clue as to where to look next. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] Sandy Bridge heisenbug

2011-04-01 Thread Chris Wilson
On Thu, 31 Mar 2011 17:54:48 -0500, Ian Pilcher arequip...@gmail.com wrote: On 03/31/2011 05:20 PM, Chris Wilson wrote: However, if you are reasonably confident that a change in mesa provokes the issue, you can bisect the commit in question. That may give another clue as to where to look

Re: [Mesa-dev] [PATCH 2/2] i965: Allocate the whole URB to the VS and clarify calculations.

2011-04-07 Thread Chris Wilson
. For safety's sake, do this as two patches. And thanks for the docs! Long have I stared at each variable, and been thinking how many 128-bit regs is, how many 256-bit urbe, how many 512-bit datums? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa

Re: [Mesa-dev] [PATCH 0/10] i965: Implement hiz and separate stencil for window framebuffer

2011-06-05 Thread Chris Wilson
I have a naive question: why are we allocating stencil/depth/aux buffers through X/DRI2? I can understand for the sake of interoperability why the color buffer attachments are negotiated with X, but I can't see any reason why X wants to know about the others. -Chris -- Chris Wilson, Intel Open

Re: [Mesa-dev] leak of gem_objects on intel i965

2011-06-14 Thread Chris Wilson
. That sounds like a simple test case to concoct. Do you have one handy? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] leak of gem_objects on intel i965

2011-06-14 Thread Chris Wilson
that they have not all been backported to 2.6.33 -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] leak of gem_objects on intel i965

2011-06-14 Thread Chris Wilson
drm_gem_vm_close() has the unref but not the close, which is a different type of leak. If the leak still occurs with 2.6.39, it is definitely in userspace. ;-) -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev

Re: [Mesa-dev] [PATCH 3/3] intel: Add support copying Y-tiled buffers with the Gen6 blitter.

2011-06-30 Thread Chris Wilson
. To support Y-tiling, afaics, in the SNB blitter, you have to set a register that forces it to treat all source and/or destination surface as y-tiled: BCS_SWCTRL 0x22200 Fortunately they did permit use to modify it with MI_LOAD_REGISTER_IMM. -Chris -- Chris Wilson, Intel Open Source Technology

Re: [Mesa-dev] [PATCH 04/10] i965: setup system routine

2011-07-13 Thread Chris Wilson
(); + /* The system routine must be set after a change to Instruction base */ + if (brw-wm.debugging) { + assert(brw-wm.sip_offset != 0); + /* assert instruction base == 0 */ Kill or correct the misleading comment. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] [PATCH 5/7] intel: Remove silly check for !bufmgr.

2013-09-27 Thread Chris Wilson
On Thu, Sep 26, 2013 at 08:36:00PM -0700, Eric Anholt wrote: If bufmgr didn't get created, then screen creation failed, and we never should have got here in the first place. This was added by Chris Wilson in 2010 with no explanation for why it would be needed. Because it prevented a segfault

[Mesa-dev] [PATCH] glx: Report the current refresh rate for GetMscRateOML

2014-05-16 Thread Chris Wilson
that as the basis for the refresh rate calculation. We fallback to the current XVidMode method if XRandR is not available. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: TheoH theo0...@gmail.com Cc: Jamey Sharp ja...@minilop.net --- configure.ac| 7 +++ src/glx/Makefile.am | 8

Re: [Mesa-dev] [PATCH] glx/dri3: request async pixmap present for swap interval 0

2014-05-30 Thread Chris Wilson
to do an asynchronise swap when the swap interval is 0. Signed-off-by: Frank Binns frank.bi...@imgtec.com Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev

Re: [Mesa-dev] [Intel-gfx] [PATCH 00/68] Broadwell 48b addressing and prelocations (no relocs)

2014-08-22 Thread Chris Wilson
-- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [Intel-gfx] [PATCH 00/68] Broadwell 48b addressing and prelocations (no relocs)

2014-08-22 Thread Chris Wilson
On Thu, Aug 21, 2014 at 11:59:04PM -0700, Kenneth Graunke wrote: On Friday, August 22, 2014 07:30:37 AM Chris Wilson wrote: On Thu, Aug 21, 2014 at 08:11:23PM -0700, Ben Widawsky wrote: The primary goal of these patches is to introduce what I've started calling, prelocations on Broadwell

Re: [Mesa-dev] [Intel-gfx] [PATCH 00/68] Broadwell 48b addressing and prelocations (no relocs)

2014-08-22 Thread Chris Wilson
On Fri, Aug 22, 2014 at 03:30:12PM +0200, Daniel Vetter wrote: On Fri, Aug 22, 2014 at 9:03 AM, Chris Wilson ch...@chris-wilson.co.uk wrote: If a GPU client uses only prelocations, the relocation process can be entirely skipped. This sounds like a big win initially, Close

Re: [Mesa-dev] [PATCH 3/4] i965: Issue performance warnings for program cache related stalls.

2014-09-26 Thread Chris Wilson
...@whitecape.org Reviewed-by: Kristian Høgsberg k...@bitplanet.net This warns if the the program cache is currently being read by the GPU (expected) but a read-read (as used here) does not incur a stall. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] [PATCH] i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.

2014-11-12 Thread Chris Wilson
) +{ + if (brw-gen == 7 brw-is_haswell) { The comment says for IVB,BYT, the code here only applies to HSW. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org

Re: [Mesa-dev] [xorg 3/3] dri2: Reuse unused flags in GetBuffers protocol to pass last SBC

2015-01-19 Thread Chris Wilson
On Mon, Jan 19, 2015 at 11:00:40AM +, Chris Wilson wrote: @@ -1104,6 +1107,8 @@ DRI2SwapBuffers(ClientPtr client, DrawablePtr pDraw, CARD64 target_msc, * it as early as possible, just to be sure. */ *swap_target = pPriv-swap_count + pPriv-swapsPending + 1; +if (ds

[Mesa-dev] [xf86-video-ati] dri2: Enable BufferAge support

2015-01-19 Thread Chris Wilson
perserving the flags when injecting the third buffer. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Dave Airlie airl...@redhat.com Cc: Jerome Glisse jgli...@redhat.com Cc: Alex Deucher alexander.deuc...@amd.com Cc: Michel Dänzer michel.daen...@amd.com --- src/radeon_dri2.c | 10 ++ 1

[Mesa-dev] [xorg 1/3] dri2: Allow GetBuffers to match any format

2015-01-19 Thread Chris Wilson
or caching of buffers (e.g. for triple buffering) void. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- hw/xfree86/dri2/dri2.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/xfree86/dri2/dri2.c b/hw/xfree86/dri2/dri2.c index 43a1899..f9f594d 100644 --- a/hw

[Mesa-dev] [dri2proto] Declare DRI2ParamXHasBufferAge

2015-01-19 Thread Chris Wilson
In order for X/DDX to reuse a driver specific field of the DRI2GetBuffers reply, we need to declare the change in semantics. To indicate that the flags field now continues the last swap buffers count instead, we introduce the has-buffer-age parameter. Signed-off-by: Chris Wilson ch...@chris

[Mesa-dev] [xf86-video-nouveau] dri2: Enable BufferAge support

2015-01-19 Thread Chris Wilson
about setting the copying the flags field when injecting the third buffer. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Maarten Lankhorst maarten.lankho...@ubuntu.com Cc: Mario Kleiner mario.kleiner...@gmail.com --- src/nouveau_dri2.c | 7 +++ 1 file changed, 7 insertions(+) diff

[Mesa-dev] [xorg 3/3] dri2: Reuse unused flags in GetBuffers protocol to pass last SBC

2015-01-19 Thread Chris Wilson
Allow mesa/dri2 to implement GLX_EXT_buffer_age by reporting the sbc of when the current back buffer was defined. As this may require ddx support, only set the value if enabled by the ddx and report the new semantics via a DRI2GetParam request. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk

[Mesa-dev] [mesa 9/9] glx/dri2: Implement getBufferAge

2015-01-19 Thread Chris Wilson
the query and the rendering where the buffer may be invalidated by the server. However, for the primary usecase (that of a compositing manager), the DRI2Drawable is only accessible to a single client mitigating the impact of the issue. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk

[Mesa-dev] Implement GLX_EXT_buffer_age for DRI2

2015-01-19 Thread Chris Wilson
In order to suport GLX_EXT_buffer_age in DRI2, we need to pass back the last swap buffer count that the back buffer was defined for. For simplicity, we can reuse an existing field in the DRI2GetBuffers reply that is not used by current drivers, the flags. Since we change the interpretation of this

[Mesa-dev] [mesa 7/9] glx/dri2: Add DRI2GetParam()

2015-01-19 Thread Chris Wilson
Available since the inclusion of dri2proto 1.4 is a DRI2 request to query and set certain parameters about the X/DDX configuration. This implements the getter request. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/glx/dri2.c | 29 + src/glx/dri2.h | 4

[Mesa-dev] [mesa 8/9] glx/dri2: Move the wait after SwapBuffers into the next GetBuffers

2015-01-19 Thread Chris Wilson
before querying properties. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/glx/dri2_glx.c | 73 -- 1 file changed, 38 insertions(+), 35 deletions(-) diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c index 462d560..0577804 100644

[Mesa-dev] [xorg 2/3] dri2: Pass swap-interval=0 ScheduleSwap requests to the ddx

2015-01-19 Thread Chris Wilson
/xorg-devel/2011-June/023102.html References: http://lists.x.org/archives/xorg-devel/2012-February/029336.html Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- hw/xfree86/dri2/dri2.c | 14 ++ hw/xfree86/dri2/dri2.h | 5 - 2 files changed, 14 insertions(+), 5 deletions

[Mesa-dev] [PATCH 1/2] i965: Throttle rendering to an fbo

2015-03-06 Thread Chris Wilson
intel_prepare_render() and switch non-fbo frontbuffer throttling over to use the same lax method. The issuing being that glFlush()/intel_prepare_read() is just as likely to be called inside a tight loop and not at frame boundaries. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Daniel

[Mesa-dev] [PATCH 1/2] i965: Throttle rendering to an fbo

2015-03-06 Thread Chris Wilson
intel_prepare_render() and switch non-fbo frontbuffer throttling over to use the same lax method. The issuing being that glFlush()/intel_prepare_read() is just as likely to be called inside a tight loop and not at frame boundaries. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Daniel

[Mesa-dev] [PATCH 2/2] i965: Throttle to the previous frame

2015-03-06 Thread Chris Wilson
of improving throughput and reducing jitter. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Kenneth Graunke kenn...@whitecape.org Cc: Ben Widawsky b...@bwidawsk.net Cc: Kristian Høgsberg k...@bitplanet.net Cc: Chad Versace chad.vers...@linux.intel.com

[Mesa-dev] [PATCH 1/2] i965: Throttle rendering to an fbo

2015-03-06 Thread Chris Wilson
any ambiguity between front buffer rendering and fbo rendering. (Chad) Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Kenneth Graunke kenn...@whitecape.org Cc: Ben Widawsky b...@bwidawsk.net Cc: Kristian Høgsberg k...@bitplanet.net Cc: Chad

[Mesa-dev] [PATCH 2/2] i965: Throttle to the previous frame

2015-03-06 Thread Chris Wilson
first_post_swapbuffer batches array to a plain throttle_batch[] as the pluralisation was contorting the name and not making it clear as to whether it was the first batch or first_post_swap batch. Not least of which was that not all throttle points are SwapBuffers. Signed-off-by: Chris Wilson ch...@chris

Re: [Mesa-dev] [PATCH] i965: Move need_throttle and first_post_swapbuffers_batch into the renderbuffer

2015-03-07 Thread Chris Wilson
often it is the same render target being used over and over again.. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] i965: Defer the throttle until we submit new commands

2015-03-11 Thread Chris Wilson
phase we can allow the user to improve concurrency between the CPU and GPU (i.e. reduce the amount of time we waste inside the throttle). Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Kenneth Graunke kenn...@whitecape.org Cc: Ben Widawsky b

Re: [Mesa-dev] [PATCH] i965: Throttle rendering to an fbo

2015-03-04 Thread Chris Wilson
On Wed, Mar 04, 2015 at 09:41:56AM -0800, Chad Versace wrote: On 02/26/2015 05:24 AM, Chris Wilson wrote: When rendering to an fbo, even though it may be acting as a winsys frontbuffer or just generally, we never throttle. However, when rendering to an fbo, there is no natural frame

Re: [Mesa-dev] [PATCH] i965: Throttle rendering to an fbo

2015-03-04 Thread Chris Wilson
On Wed, Mar 04, 2015 at 10:28:16AM -0800, Chad Versace wrote: On 03/04/2015 09:52 AM, Chris Wilson wrote: The manpage for glFlush says glFlush can return at any time. It does not wait until the execution of *all* previously issued GL commands is complete. Emphasis mine

[Mesa-dev] [PATCH] i965: Throttle rendering to an fbo

2015-02-26 Thread Chris Wilson
never to throttle, throttle after every draw call, or at an intermediate user defined point such as glFlush and thus all the implied flushes. This patch opts for the latter. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Kenneth Graunke kenn

Re: [Mesa-dev] [PATCH] i965: Throttle rendering to an fbo

2015-03-06 Thread Chris Wilson
peril. Will you please fix your code then. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] i965: Always use Y-tiled buffers on SKL+

2015-04-13 Thread Chris Wilson
of handshake with the compositor to make sure it understands this, presuming I didn't miss something. You can send Y-tiled buffers to the DDX. The problem is that the kernel won't allow us to display them and so we will (and always have been) copying from them. -Chris -- Chris Wilson, Intel Open Source

[Mesa-dev] RFC Fast batch and relocation handling for i965

2015-05-01 Thread Chris Wilson
Relocation processing is a significant overhead of heavy batches. The kernel tries to make this as cheap as possible by avoiding as much work as possible, but to be truly lazy requires userspace to construct its batches and relocation trees in a convenient manner for processing. Kristian made an

[Mesa-dev] [PATCH 3/4] i965: Move pipecontrol workaround bo to brw_pipe_control

2015-05-01 Thread Chris Wilson
With the exception of gen8, the sole user of the workaround bo are for emitting pipe controls. More it out of the purview of the batchbuffer and into the pipecontrol. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/brw_context.c | 7 + src/mesa

[Mesa-dev] [PATCH 1/4] i965: Transplant PIPE_CONTROL routines to brw_pipe_control

2015-05-01 Thread Chris Wilson
Start trimming the fat from intel_batchbuffer.c. First by moving the set of routines for emitting PIPE_CONTROLS (along with the lore concerning hardware workarounds) to a separate brw_pipe_control.c Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 2/4] i915: Rename intel_emit* to reflect their new location in brw_pipe_control

2015-05-01 Thread Chris Wilson
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 4 ++-- src/mesa/drivers/dri/i965/brw_clear.c | 4 ++-- src/mesa/drivers/dri/i965/brw_context.h | 6 +++--- src/mesa/drivers/dri/i965/brw_draw.c

[Mesa-dev] [PATCH 1/3] i965: Fix HW blitter pitch limits

2015-06-05 Thread Chris Wilson
The BLT pitch is specified in bytes for linear surfaces and in dwords for tiled surfaces. In both cases the programmable limit is 32,767, so adjust the check to compensate for the effect of tiling. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Kristian Høgsberg k...@bitplanet.net Cc

[Mesa-dev] [PATCH 2/3] i915: Blit RGBX-RGBA drawpixels

2015-06-05 Thread Chris Wilson
to the callers. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Jason Ekstrand ja...@jlekstrand.net Cc: Alexander Monakov amona...@gmail.com Cc: Kristian Høgsberg k...@bitplanet.net Cc: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/i965/intel_blit.c | 38

[Mesa-dev] [PATCH 3/3] i965: Export format comparison for blitting between miptrees

2015-06-05 Thread Chris Wilson
conversions. References: https://bugs.freedesktop.org/show_bug.cgi?id=90839 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Jason Ekstrand ja...@jlekstrand.net Cc: Alexander Monakov amona...@gmail.com Cc: Kristian Høgsberg k...@bitplanet.net Cc: Kenneth Graunke kenn...@whitecape.org

Re: [Mesa-dev] [PATCH 2/3] i915: Blit RGBX-RGBA drawpixels

2015-06-08 Thread Chris Wilson
On Sun, Jun 07, 2015 at 02:21:27AM -0700, Kenneth Graunke wrote: On Sunday, June 07, 2015 11:29:16 AM Alexander Monakov wrote: On Sun, Jun 7, 2015 at 11:06 AM, Kenneth Graunke kenn...@whitecape.org wrote: On Friday, June 05, 2015 03:14:30 PM Chris Wilson wrote: The blitter already has

Re: [Mesa-dev] [PATCH 1/3] i965: Fix HW blitter pitch limits

2015-06-05 Thread Chris Wilson
On Fri, Jun 05, 2015 at 11:26:29AM -0700, Ben Widawsky wrote: On Fri, Jun 05, 2015 at 03:14:29PM +0100, Chris Wilson wrote: The BLT pitch is specified in bytes for linear surfaces and in dwords for tiled surfaces. In both cases the programmable limit is 32,767, so adjust the check

Re: [Mesa-dev] [PATCH 2/3] i915: Blit RGBX-RGBA drawpixels

2015-06-06 Thread Chris Wilson
On Sat, Jun 06, 2015 at 12:58:05PM +0300, Alexander Monakov wrote: On Fri, Jun 5, 2015 at 5:14 PM, Chris Wilson ch...@chris-wilson.co.uk wrote: The blitter already has code to accommodate filling in the alpha channel for BGRX destination formats, so expand this to also allow filling

Re: [Mesa-dev] [PATCH 1/3] i965: Fix HW blitter pitch limits

2015-06-07 Thread Chris Wilson
On Sun, Jun 07, 2015 at 01:01:48AM -0700, Kenneth Graunke wrote: On Friday, June 05, 2015 03:14:29 PM Chris Wilson wrote: The BLT pitch is specified in bytes for linear surfaces and in dwords for tiled surfaces. In both cases the programmable limit is 32,767, so adjust the check

Re: [Mesa-dev] [PATCH 3/6] i965: Enable hardware-generated binding tables on render path.

2015-06-26 Thread Chris Wilson
+gen7_disable_hw_binding_tables(struct brw_context *brw) +{ + int pkt_len = brw-gen = 8 ? 4 : 3; How do you anticipate this function being used? As it looks like a if (!brw-resource_streamer_active) return; would make the function foolproof. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] [PATCH 5/6] i965: Upload binding tables in hw-generated binding table format.

2015-06-26 Thread Chris Wilson
the surfaces into their own state bo would cut down on the amount of RS traffic (you would not need to reload the binding table bo every batch, nor change the entries as often). Right? -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev

Re: [Mesa-dev] [PATCH 4/4] drisw/glx: use XShm if possible

2015-06-10 Thread Chris Wilson
keeping it as a ShmPixmap is hugely beneficial to UMA drivers. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v3 2/6] i965: Enable resource streamer for the batchbuffer

2015-06-16 Thread Chris Wilson
is. getparam.param = HAS_RESOURCE_STREAMER; getparam.value = val; val = -1; drmIoctl(psp-fd, DRM_IOCTL_I915_GETPARAM, getparam); intelScreen-has_resource_streamer = val 0; Hmm, now I need to double check the kernel patch for you GETPARAM. -Chris -- Chris Wilson, Intel Open Source Technology Centre

Re: [Mesa-dev] [Intel-gfx] [PATCH mesa v2] i965/gen8+: bo in state base address must be in 32-bit address range

2015-07-02 Thread Chris Wilson
it. Just my 2c because I have seen what trouble lying to the kernel about relocation values can cause and would rather not have that in the interface by design. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa

Re: [Mesa-dev] [Intel-gfx] [PATCH mesa v2] i965/gen8+: bo in state base address must be in 32-bit address range

2015-07-02 Thread Chris Wilson
be zero. You can adopt the libdrm interface Ben suggested underneath the macros, but having it marked as being both a 64-bit relocation and a w/a in the source is pricless imo. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing

[Mesa-dev] [PATCH 03/18] i965: Share the workaround bo between all contexts

2015-07-06 Thread Chris Wilson
for the first context - and baring synchronisation issues should not be a problem. Safer would be to move that also to the screen.) Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 6 +++--- src/mesa/drivers/dri/i965/intel_screen.c | 4

[Mesa-dev] [PATCH 09/18] i965: Enable GPU snooping of CPU caches for select buffers

2015-07-06 Thread Chris Wilson
On LLC, all buffers are normally cache coherent between the CPU and the GPU, giving both parties fast access to shared data. However, older architectures or Atoms, do not implement LLC between the CPU and GPU. Instead they utilise a snooping architecture where the GPU can snoop the CPU cache when

[Mesa-dev] [PATCH 07/18] i965: Make intel_mipmap_tree_map_raw() static

2015-07-06 Thread Chris Wilson
No external users, so no need to export the symbol outside of our compilation unit. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 +-- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 7 -- 2 files changed

[Mesa-dev] [PATCH 10/18] i965: Speculatively flush the batch after transform feedback

2015-07-06 Thread Chris Wilson
Since the purpose of transform feedback tends to be for the client to act upon the results to change the geometry in the scene, it is likely that the client will soon be waiting upon the results. Flush the batch early so that we don't build up a long queue of commands afterwards that could delay

[Mesa-dev] [PATCH 11/18] i965: Track active GPU region from MapBufferRange

2015-07-06 Thread Chris Wilson
Avoid unrequired synchronization if the user requests to map an unused range on active buffer, equivalent to BufferSubData. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/intel_buffer_objects.c | 78 +--- 1 file changed, 42 insertions

[Mesa-dev] [PATCH 05/18] i965: Reuse our VBO for streaming fast-clear vertices

2015-07-06 Thread Chris Wilson
Rather than allocating a fresh page every time we clear a buffer, keep that page around between invocations by tracking the last used offset and only allocating a fresh page when we wrap. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c

[Mesa-dev] [PATCH 08/18] i965: Coalesce relocation read/write domains to a single integer

2015-07-06 Thread Chris Wilson
. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/brw_batch.c | 11 src/mesa/drivers/dri/i965/brw_batch.h | 19 +++-- src/mesa/drivers/dri/i965/brw_cc.c | 2 +- src/mesa/drivers/dri/i965/brw_clip_state.c

[Mesa-dev] [PATCH 01/18] i965: Query whether we have kernel support for the TIMESTAMP register once

2015-07-06 Thread Chris Wilson
times and check the register is incrementing. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/intel_extensions.c | 6 +- src/mesa/drivers/dri/i965/intel_screen.c | 15 +++ src/mesa/drivers/dri/i965/intel_screen.h | 2 ++ 3 files changed

[Mesa-dev] [PATCH 02/18] i965: Move pipecontrol workaround bo to brw_pipe_control

2015-07-06 Thread Chris Wilson
With the exception of gen8, the sole user of the workaround bo are for emitting pipe controls. Move it out of the purview of the batchbuffer and into the pipecontrol. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/brw_context.c | 7 + src/mesa

[Mesa-dev] [PATCH 06/18] i965: Pass the map-mode along to intel_mipmap_tree_map_raw()

2015-07-06 Thread Chris Wilson
Since we can distinguish when mapping between READ and WRITE, we can pass along the map mode to avoid stalls and flushes where possible. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28 ++- src/mesa/drivers/dri

[Mesa-dev] [PATCH 12/18] i965: Reuse any available upload space for temporary MapBufferRange blits

2015-07-06 Thread Chris Wilson
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/intel_buffer_objects.c | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c index

[Mesa-dev] [PATCH 13/18] util/register_allocate: Combine the BITSET arrays into a single allocation

2015-07-06 Thread Chris Wilson
ralloc's ability to track all pointers belonging to a context and free them in a single call does not come cheap, and we can reduce the overhead here by combining the array of BITSETs for a regset into a single allocation. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Matt Turner matts

[Mesa-dev] i965: Context local batch manager, take 2

2015-07-06 Thread Chris Wilson
Since the last posting, it has grown a few superficial patches for tweaks in the general area and a couple of drive-bys from looking at the synmark profiles. As for the main patch, I've worked through the few piglit regressions and it should be clean on ivb/byt/hsw/bdw to the best of my knowledge,

[Mesa-dev] [PATCH 18/18] i965: AMD_pinned_memory and userptr

2015-07-06 Thread Chris Wilson
is suitable for any general usage (e.g. vertex data, texture data) and so only on LLC can we offer that extension. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/brw_batch.c| 36 + src/mesa/drivers/dri/i965/brw_batch.h

[Mesa-dev] [PATCH 14/18] util/register_allocate: Compute transitive conflicts using 2-passes

2015-07-06 Thread Chris Wilson
18351.5us to 4787.1us on my ivb i7-3720QM (in context that 18ms represents about 50% of the time it takes to start X, though why X instantiates an intel_screen at all remains a mystery). Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Matt Turner matts...@gmail.com Cc: Jason Ekstrand

[Mesa-dev] [PATCH 15/18] swrast: Defer _tnl_vertex_init until first use

2015-07-06 Thread Chris Wilson
The vertices require a large chunk of memory, currently allocated during context creation. However, this memory is not required until use so we can defer the allocation until the first swrast_Wakeup(). Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Kenneth Graunke kenn...@whitecape.org

[Mesa-dev] [PATCH 17/18] loader: Look for any version of currently linked libudev.so

2015-07-06 Thread Chris Wilson
the application for current linkage against all known versions first. Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/loader/loader.c | 46 -- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/src/loader/loader.c b/src/loader

[Mesa-dev] [PATCH 16/18] i965: Prevent coordinate overflow in intel_emit_linear_blit

2015-07-06 Thread Chris Wilson
line just in case it may exceed the coordinate limit. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90734 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk Cc: Kenneth Graunke kenn...@whitecape.org Cc: Ian Romanick ian.d.roman...@intel.com Cc: Anuj Phogat anuj.pho...@gmail.com Cc: mesa

Re: [Mesa-dev] [PATCH 01/18] i965: Query whether we have kernel support for the TIMESTAMP register once

2015-07-06 Thread Chris Wilson
On Mon, Jul 06, 2015 at 03:10:48PM +0300, Martin Peres wrote: On 06/07/15 13:33, Chris Wilson wrote: Move the query for the TIMESTAMP register from context init to the screen, so that it is only queried once for all contexts. On 32bit systems, some old kernels trigger a hw bug resulting

Re: [Mesa-dev] [PATCH v4 3/6] i965: Enable hardware-generated binding tables on render path.

2015-07-03 Thread Chris Wilson
running. Since the flush is mandatory, that implies to me that the state it changing is not latched and so still being used by those earlier commands. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-dev mailing list mesa-dev

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