On 13/02/18 17:57, srol...@vmware.com wrote:
From: Roland Scheidegger
Shaders coming from dx10 state trackers have a RET before the END.
And the epilog needs to be placed before the RET (otherwise it will
get ignored).
Hence figure out if a RET is in main, in this case
From: Roland Scheidegger
Shaders coming from dx10 state trackers have a RET before the END.
And the epilog needs to be placed before the RET (otherwise it will
get ignored).
Hence figure out if a RET is in main, in this case we'll place
the epilog there rather than before the
It looks good to me.
Though I think it would be useful to track nesting of subroutines and
other control flow separately, and throw a warning when we ignore RETs
on the main subroutine that are not on the top-most level of the control
flow stack. So it's easier to spot when that problem
LGTM.
Reviewed-by: Brian Paul
On 02/12/2018 09:10 PM, srol...@vmware.com wrote:
From: Roland Scheidegger
Shaders coming from dx10 state trackers have a RET before the END.
And the epilog needs to be placed before the RET (otherwise it will
get
From: Roland Scheidegger
Shaders coming from dx10 state trackers have a RET before the END.
And the epilog needs to be placed before the RET (otherwise it will
get ignored).
Hence figure out if a RET is in main, in this case we'll place
the epilog there rather than before the