subject:"\[Mesa\-dev\] \[PATCH 04\/12\] radeon\/vcn\: add ib implementations for HEVC"

[Mesa-dev] [PATCH 04/12] radeon/vcn: add ib implementations for HEVC

2018-02-02 Thread boyuan.zhang

From: Boyuan Zhang 

Implement required ibs for vcn HEVC encode.

Signed-off-by: Boyuan Zhang 
Acked-by: Christian König 
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 267 
 1 file changed, 222 insertions(+), 45 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 06b8092..a651f7e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -231,6 +231,27 @@ static void radeon_enc_session_init(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
+{
+   enc->enc_pic.session_init.encode_standard = 
RENCODE_ENCODE_STANDARD_HEVC;
+   enc->enc_pic.session_init.aligned_picture_width = 
align(enc->base.width, 64);
+   enc->enc_pic.session_init.aligned_picture_height = 
align(enc->base.height, 16);
+   enc->enc_pic.session_init.padding_width = 
enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
+   enc->enc_pic.session_init.padding_height = 
enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
+   enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
+   enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
+
+   RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
+   RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 {
enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
@@ -262,6 +283,19 @@ static void radeon_enc_slice_control(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
+{
+   enc->enc_pic.hevc_slice_ctrl.slice_control_mode = 
RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
+   enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = 
align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
+   
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = 
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
+
+   RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
+   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
 {
enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
@@ -283,27 +317,68 @@ static void radeon_enc_spec_misc(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
+{
+   struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
+   enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 = 
pic->seq.log2_min_luma_coding_block_size_minus3;
+   enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
+   enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = 
pic->seq.strong_intra_smoothing_enabled_flag;
+   enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = 
pic->pic.constrained_intra_pred_flag;
+   enc->enc_pic.hevc_spec_misc.cabac_init_flag = 
pic->slice.cabac_init_flag;
+   enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
+   enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
+
+   RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SPEC_MISC);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
 {
-   struct pipe_h264_enc_picture_desc *pic = (struct 
pipe_h264_enc_picture_desc *)picture;
-

[Mesa-dev] [PATCH 04/12] radeon/vcn: add ib implementations for HEVC

2018-01-25 Thread boyuan.zhang

From: Boyuan Zhang 

Implement required ibs for vcn HEVC encode.

Signed-off-by: Boyuan Zhang 
---
 src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c | 267 
 1 file changed, 222 insertions(+), 45 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c 
b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
index 06b8092..a651f7e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
@@ -231,6 +231,27 @@ static void radeon_enc_session_init(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_session_init_hevc(struct radeon_encoder *enc)
+{
+   enc->enc_pic.session_init.encode_standard = 
RENCODE_ENCODE_STANDARD_HEVC;
+   enc->enc_pic.session_init.aligned_picture_width = 
align(enc->base.width, 64);
+   enc->enc_pic.session_init.aligned_picture_height = 
align(enc->base.height, 16);
+   enc->enc_pic.session_init.padding_width = 
enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
+   enc->enc_pic.session_init.padding_height = 
enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
+   enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
+   enc->enc_pic.session_init.pre_encode_chroma_enabled = false;
+
+   RADEON_ENC_BEGIN(RENCODE_IB_PARAM_SESSION_INIT);
+   RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
+   RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
+   RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_layer_control(struct radeon_encoder *enc)
 {
enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1;
@@ -262,6 +283,19 @@ static void radeon_enc_slice_control(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc)
+{
+   enc->enc_pic.hevc_slice_ctrl.slice_control_mode = 
RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS;
+   enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = 
align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64;
+   
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = 
enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice;
+
+   RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SLICE_CONTROL);
+   RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_spec_misc(struct radeon_encoder *enc)
 {
enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
@@ -283,27 +317,68 @@ static void radeon_enc_spec_misc(struct radeon_encoder 
*enc)
RADEON_ENC_END();
 }
 
+static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
+{
+   struct pipe_h265_enc_picture_desc *pic = (struct 
pipe_h265_enc_picture_desc *)picture;
+   enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 = 
pic->seq.log2_min_luma_coding_block_size_minus3;
+   enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
+   enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled = 
pic->seq.strong_intra_smoothing_enabled_flag;
+   enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag = 
pic->pic.constrained_intra_pred_flag;
+   enc->enc_pic.hevc_spec_misc.cabac_init_flag = 
pic->slice.cabac_init_flag;
+   enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
+   enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
+
+   RADEON_ENC_BEGIN(RENCODE_HEVC_IB_PARAM_SPEC_MISC);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled);
+   
RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled);
+   RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled);
+   RADEON_ENC_END();
+}
+
 static void radeon_enc_rc_session_init(struct radeon_encoder *enc, struct 
pipe_picture_desc *picture)
 {
-   struct pipe_h264_enc_picture_desc *pic = (struct 
pipe_h264_enc_picture_desc *)picture;
-   switch(pic->rate_ctrl.rate_ctrl_method) {
-

[Mesa-dev] [PATCH 04/12] radeon/vcn: add ib implementations for HEVC

[Mesa-dev] [PATCH 04/12] radeon/vcn: add ib implementations for HEVC

2 matches

Site Navigation

Mail list logo

Footer information