From: Marek Olšák <marek.ol...@amd.com>
The other codepaths don't need this.
---
src/gallium/drivers/radeonsi/si_state_draw.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 8f5dcbc..ca28f50 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1079,30 +1079,29 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
start_offset = start * ib.index_size;
u_upload_data(ctx->stream_uploader, start_offset,
count * ib.index_size,
256, (char*)ib.user_buffer + start_offset,
&ib.offset, &ib.buffer);
if (!ib.buffer)
return;
/* info->start will be added by the drawing code */
ib.offset -= start_offset;
+ } else if (sctx->b.chip_class <= CIK &&
+ r600_resource(ib.buffer)->TC_L2_dirty) {
+ /* VI reads index buffers through TC L2, so it doesn't
+ * need this. */
+ sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
+ r600_resource(ib.buffer)->TC_L2_dirty = false;
}
}
- /* VI reads index buffers through TC L2. */
- if (info->indexed && sctx->b.chip_class <= CIK &&
- r600_resource(ib.buffer)->TC_L2_dirty) {
- sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
- r600_resource(ib.buffer)->TC_L2_dirty = false;
- }
-
if (info->indirect) {
/* Add the buffer size for memory checking in need_cs_space. */
r600_context_add_resource_size(ctx, info->indirect);
if (r600_resource(info->indirect)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(info->indirect)->TC_L2_dirty = false;
}
if (info->indirect_params &&
--
2.7.4
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