From: Dave Airlie <airl...@redhat.com> AMDVLK says 16 for pre-GFX9 and 64 for GFX9.
This seems to help fix: https://bugs.freedesktop.org/show_bug.cgi?id=105464 on Polaris. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464 Signed-off-by: Dave Airlie <airl...@redhat.com> --- src/amd/vulkan/radv_pipeline.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index f8f09a7e166..3fe4559dcfe 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1317,7 +1317,7 @@ calculate_tess_state(struct radv_pipeline *pipeline, unsigned input_patch_size, output_patch_size, output_patch0_offset; unsigned lds_size, hardware_lds_size; unsigned perpatch_output_offset; - unsigned num_patches; + unsigned num_patches, hw_optimal; struct radv_tessellation_state tess = {0}; /* This calculates how shader inputs and outputs among VS, TCS, and TES @@ -1357,9 +1357,13 @@ calculate_tess_state(struct radv_pipeline *pipeline, output_patch_size); /* Not necessary for correctness, but improves performance. The - * specific value is taken from the proprietary driver. + * specific value is taken from the AMDVLK driver. */ - num_patches = MIN2(num_patches, 40); + if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) + hw_optimal = 64; + else + hw_optimal = 16; + num_patches = MIN2(num_patches, hw_optimal); /* SI bug workaround - limit LS-HS threadgroups to only one wave. */ if (pipeline->device->physical_device->rad_info.chip_class == SI) { -- 2.14.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
