From: Marek Olšák <marek.ol...@amd.com>

The clear code is exactly the same as for 1 sample buffers -
just clear the whole thing.
---
 src/gallium/drivers/radeonsi/si_clear.c   | 13 +++++++------
 src/gallium/drivers/radeonsi/si_pipe.c    |  5 +----
 src/gallium/drivers/radeonsi/si_pipe.h    |  1 -
 src/gallium/drivers/radeonsi/si_texture.c | 15 ++++++++++++---
 4 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_clear.c 
b/src/gallium/drivers/radeonsi/si_clear.c
index b08a9558b4d..f2df9483c12 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -204,33 +204,34 @@ void vi_dcc_clear_level(struct si_context *sctx,
                dcc_buffer = &rtex->dcc_separate_buffer->b.b;
                dcc_offset = 0;
        } else {
                dcc_buffer = &rtex->resource.b.b;
                dcc_offset = rtex->dcc_offset;
        }
 
        if (sctx->chip_class >= GFX9) {
                /* Mipmap level clears aren't implemented. */
                assert(rtex->resource.b.b.last_level == 0);
-               /* MSAA needs a different clear size. */
-               assert(rtex->resource.b.b.nr_samples <= 1);
+               /* 4x and 8x MSAA needs a sophisticated compute shader for
+                * the clear. See AMDVLK. */
+               assert(rtex->resource.b.b.nr_samples <= 2);
                clear_size = rtex->surface.dcc_size;
        } else {
                unsigned num_layers = util_num_layers(&rtex->resource.b.b, 
level);
 
                /* If this is 0, fast clear isn't possible. (can occur with 
MSAA) */
                assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
-               /* Layered MSAA DCC fast clears need to clear 
dcc_fast_clear_size
-                * bytes for each layer. This is not currently implemented, and
-                * therefore MSAA DCC isn't even enabled with multiple layers.
+               /* Layered 4x and 8x MSAA DCC fast clears need to clear
+                * dcc_fast_clear_size bytes for each layer. A compute shader
+                * would be more efficient than separate per-layer clear 
operations.
                 */
-               assert(rtex->resource.b.b.nr_samples <= 1 || num_layers == 1);
+               assert(rtex->resource.b.b.nr_samples <= 2 || num_layers == 1);
 
                dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
                clear_size = 
rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
                             num_layers;
        }
 
        si_clear_buffer(sctx, dcc_buffer, dcc_offset, clear_size,
                        clear_value, SI_COHERENCY_CB_META);
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 466546b76b7..a10f1c9f794 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -83,21 +83,20 @@ static const struct debug_named_value debug_options[] = {
        { "dpbb", DBG(DPBB), "Enable DPBB." },
        { "dfsm", DBG(DFSM), "Enable DFSM." },
        { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
        { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
        { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
        { "notiling", DBG(NO_TILING), "Disable tiling" },
        { "nodcc", DBG(NO_DCC), "Disable DCC." },
        { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
        { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main 
framebuffer" },
        { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
-       { "dccmsaa", DBG(DCC_MSAA), "Enable DCC for MSAA" },
        { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
 
        /* Tests: */
        { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
        { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and 
exit." },
        { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault 
test and exit." },
        { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM 
fault test and exit." },
 
        DEBUG_NAMED_VALUE_END /* must be last */
 };
@@ -1004,23 +1003,21 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
                sscreen->has_rbplus = true;
 
                sscreen->rbplus_allowed =
                        !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
                        (sscreen->info.family == CHIP_STONEY ||
                         sscreen->info.family == CHIP_VEGA12 ||
                         sscreen->info.family == CHIP_RAVEN);
        }
 
        sscreen->dcc_msaa_allowed =
-               !(sscreen->debug_flags & DBG(NO_DCC_MSAA)) &&
-               (sscreen->debug_flags & DBG(DCC_MSAA) ||
-                sscreen->info.chip_class == VI);
+               !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
 
        sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
 
        (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
        sscreen->use_monolithic_shaders =
                (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
 
        sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
                                            SI_CONTEXT_INV_VMEM_L1;
        if (sscreen->info.chip_class <= VI) {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index 351c9f4cd38..f73e0d1aac3 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -147,21 +147,20 @@ enum {
        DBG_DPBB,
        DBG_DFSM,
        DBG_NO_HYPERZ,
        DBG_NO_RB_PLUS,
        DBG_NO_2D_TILING,
        DBG_NO_TILING,
        DBG_NO_DCC,
        DBG_NO_DCC_CLEAR,
        DBG_NO_DCC_FB,
        DBG_NO_DCC_MSAA,
-       DBG_DCC_MSAA,
        DBG_NO_FMASK,
 
        /* Tests: */
        DBG_TEST_DMA,
        DBG_TEST_VMFAULT_CP,
        DBG_TEST_VMFAULT_SDMA,
        DBG_TEST_VMFAULT_SHADER,
 };
 
 #define DBG_ALL_SHADERS                (((1 << (DBG_CS + 1)) - 1))
diff --git a/src/gallium/drivers/radeonsi/si_texture.c 
b/src/gallium/drivers/radeonsi/si_texture.c
index b41a0d1b925..675e78766ad 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -261,23 +261,32 @@ static int si_init_surface(struct si_screen *sscreen,
                        flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
                }
 
                if (is_stencil)
                        flags |= RADEON_SURF_SBUFFER;
        }
 
        if (sscreen->info.chip_class >= VI &&
            (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC ||
             ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
-            /* DCC MSAA array textures are disallowed due to incomplete clear 
impl. */
-            (ptex->nr_samples >= 2 &&
-             (!sscreen->dcc_msaa_allowed || ptex->array_size > 1))))
+            (ptex->nr_samples >= 2 && !sscreen->dcc_msaa_allowed)))
+               flags |= RADEON_SURF_DISABLE_DCC;
+
+       /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
+       if (sscreen->info.chip_class == VI &&
+           ptex->nr_samples >= 4 &&
+           ptex->array_size > 1)
+               flags |= RADEON_SURF_DISABLE_DCC;
+
+       /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
+       if (sscreen->info.chip_class >= GFX9 &&
+           ptex->nr_samples >= 4)
                flags |= RADEON_SURF_DISABLE_DCC;
 
        if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
                /* This should catch bugs in gallium users setting incorrect 
flags. */
                assert(ptex->nr_samples <= 1 &&
                       ptex->array_size == 1 &&
                       ptex->depth0 == 1 &&
                       ptex->last_level == 0 &&
                       !(flags & RADEON_SURF_Z_OR_SBUFFER));
 
-- 
2.17.0

_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Reply via email to