Re: [Mesa-dev] [PATCH v2] i965: Add and use a single miptree aux_buf field

2018-04-23 Thread Jason Ekstrand 

Rb

On April 23, 2018 20:14:36 Nanley Chery  wrote:


We want to add and use a function that accesses the auxiliary buffer's
clear_color_bo and doesn't care if it has an MCS or HiZ buffer
specifically.

v2 (Jason Ekstrand):
* Drop intel_miptree_get_aux_buffer().
* Mention CCS in the aux_buf field.
---
src/mesa/drivers/dri/i965/brw_blorp.c|  16 ++--
src/mesa/drivers/dri/i965/brw_clear.c|   4 +-
src/mesa/drivers/dri/i965/brw_wm.c   |   2 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  11 ++-
src/mesa/drivers/dri/i965/gen6_depth_state.c |   6 +-
src/mesa/drivers/dri/i965/gen7_misc_state.c  |   4 +-
src/mesa/drivers/dri/i965/gen8_depth_state.c |   6 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 106 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  53 +---
src/mesa/drivers/dri/i965/intel_tex_image.c  |   2 +-
10 files changed, 96 insertions(+), 114 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c

index 962a316c5cf..37fca5e9d31 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -168,21 +168,19 @@ blorp_surf_for_miptree(struct brw_context *brw,
   */
  surf->clear_color = mt->fast_clear_color;

-  struct intel_miptree_aux_buffer *aux_buf =
- intel_miptree_get_aux_buffer(mt);
-  surf->aux_surf = _buf->surf;
+  surf->aux_surf = >aux_buf->surf;
  surf->aux_addr = (struct blorp_address) {
 .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
 .mocs = surf->addr.mocs,
  };

-  surf->aux_addr.buffer = aux_buf->bo;
-  surf->aux_addr.offset = aux_buf->offset;
+  surf->aux_addr.buffer = mt->aux_buf->bo;
+  surf->aux_addr.offset = mt->aux_buf->offset;

  if (devinfo->gen >= 10) {
 surf->clear_color_addr = (struct blorp_address) {
-.buffer = aux_buf->clear_color_bo,
-.offset = aux_buf->clear_color_offset,
+.buffer = mt->aux_buf->clear_color_bo,
+.offset = mt->aux_buf->clear_color_offset,
 };
  }
   } else {
@@ -1212,7 +1210,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,


   /* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
*/
-   if (can_fast_clear && !irb->mt->mcs_buf) {
+   if (can_fast_clear && !irb->mt->aux_buf) {
  assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
  if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
 /* There are a few reasons in addition to out-of-memory, that can
@@ -1611,7 +1609,7 @@ intel_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,

   brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
   }

-   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->hiz_buf);
+   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);

   struct isl_surf isl_tmp[2];
   struct blorp_surf surf;
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c

index 487de9b8997..3d540d6d905 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -240,7 +240,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
  * buffer when doing a fast clear. Since we are skipping the fast
  * clear here, we need to update the clear color ourselves.
  */
- uint32_t clear_offset = mt->hiz_buf->clear_color_offset;
+ uint32_t clear_offset = mt->aux_buf->clear_color_offset;
 union isl_color_value clear_color = { .f32 = { clear_value, } };

 /* We can't update the clear color while the hardware is still using
@@ -249,7 +249,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
  */
 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
 for (int i = 0; i < 4; i++) {
-brw_store_data_imm32(brw, mt->hiz_buf->clear_color_bo,
+brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
 clear_offset + i * 4, clear_color.u32[i]);
 }
 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c

index 68d4ab88d77..94048cd758f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -384,7 +384,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
 if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) {
assert(devinfo->gen >= 7);
assert(intel_tex->mt->surf.samples > 1);
-assert(intel_tex->mt->mcs_buf);
+assert(intel_tex->mt->aux_buf);
assert(intel_tex->mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
key->compressed_multisample_layout_mask |= 1 << s;

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c

[Mesa-dev] [PATCH v2] i965: Add and use a single miptree aux_buf field

2018-04-23 Thread Nanley Chery 
We want to add and use a function that accesses the auxiliary buffer's
clear_color_bo and doesn't care if it has an MCS or HiZ buffer
specifically.

v2 (Jason Ekstrand):
* Drop intel_miptree_get_aux_buffer().
* Mention CCS in the aux_buf field.
---
 src/mesa/drivers/dri/i965/brw_blorp.c|  16 ++--
 src/mesa/drivers/dri/i965/brw_clear.c|   4 +-
 src/mesa/drivers/dri/i965/brw_wm.c   |   2 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |  11 ++-
 src/mesa/drivers/dri/i965/gen6_depth_state.c |   6 +-
 src/mesa/drivers/dri/i965/gen7_misc_state.c  |   4 +-
 src/mesa/drivers/dri/i965/gen8_depth_state.c |   6 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 106 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h|  53 +---
 src/mesa/drivers/dri/i965/intel_tex_image.c  |   2 +-
 10 files changed, 96 insertions(+), 114 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 962a316c5cf..37fca5e9d31 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -168,21 +168,19 @@ blorp_surf_for_miptree(struct brw_context *brw,
*/
   surf->clear_color = mt->fast_clear_color;
 
-  struct intel_miptree_aux_buffer *aux_buf =
- intel_miptree_get_aux_buffer(mt);
-  surf->aux_surf = _buf->surf;
+  surf->aux_surf = >aux_buf->surf;
   surf->aux_addr = (struct blorp_address) {
  .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0,
  .mocs = surf->addr.mocs,
   };
 
-  surf->aux_addr.buffer = aux_buf->bo;
-  surf->aux_addr.offset = aux_buf->offset;
+  surf->aux_addr.buffer = mt->aux_buf->bo;
+  surf->aux_addr.offset = mt->aux_buf->offset;
 
   if (devinfo->gen >= 10) {
  surf->clear_color_addr = (struct blorp_address) {
-.buffer = aux_buf->clear_color_bo,
-.offset = aux_buf->clear_color_offset,
+.buffer = mt->aux_buf->clear_color_bo,
+.offset = mt->aux_buf->clear_color_offset,
  };
   }
} else {
@@ -1212,7 +1210,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
 
/* If the MCS buffer hasn't been allocated yet, we need to allocate it now.
 */
-   if (can_fast_clear && !irb->mt->mcs_buf) {
+   if (can_fast_clear && !irb->mt->aux_buf) {
   assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
   if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
  /* There are a few reasons in addition to out-of-memory, that can
@@ -1611,7 +1609,7 @@ intel_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
}
 
-   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->hiz_buf);
+   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ && mt->aux_buf);
 
struct isl_surf isl_tmp[2];
struct blorp_surf surf;
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 487de9b8997..3d540d6d905 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -240,7 +240,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
   * buffer when doing a fast clear. Since we are skipping the fast
   * clear here, we need to update the clear color ourselves.
   */
- uint32_t clear_offset = mt->hiz_buf->clear_color_offset;
+ uint32_t clear_offset = mt->aux_buf->clear_color_offset;
  union isl_color_value clear_color = { .f32 = { clear_value, } };
 
  /* We can't update the clear color while the hardware is still using
@@ -249,7 +249,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
   */
  brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
  for (int i = 0; i < 4; i++) {
-brw_store_data_imm32(brw, mt->hiz_buf->clear_color_bo,
+brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
  clear_offset + i * 4, clear_color.u32[i]);
  }
  brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index 68d4ab88d77..94048cd758f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -384,7 +384,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx,
  if (intel_tex->mt->aux_usage == ISL_AUX_USAGE_MCS) {
 assert(devinfo->gen >= 7);
 assert(intel_tex->mt->surf.samples > 1);
-assert(intel_tex->mt->mcs_buf);
+assert(intel_tex->mt->aux_buf);
 assert(intel_tex->mt->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY);
 key->compressed_multisample_layout_mask |= 1 << s;
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index